1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * Copyright (c) 2017-2023 Nuvoton Technology Corp. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <drivers/arm/gic_common.h> 16 #include <lib/utils_def.h> 17 #include <lib/xlat_tables/xlat_tables_defs.h> 18 #include <npcm845x_arm_def.h> 19 #include <plat/arm/common/smccc_def.h> 20 #include <plat/common/common_def.h> 21 22 #define VALUE_TO_STRING(x) #x 23 #define VALUE(x) VALUE_TO_STRING(x) 24 #define VAR_NAME_VALUE(var) #var "=" VALUE(var) 25 26 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 27 #define PLATFORM_LINKER_ARCH aarch64 28 29 #define PLATFORM_STACK_SIZE 0x400 30 31 #define PLATFORM_CORE_COUNT NPCM845x_PLATFORM_CORE_COUNT 32 #define PLATFORM_CLUSTER_COUNT NPCM845x_CLUSTER_COUNT 33 #define PLATFORM_MAX_CPU_PER_CLUSTER NPCM845x_MAX_CPU_PER_CLUSTER 34 #define PLAT_PRIMARY_CPU NPCM845x_PLAT_PRIMARY_CPU 35 #define PLATFORM_SYSTEM_COUNT NPCM845x_SYSTEM_COUNT 36 37 /* Local power state for power domains in Run state. */ 38 #define PLAT_LOCAL_STATE_RUN U(0) 39 /* Local power state for retention. Valid only for CPU power domains */ 40 #define PLAT_LOCAL_STATE_RET U(1) 41 /* 42 * Local power state for OFF/power-down. Valid for CPU and cluster power 43 * domains. 44 */ 45 #define PLAT_LOCAL_STATE_OFF U(2) 46 47 /* 48 * This macro defines the deepest power down states possible. Any state ID 49 * higher than this is invalid. 50 */ 51 #define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF 52 #define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET 53 54 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) 55 #define NPCM845x_MAX_PWR_LVL ARM_PWR_LVL1 56 57 /* 58 * Macros used to parse state information from State-ID if it is using the 59 * recommended encoding for State-ID. 60 */ 61 #define PLAT_LOCAL_PSTATE_WIDTH 4 62 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 63 64 /* 65 * Required ARM standard platform porting definitions 66 */ 67 #define PLAT_ARM_CLUSTER_COUNT PLATFORM_CLUSTER_COUNT 68 69 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) 70 #define PLAT_MAX_PWR_LVL NPCM845x_MAX_PWR_LVL 71 72 #define PLAT_LOCAL_PSTATE_WIDTH 4 73 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 74 75 #ifdef BL32_BASE 76 77 #ifndef CONFIG_TARGET_ARBEL_PALLADIUM 78 #define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE 79 #else 80 #define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE 81 #endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ 82 83 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 84 #endif /* BL32_BASE */ 85 86 #define PWR_DOMAIN_AT_MAX_LVL U(1) 87 88 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 89 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 90 #define MAX_XLAT_TABLES 16 91 #define PLAT_ARM_MMAP_ENTRIES 17 92 93 #ifdef NPCM845X_DEBUG 94 #define MAX_MMAP_REGIONS 8 95 #define NPCM845X_TZ1_BASE 0xFFFB0000 96 #endif /* NPCM845X_DEBUG */ 97 98 #define FIQ_SMP_CALL_SGI 10 99 100 /* (0x00040000) 128 KB, the rest 128K if it is non secured */ 101 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00020000) 102 103 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 104 105 /* UL(0xfffCE000) add calc ARM_TRUSTED_SRAM_BASE */ 106 #define ARM_SHARED_RAM_BASE (BL31_BASE + 0x00020000 - ARM_SHARED_RAM_SIZE) 107 108 /* The remaining Trusted SRAM is used to load the BL images */ 109 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE) 110 111 /* 112 * PLAT_ARM_TRUSTED_SRAM_SIZE is taken from platform_def.h 0x20000 113 * because only half is secured in this specific implementation 114 */ 115 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) 116 117 #if RESET_TO_BL31 118 /* Size of Trusted SRAM - the first 4KB of shared memory */ 119 #define PLAT_ARM_MAX_BL31_SIZE \ 120 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) 121 #else 122 /* 123 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE 124 * is calculated using the current BL31 PROGBITS debug size plus the sizes 125 * of BL2 and BL1-RW 126 */ 127 #define PLAT_ARM_MAX_BL31_SIZE \ 128 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) 129 #endif /* RESET_TO_BL31 */ 130 /* 131 * Load address of BL33 for this platform port 132 */ 133 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x6208000)) 134 135 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 136 137 /* GIC parameters */ 138 139 /* Base compatible GIC memory map */ 140 #define NT_GIC_BASE (0xDFFF8000) 141 #define BASE_GICD_BASE (NT_GIC_BASE + 0x1000) 142 #define BASE_GICC_BASE (NT_GIC_BASE + 0x2000) 143 #define BASE_GICR_BASE (NT_GIC_BASE + 0x200000) 144 #define BASE_GICH_BASE (NT_GIC_BASE + 0x4000) 145 #define BASE_GICV_BASE (NT_GIC_BASE + 0x6000) 146 147 #define DEVICE1_BASE BASE_GICD_BASE 148 #define DEVICE1_SIZE 0x7000 149 150 #ifdef NPCM845X_DEBUG 151 /* ((BASE_GICR_BASE - BASE_GICD_BASE) + (PLATFORM_CORE_COUNT * 0x20000)) */ 152 #define ARM_CPU_START_ADDRESS(m) UL(0xf0800e00 + 0x10 + m * 4) 153 #endif /* NPCM845X_DEBUG */ 154 155 #define PLAT_REG_BASE NPCM845x_REG_BASE 156 #define PLAT_REG_SIZE NPCM845x_REG_SIZE 157 158 /* MMU entry for internal (register) space access */ 159 #define MAP_DEVICE0 \ 160 MAP_REGION_FLAT(PLAT_REG_BASE, PLAT_REG_SIZE, MT_DEVICE | MT_RW | MT_NS) 161 162 #define MAP_DEVICE1 \ 163 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, \ 164 MT_DEVICE | MT_RW | MT_SECURE) 165 166 /* 167 * Define a list of Group 1 Secure and Group 0 interrupt properties 168 * as per GICv3 terminology. On a GICv2 system or mode, 169 * the lists will be merged and treated as Group 0 interrupts. 170 */ 171 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 172 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 173 174 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 175 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 176 GIC_INTR_CFG_LEVEL), \ 177 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 178 grp, GIC_INTR_CFG_EDGE), \ 179 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 180 grp, GIC_INTR_CFG_EDGE), \ 181 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 182 grp, GIC_INTR_CFG_EDGE), \ 183 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 184 grp, GIC_INTR_CFG_EDGE), \ 185 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 186 grp, GIC_INTR_CFG_EDGE), \ 187 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 188 grp, GIC_INTR_CFG_EDGE), \ 189 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 190 grp, GIC_INTR_CFG_EDGE), \ 191 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 192 grp, GIC_INTR_CFG_EDGE) 193 194 #define PLAT_ARM_G0_IRQ_PROPS(grp) 195 196 /* Required for compilation: */ 197 198 /* 199 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 200 * plus a little space for growth. 201 */ 202 #define PLAT_ARM_MAX_BL1_RW_SIZE 0 /* UL(0xB000) */ 203 #if USE_ROMLIB 204 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 205 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 206 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) 207 #else 208 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 209 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 210 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 211 #endif /* USE_ROMLIB */ 212 213 /* 214 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size 215 * plus a little space for growth. 216 */ 217 #if TRUSTED_BOARD_BOOT 218 #define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) * FVP_BL2_ROMLIB_OPTIMIZATION) 219 #else 220 /* (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) */ 221 #define PLAT_ARM_MAX_BL2_SIZE 0 222 #endif /* TRUSTED_BOARD_BOOT */ 223 224 #undef NPCM_PRINT_ONCE 225 #ifdef NPCM_PRINT_ONCE 226 #define PRINT_ONLY_ONCE 227 #pragma message(VAR_NAME_VALUE(ARM_AP_TZC_DRAM1_BASE)) 228 #pragma message(VAR_NAME_VALUE(BL31_BASE)) 229 #pragma message(VAR_NAME_VALUE(BL31_LIMIT)) 230 #pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL31_SIZE)) 231 #pragma message(VAR_NAME_VALUE(BL32_BASE)) 232 #pragma message(VAR_NAME_VALUE(BL32_LIMIT)) 233 #pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL32_SIZE) 234 #pragma message(VAR_NAME_VALUE(SPMD_SPM_AT_SEL2_KKO)) 235 #endif /* NPCM_PRINT_ONCE */ 236 237 #define MAX_IO_DEVICES 4 238 #define MAX_IO_HANDLES 4 239 240 #define PLAT_ARM_FIP_BASE 0x0 241 #define PLAT_ARM_FIP_MAX_SIZE PLAT_ARM_MAX_BL31_SIZE 242 243 #define PLAT_ARM_BOOT_UART_BASE 0xF0000000 244 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 115200 245 #define PLAT_ARM_RUN_UART_BASE 0xF0000000 246 #define PLAT_ARM_RUN_UART_CLK_IN_HZ 115200 247 #define PLAT_ARM_CRASH_UART_BASE 0xF0000000 248 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ 115200 249 250 /* 251 * Mailbox to control the secondary cores.All secondary cores are held in a wait 252 * loop in cold boot. To release them perform the following steps (plus any 253 * additional barriers that may be needed): 254 * 255 * uint64_t *entrypoint = (uint64_t *)PLAT_NPCM_TM_ENTRYPOINT; 256 * *entrypoint = ADDRESS_TO_JUMP_TO; 257 * 258 * uint64_t *mbox_entry = (uint64_t *)PLAT_NPCM_TM_HOLD_BASE; 259 * mbox_entry[cpu_id] = PLAT_NPCM_TM_HOLD_BASE; 260 * 261 * sev(); 262 */ 263 #define PLAT_NPCM_TRUSTED_MAILBOX_BASE ARM_SHARED_RAM_BASE 264 265 /* The secure entry point to be used on warm reset by all CPUs. */ 266 #define PLAT_NPCM_TM_ENTRYPOINT PLAT_NPCM_TRUSTED_MAILBOX_BASE 267 #define PLAT_NPCM_TM_ENTRYPOINT_SIZE ULL(8) 268 269 /* Hold entries for each CPU. */ 270 #define PLAT_NPCM_TM_HOLD_BASE \ 271 (PLAT_NPCM_TM_ENTRYPOINT + PLAT_NPCM_TM_ENTRYPOINT_SIZE) 272 #define PLAT_NPCM_TM_HOLD_ENTRY_SIZE ULL(8) 273 #define PLAT_NPCM_TM_HOLD_SIZE \ 274 (PLAT_NPCM_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT) 275 #define PLAT_NPCM_TRUSTED_NOTIFICATION_BASE \ 276 (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE) 277 278 #define PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE ULL(8) 279 280 #define PLAT_NPCM_TRUSTED_NOTIFICATION_SIZE \ 281 (PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE * PLATFORM_CORE_COUNT) 282 283 #define PLAT_NPCM_TRUSTED_MAILBOX_SIZE \ 284 (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE + \ 285 PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE) 286 287 #define PLAT_NPCM_TM_HOLD_STATE_WAIT ULL(0) 288 #define PLAT_NPCM_TM_HOLD_STATE_GO ULL(1) 289 #define PLAT_NPCM_TM_HOLD_STATE_BSP_OFF ULL(2) 290 291 #define PLAT_NPCM_TM_NOTIFICATION_START ULL(0xAA) 292 #define PLAT_NPCM_TM_NOTIFICATION_BR ULL(0xCC) 293 294 #ifdef NPCM845X_DEBUG 295 #define PLAT_ARM_TRUSTED_MAILBOX_BASE 0xfffB0000 296 #endif /* NPCM845X_DEBUG */ 297 298 #endif /* PLATFORM_DEF_H */ 299