1 /*
2  * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch.h>
8 #include <common/tbbr/tbbr_img_def.h>
9 #include <lib/utils_def.h>
10 #include <plat/common/common_def.h>
11 
12 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
13 #define PLATFORM_LINKER_ARCH		aarch64
14 
15 #define PLATFORM_STACK_SIZE		0xB00
16 #define CACHE_WRITEBACK_GRANULE		64
17 
18 #define PLAT_PRIMARY_CPU		U(0x0)
19 #define PLATFORM_MAX_CPU_PER_CLUSTER	U(4)
20 #define PLATFORM_CLUSTER_COUNT		U(1)
21 #define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
22 #define PLATFORM_CLUSTER1_CORE_COUNT	U(0)
23 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT)
24 
25 #define IMX_PWR_LVL0			MPIDR_AFFLVL0
26 #define IMX_PWR_LVL1			MPIDR_AFFLVL1
27 #define IMX_PWR_LVL2			MPIDR_AFFLVL2
28 
29 #define PWR_DOMAIN_AT_MAX_LVL		U(1)
30 #define PLAT_MAX_PWR_LVL		U(2)
31 #define PLAT_MAX_OFF_STATE		U(4)
32 #define PLAT_MAX_RET_STATE		U(2)
33 
34 #define PLAT_WAIT_RET_STATE		U(1)
35 #define PLAT_STOP_OFF_STATE		U(3)
36 
37 #define PLAT_PRI_BITS			U(3)
38 #define PLAT_SDEI_CRITICAL_PRI		0x10
39 #define PLAT_SDEI_NORMAL_PRI		0x20
40 #define PLAT_SDEI_SGI_PRIVATE		U(9)
41 
42 #if defined(NEED_BL2)
43 #define BL2_BASE			U(0x920000)
44 #define BL2_SIZE			SZ_128K
45 #define BL2_LIMIT			(BL2_BASE + BL2_SIZE)
46 #define BL31_BASE			U(0x900000)
47 #define IMX_FIP_BASE			U(0x40310000)
48 #define IMX_FIP_SIZE			U(0x000300000)
49 #define IMX_FIP_LIMIT			U(FIP_BASE + FIP_SIZE)
50 
51 /* Define FIP image location on eMMC */
52 #define IMX_FIP_MMC_BASE		U(0x100000)
53 
54 #define PLAT_IMX8MM_BOOT_MMC_BASE	U(0x30B50000) /* SD */
55 #else
56 #define BL31_BASE			U(0x920000)
57 #endif
58 
59 #define BL31_SIZE			SZ_128K
60 #define BL31_LIMIT			(BL31_BASE + BL31_SIZE)
61 
62 /* non-secure uboot base */
63 #ifndef PLAT_NS_IMAGE_OFFSET
64 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
65 #endif
66 #define PLAT_NS_IMAGE_SIZE		U(0x00200000)
67 
68 #define BL32_FDT_OVERLAY_ADDR		(PLAT_NS_IMAGE_OFFSET + 0x3000000)
69 
70 /* GICv3 base address */
71 #define PLAT_GICD_BASE			U(0x38800000)
72 #define PLAT_GICR_BASE			U(0x38880000)
73 
74 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
75 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
76 
77 #define MAX_XLAT_TABLES			8
78 #define MAX_MMAP_REGIONS		16
79 
80 #define HAB_RVT_BASE			U(0x00000900) /* HAB_RVT for i.MX8MM */
81 
82 #define IMX_BOOT_UART_CLK_IN_HZ		24000000 /* Select 24MHz oscillator */
83 
84 #define PLAT_CRASH_UART_BASE		IMX_BOOT_UART_BASE
85 #define PLAT_CRASH_UART_CLK_IN_HZ	24000000
86 #define IMX_CONSOLE_BAUDRATE		115200
87 
88 #define IMX_AIPSTZ1			U(0x301f0000)
89 #define IMX_AIPSTZ2			U(0x305f0000)
90 #define IMX_AIPSTZ3			U(0x309f0000)
91 #define IMX_AIPSTZ4			U(0x32df0000)
92 
93 #define IMX_AIPS_BASE			U(0x30000000)
94 #define IMX_AIPS_SIZE			U(0x3000000)
95 #define IMX_GPV_BASE			U(0x32000000)
96 #define IMX_GPV_SIZE			U(0x800000)
97 #define IMX_AIPS1_BASE			U(0x30200000)
98 #define IMX_AIPS4_BASE			U(0x32c00000)
99 #define IMX_ANAMIX_BASE			U(0x30360000)
100 #define IMX_CCM_BASE			U(0x30380000)
101 #define IMX_SRC_BASE			U(0x30390000)
102 #define IMX_GPC_BASE			U(0x303a0000)
103 #define IMX_RDC_BASE			U(0x303d0000)
104 #define IMX_CSU_BASE			U(0x303e0000)
105 #define IMX_WDOG_BASE			U(0x30280000)
106 #define IMX_SNVS_BASE			U(0x30370000)
107 #define IMX_NOC_BASE			U(0x32700000)
108 #define IMX_TZASC_BASE			U(0x32F80000)
109 #define IMX_IOMUX_GPR_BASE		U(0x30340000)
110 #define IMX_CAAM_BASE			U(0x30900000)
111 #define IMX_DDRC_BASE			U(0x3d400000)
112 #define IMX_DDRPHY_BASE			U(0x3c000000)
113 #define IMX_DDR_IPS_BASE		U(0x3d000000)
114 #define IMX_DDR_IPS_SIZE		U(0x1800000)
115 #define IMX_VPUMIX_BASE			U(0x38330000)
116 #define IMX_VPUMIX_SIZE			U(0x100000)
117 #define IMX_ROM_BASE			U(0x0)
118 #define IMX_ROM_SIZE			U(0x40000)
119 #define IMX_NS_OCRAM_BASE		U(0x900000)
120 #define IMX_NS_OCRAM_SIZE		U(0x20000)
121 #define IMX_CAAM_RAM_BASE		U(0x100000)
122 #define IMX_CAAM_RAM_SIZE		U(0x10000)
123 #define IMX_DRAM_BASE			U(0x40000000)
124 #define IMX_DRAM_SIZE			U(0xc0000000)
125 
126 #define GPV_BASE			U(0x32000000)
127 #define GPV_SIZE			U(0x800000)
128 #define IMX_GIC_BASE			PLAT_GICD_BASE
129 #define IMX_GIC_SIZE			U(0x200000)
130 
131 #define WDOG_WSR			U(0x2)
132 #define WDOG_WCR_WDZST			BIT(0)
133 #define WDOG_WCR_WDBG			BIT(1)
134 #define WDOG_WCR_WDE			BIT(2)
135 #define WDOG_WCR_WDT			BIT(3)
136 #define WDOG_WCR_SRS			BIT(4)
137 #define WDOG_WCR_WDA			BIT(5)
138 #define WDOG_WCR_SRE			BIT(6)
139 #define WDOG_WCR_WDW			BIT(7)
140 
141 #define SRC_A53RCR0			U(0x4)
142 #define SRC_A53RCR1			U(0x8)
143 #define SRC_OTG1PHY_SCR			U(0x20)
144 #define SRC_OTG2PHY_SCR			U(0x24)
145 #define SRC_GPR1_OFFSET			U(0x74)
146 #define SRC_GPR10_OFFSET		U(0x98)
147 #define SRC_GPR10_PERSIST_SECONDARY_BOOT	BIT(30)
148 
149 #define SNVS_LPCR			U(0x38)
150 #define SNVS_LPCR_SRTC_ENV		BIT(0)
151 #define SNVS_LPCR_DP_EN			BIT(5)
152 #define SNVS_LPCR_TOP			BIT(6)
153 
154 #define IOMUXC_GPR10			U(0x28)
155 #define GPR_TZASC_EN			BIT(0)
156 #define GPR_TZASC_EN_LOCK		BIT(16)
157 
158 #define ANAMIX_MISC_CTL			U(0x124)
159 #define DRAM_PLL_CTRL			(IMX_ANAMIX_BASE + 0x50)
160 
161 #define MAX_CSU_NUM			U(64)
162 
163 #define OCRAM_S_BASE			U(0x00180000)
164 #define OCRAM_S_SIZE			U(0x8000)
165 #define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
166 #define SAVED_DRAM_TIMING_BASE		OCRAM_S_BASE
167 
168 #define COUNTER_FREQUENCY		8000000 /* 8MHz */
169 
170 #define IMX_WDOG_B_RESET
171 
172 #define MAX_IO_HANDLES			3U
173 #define MAX_IO_DEVICES			2U
174 #define MAX_IO_BLOCK_DEVICES		1U
175 
176 #define PLAT_IMX8M_DTO_BASE		0x53000000
177 #define PLAT_IMX8M_DTO_MAX_SIZE		0x1000
178 #define PLAT_IMX_EVENT_LOG_MAX_SIZE	UL(0x400)
179