1 /* 2 * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 #endif 58 59 /* 60 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 61 * max size of BL32 image. 62 */ 63 #if defined(SPD_spmd) 64 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 65 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 66 #endif 67 68 /* virtual address used by dynamic mem_protect for chunk_base */ 69 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 70 71 /* No SCP in FVP */ 72 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 73 74 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 75 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 76 77 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 78 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 79 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 80 81 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 82 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 83 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 84 85 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 86 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 87 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 88 89 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 90 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 91 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 92 93 /* Range of kernel DTB load address */ 94 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 95 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 96 97 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 98 FVP_DTB_DRAM_MAP_START, \ 99 FVP_DTB_DRAM_MAP_SIZE, \ 100 MT_MEMORY | MT_RO | MT_NS) 101 102 /* 103 * On the FVP platform when using the EL3 SPMC implementation allocate the 104 * datastore for tracking shared memory descriptors in the TZC DRAM section 105 * to ensure sufficient storage can be allocated. 106 * Provide an implementation of the accessor method to allow the datastore 107 * details to be retrieved by the SPMC. 108 * The SPMC will take care of initializing the memory region. 109 */ 110 111 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 112 113 /* Define memory configuration for device tree files. */ 114 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 115 116 #if SPMC_AT_EL3 117 /* 118 * Number of Secure Partitions supported. 119 * SPMC at EL3, uses this count to configure the maximum number of supported 120 * secure partitions. 121 */ 122 #define SECURE_PARTITION_COUNT 1 123 124 /* 125 * Number of Normal World Partitions supported. 126 * SPMC at EL3, uses this count to configure the maximum number of supported 127 * NWd partitions. 128 */ 129 #define NS_PARTITION_COUNT 1 130 131 /* 132 * Number of Logical Partitions supported. 133 * SPMC at EL3, uses this count to configure the maximum number of supported 134 * logical partitions. 135 */ 136 #define MAX_EL3_LP_DESCS_COUNT 1 137 138 #endif /* SPMC_AT_EL3 */ 139 140 /* 141 * Load address of BL33 for this platform port 142 */ 143 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 144 145 #if TRANSFER_LIST 146 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x5000) 147 148 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 149 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 150 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 151 152 #else 153 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 154 #endif 155 156 /* 157 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 158 * plat_arm_mmap array defined for each BL stage. 159 */ 160 #if defined(IMAGE_BL31) 161 # if SPM_MM 162 # define PLAT_ARM_MMAP_ENTRIES 10 163 # define MAX_XLAT_TABLES 9 164 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 165 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 166 # elif SPMC_AT_EL3 167 # define PLAT_ARM_MMAP_ENTRIES 13 168 # define MAX_XLAT_TABLES 11 169 # else 170 # define PLAT_ARM_MMAP_ENTRIES 9 171 # if USE_DEBUGFS 172 # if ENABLE_RME 173 # define MAX_XLAT_TABLES 9 174 # else 175 # define MAX_XLAT_TABLES 8 176 # endif 177 # else 178 # if ENABLE_RME 179 # define MAX_XLAT_TABLES 8 180 # elif DRTM_SUPPORT 181 # define MAX_XLAT_TABLES 8 182 # else 183 # define MAX_XLAT_TABLES 7 184 # endif 185 # endif 186 # endif 187 #elif defined(IMAGE_BL32) 188 # if SPMC_AT_EL3 189 # define PLAT_ARM_MMAP_ENTRIES 270 190 # define MAX_XLAT_TABLES 10 191 # else 192 # define PLAT_ARM_MMAP_ENTRIES 9 193 # define MAX_XLAT_TABLES 6 194 # endif 195 #elif !USE_ROMLIB 196 # if ENABLE_RME && defined(IMAGE_BL2) 197 # define PLAT_ARM_MMAP_ENTRIES 12 198 # define MAX_XLAT_TABLES 6 199 # else 200 # define PLAT_ARM_MMAP_ENTRIES 11 201 # define MAX_XLAT_TABLES 5 202 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 203 #else 204 # define PLAT_ARM_MMAP_ENTRIES 12 205 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 206 defined(IMAGE_BL2) && MEASURED_BOOT 207 # define MAX_XLAT_TABLES 7 208 # else 209 # define MAX_XLAT_TABLES 6 210 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 211 #endif 212 213 /* 214 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 215 * plus a little space for growth. 216 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 217 * area. 218 */ 219 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO 220 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 221 #else 222 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 223 #endif 224 225 /* 226 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 227 */ 228 229 #if USE_ROMLIB 230 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 231 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 232 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 233 #else 234 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 235 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 236 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 237 #endif 238 239 /* 240 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 241 * Maximum size of BL2 increases as Trusted SRAM size increases. 242 */ 243 #if CRYPTO_SUPPORT 244 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 245 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 246 (2 * PAGE_SIZE) - \ 247 FVP_BL2_ROMLIB_OPTIMIZATION) 248 #else 249 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 250 (3 * PAGE_SIZE) - \ 251 FVP_BL2_ROMLIB_OPTIMIZATION) 252 #endif 253 #elif ARM_BL31_IN_DRAM 254 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 255 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 256 #else 257 /** 258 * Default to just under half of SRAM to ensure there's enough room for really 259 * large BL31 build configurations when using the default SRAM size (256 Kb). 260 */ 261 #define PLAT_ARM_MAX_BL2_SIZE \ 262 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 263 FVP_BL2_ROMLIB_OPTIMIZATION) 264 #endif 265 266 #if RESET_TO_BL31 267 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 268 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 269 ARM_SHARED_RAM_SIZE - \ 270 ARM_L0_GPT_SIZE) 271 #else 272 /* 273 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 274 * calculated using the current BL31 PROGBITS debug size plus the sizes of 275 * BL2 and BL1-RW. 276 * Size of the BL31 PROGBITS increases as the SRAM size increases. 277 */ 278 #if TRANSFER_LIST 279 #define PLAT_ARM_MAX_BL31_SIZE \ 280 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 281 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 282 #else 283 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 284 ARM_SHARED_RAM_SIZE - \ 285 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 286 #endif /* TRANSFER_LIST */ 287 #endif /* RESET_TO_BL31 */ 288 289 #ifndef __aarch64__ 290 #if RESET_TO_SP_MIN 291 /* Size of Trusted SRAM - the first 4KB of shared memory */ 292 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 293 ARM_SHARED_RAM_SIZE) 294 #else 295 /* 296 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 297 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 298 * BL2 and BL1-RW 299 */ 300 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 301 #endif /* RESET_TO_SP_MIN */ 302 #endif 303 304 /* 305 * Size of cacheable stacks 306 */ 307 #if defined(IMAGE_BL1) 308 # if CRYPTO_SUPPORT 309 # define PLATFORM_STACK_SIZE UL(0x1000) 310 # else 311 # define PLATFORM_STACK_SIZE UL(0x500) 312 # endif /* CRYPTO_SUPPORT */ 313 #elif defined(IMAGE_BL2) 314 # if CRYPTO_SUPPORT 315 # define PLATFORM_STACK_SIZE UL(0x1000) 316 # else 317 # define PLATFORM_STACK_SIZE UL(0x600) 318 # endif /* CRYPTO_SUPPORT */ 319 #elif defined(IMAGE_BL2U) 320 # define PLATFORM_STACK_SIZE UL(0x400) 321 #elif defined(IMAGE_BL31) 322 # if DRTM_SUPPORT 323 # define PLATFORM_STACK_SIZE UL(0x1000) 324 # else 325 # define PLATFORM_STACK_SIZE UL(0x800) 326 # endif /* DRTM_SUPPORT */ 327 #elif defined(IMAGE_BL32) 328 # if SPMC_AT_EL3 329 # define PLATFORM_STACK_SIZE UL(0x1000) 330 # else 331 # define PLATFORM_STACK_SIZE UL(0x440) 332 # endif /* SPMC_AT_EL3 */ 333 #elif defined(IMAGE_RMM) 334 # define PLATFORM_STACK_SIZE UL(0x440) 335 #endif 336 337 #define MAX_IO_DEVICES 3 338 #define MAX_IO_HANDLES 4 339 340 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 341 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 342 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 343 344 #if ARM_GPT_SUPPORT 345 /* 346 * Offset of the FIP in the GPT image. BL1 component uses this option 347 * as it does not load the partition table to get the FIP base 348 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 349 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 350 */ 351 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 352 #endif /* ARM_GPT_SUPPORT */ 353 354 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 355 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 356 357 /* 358 * PL011 related constants 359 */ 360 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 361 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 362 363 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 364 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 365 366 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 367 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 368 369 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 370 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 371 372 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 373 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 374 375 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 376 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 377 378 /* CCI related constants */ 379 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 380 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 381 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 382 383 /* CCI-500/CCI-550 on Base platform */ 384 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 385 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 386 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 387 388 /* CCN related constants. Only CCN 502 is currently supported */ 389 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 390 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 391 392 /* System timer related constants */ 393 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 394 395 /* Mailbox base address */ 396 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 397 398 399 /* TrustZone controller related constants 400 * 401 * Currently only filters 0 and 2 are connected on Base FVP. 402 * Filter 0 : CPU clusters (no access to DRAM by default) 403 * Filter 1 : not connected 404 * Filter 2 : LCDs (access to VRAM allowed by default) 405 * Filter 3 : not connected 406 * Programming unconnected filters will have no effect at the 407 * moment. These filter could, however, be connected in future. 408 * So care should be taken not to configure the unused filters. 409 * 410 * Allow only non-secure access to all DRAM to supported devices. 411 * Give access to the CPUs and Virtio. Some devices 412 * would normally use the default ID so allow that too. 413 */ 414 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 415 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 416 417 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 418 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 419 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 420 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 421 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 422 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 423 424 /* 425 * GIC related constants to cater for both GICv2 and GICv3 instances of an 426 * FVP. They could be overridden at runtime in case the FVP implements the 427 * legacy VE memory map. 428 */ 429 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 430 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 431 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 432 433 /* 434 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 435 * terminology. On a GICv2 system or mode, the lists will be merged and treated 436 * as Group 0 interrupts. 437 */ 438 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 439 ARM_G1S_IRQ_PROPS(grp), \ 440 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 441 GIC_INTR_CFG_LEVEL), \ 442 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 443 GIC_INTR_CFG_LEVEL) 444 445 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 446 447 #if SDEI_IN_FCONF 448 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 449 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 450 #else 451 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 452 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 453 ARM_SDEI_PRIVATE_EVENTS, \ 454 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 455 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 456 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 457 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 458 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 459 #else 460 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 461 #endif 462 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 463 #endif 464 465 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 466 PLAT_SP_IMAGE_NS_BUF_SIZE) 467 468 #define PLAT_SP_PRI 0x20 469 470 /* 471 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 472 */ 473 #ifdef __aarch64__ 474 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 475 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 476 #else 477 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 478 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 479 #endif 480 481 /* 482 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 483 */ 484 #if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) 485 /* Account for additional measurements of secure partitions and SPM. */ 486 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 487 #else 488 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 489 #endif 490 491 /* 492 * Maximum size of Event Log buffer used for DRTM 493 */ 494 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 495 496 /* 497 * Number of MMAP entries used by DRTM implementation 498 */ 499 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 500 501 #endif /* PLATFORM_DEF_H */ 502