1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/common/common_def.h> 11 12 #define PLATFORM_STACK_SIZE U(0x1000) 13 14 /* Caches */ 15 #define CACHE_WRITEBACK_SHIFT U(6) 16 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 17 18 /* CPU Topology */ 19 #define PLATFORM_CORE_COUNT U(4) 20 #define PLATFORM_SYSTEM_COUNT U(1) 21 #define PLATFORM_CLUSTER_COUNT U(2) 22 #define PLATFORM_PRIMARY_CPU U(0) 23 #define PLATFORM_MPIDR_CPU_MASK_BITS U(1) 24 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) 25 26 /* Power Domains */ 27 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 28 PLATFORM_CLUSTER_COUNT + \ 29 PLATFORM_CORE_COUNT) 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 31 #define PLAT_MAX_OFF_STATE U(2) 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_PWR_LVL_STATES U(2) 34 35 /* BL2 stage */ 36 #define BL2_BASE UL(0x34078000) 37 #define BL2_LIMIT UL(0x34100000) 38 39 /* BL31 stage */ 40 #define BL31_BASE UL(0x34200000) 41 #define BL31_LIMIT UL(0x34300000) 42 43 /* It is a dummy value for now, given the missing DDR */ 44 #define BL33_BASE UL(0x34500000) 45 #define BL33_LIMIT UL(0x345FF000) 46 47 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) 48 /* We'll be doing a 1:1 mapping anyway */ 49 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 36) 50 51 #define MAX_MMAP_REGIONS U(8) 52 #define MAX_XLAT_TABLES U(32) 53 54 /* Console settings */ 55 #define UART_BASE UL(0x401C8000) 56 #define UART_BAUDRATE U(115200) 57 /* FIRC clock */ 58 #define UART_CLOCK_HZ U(48000000) 59 60 #define S32G_FIP_BASE UL(0x34100000) 61 #define S32G_FIP_SIZE UL(0x100000) 62 63 #define MAX_IO_HANDLES U(2) 64 #define MAX_IO_DEVICES U(2) 65 66 /* GIC settings */ 67 #define S32G_GIC_BASE UL(0x50800000) 68 #define PLAT_GICD_BASE S32G_GIC_BASE 69 #define PLAT_GICR_BASE (S32G_GIC_BASE + UL(0x80000)) 70 71 /* Generic timer frequency; this goes directly into CNTFRQ_EL0. 72 * Its end-value is 5MHz; this is based on the assumption that 73 * GPR00[CA53_COUNTER_CLK_DIV_VAL] contains the reset value of 0x7, hence 74 * producing a divider value of 8, applied to the FXOSC frequency of 40MHz. 75 */ 76 #define COUNTER_FREQUENCY U(5000000) 77 78 #endif /* PLATFORM_DEF_H */ 79