1 /* 2 * Copyright (c) 2021-2023, Stephan Gerhold <[email protected]> 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLATFORM_DEF_H 7 #define PLATFORM_DEF_H 8 9 #include <plat/common/common_def.h> 10 11 #ifdef __aarch64__ 12 /* 13 * There is at least 1 MiB available for BL31. However, at the moment the 14 * "msm8916_entry_point" variable in the data section is read through the 15 * 64 KiB region of the "boot remapper" after reset. For simplicity, limit 16 * the end of the data section (BL31_PROGBITS_LIMIT) to 64 KiB for now and 17 * the overall limit to 128 KiB. This could be increased if needed by placing 18 * the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31. 19 */ 20 #define BL31_LIMIT (BL31_BASE + SZ_128K) 21 #define BL31_PROGBITS_LIMIT (BL31_BASE + SZ_64K) 22 #endif 23 #define BL32_LIMIT (BL32_BASE + SZ_128K) 24 25 #define CACHE_WRITEBACK_GRANULE U(64) 26 #define PLATFORM_STACK_SIZE SZ_4K 27 28 /* CPU topology: one or two clusters with 4 cores each */ 29 #ifdef PLAT_msm8939 30 #define PLATFORM_CLUSTER_COUNT U(2) 31 #else 32 #define PLATFORM_CLUSTER_COUNT U(1) 33 #endif 34 #if defined(PLAT_mdm9607) 35 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(0) /* 1 */ 36 #else 37 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2) /* 4 */ 38 #endif 39 #define PLATFORM_CPUS_PER_CLUSTER (1 << PLATFORM_CPU_PER_CLUSTER_SHIFT) 40 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 41 PLATFORM_CPUS_PER_CLUSTER) 42 43 /* Power management */ 44 #define PLATFORM_SYSTEM_COUNT U(1) 45 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 46 PLATFORM_CLUSTER_COUNT + \ 47 PLATFORM_CORE_COUNT) 48 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 49 #define PLAT_MAX_RET_STATE U(2) 50 #define PLAT_MAX_OFF_STATE U(3) 51 52 /* Translation tables */ 53 #define MAX_MMAP_REGIONS 8 54 #define MAX_XLAT_TABLES 4 55 56 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 57 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 58 59 /* Timer */ 60 #define PLAT_SYSCNT_FREQ 19200000 61 #define IRQ_SEC_PHY_TIMER (16 + 2) /* PPI #2 */ 62 63 /* 64 * The Qualcomm QGIC2 implementation seems to have PIDR0-4 and PIDR4-7 65 * erroneously swapped for some reason. PIDR2 is actually at 0xFD8. 66 * Override the address in <drivers/arm/gicv2.h> to avoid a failing assert(). 67 */ 68 #define GICD_PIDR2_GICV2 U(0xFD8) 69 70 /* TSP */ 71 #define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER 72 #define TSP_SEC_MEM_BASE BL32_BASE 73 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 74 75 #endif /* PLATFORM_DEF_H */ 76