1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_PCH_PCI_DEVS_H_ 4 #define _SOC_PCH_PCI_DEVS_H_ 5 6 #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) 7 8 #if !defined(__SIMPLE_DEVICE__) 9 #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) 10 #else 11 #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) 12 #endif 13 14 /* PCH Device info */ 15 16 #define PCH_DEV_SLOT_MROM0 0x11 17 #define PCH_DEVFN_SSATA _PCH_DEVFN(MROM0, 5) 18 #define PCH_DEV_SSATA _PCH_DEV(MROM0, 5) 19 20 #define XHCI_BUS_NUMBER 0x0 21 #define PCH_DEV_SLOT_XHCI 0x14 22 #define XHCI_FUNC_NUM 0x0 23 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) 24 #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) 25 #define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) 26 27 #define HPET_BUS_NUM 0x0 28 #define HPET_DEV_NUM PCH_DEV_SLOT_LPC 29 #define HPET0_FUNC_NUM 0x00 30 31 #define PCH_DEV_SLOT_CSE 0x16 32 #define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) 33 #define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) 34 #define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) 35 #define PCH_DEV_CSE _PCH_DEV(CSE, 0) 36 #define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) 37 #define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) 38 39 #define PCH_DEV_SLOT_SATA 0x17 40 #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) 41 #define PCH_DEV_SATA _PCH_DEV(SATA, 0) 42 #define SATAGC 0x9c 43 #define SATAGC_REGLOCK BIT(31) 44 45 #define PCH_DEV_SLOT_LPC 0x1f 46 #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) 47 #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) 48 #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) 49 #define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3) 50 #define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) 51 #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) 52 #define PCH_DEV_LPC _PCH_DEV(LPC, 0) 53 #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) 54 #define PCH_DEV_PMC _PCH_DEV(LPC, 2) 55 #define PCH_DEV_HDA _PCH_DEV(LPC, 3) 56 #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) 57 #define PCH_DEV_SPI _PCH_DEV(LPC, 5) 58 59 #define PCH_IOAPIC_BUS_NUMBER 0xF0 60 #define PCH_IOAPIC_DEV_NUM 0x1F 61 #define PCH_IOAPIC_FUNC_NUM 0x00 62 63 #endif 64