1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _I2C_PCF8523_H_ 3 #define _I2C_PCF8523_H_ 4 5 /* The address of this RTC is fixed. */ 6 #define PCF8523_SLAVE_ADR 0x68 7 8 /* Register layout */ 9 #define CTRL_REG_1 0x00 10 #define STOP_BIT (1 << 5) 11 #define CAP_SEL (1 << 7) 12 #define CTRL_REG_2 0x01 13 #define CTRL_REG_3 0x02 14 #define PM_MASK (7 << 5) 15 #define SECOND_REG 0x03 16 #define OS_BIT (1 << 7) 17 #define MINUTE_REG 0x04 18 #define HOUR_REG 0x05 19 #define DAY_REG 0x06 20 #define WEEKDAY_REG 0x07 21 #define MONTH_REG 0x08 22 #define YEAR_REG 0x09 23 #define ALARM_MINUTE_REG 0x0A 24 #define ALARM_HOUR_REG 0x0B 25 #define ALARM_DAY_REG 0x0C 26 #define ALARM_WEEKDAY_REG 0x0D 27 #define OFFSET_REG 0x0E 28 #define TMR_CLKOUT_REG 0x0F 29 #define COF_MASK 0x38 30 #define TMR_A_FREQ_REG 0x10 31 #define TMR_A_REG 0x11 32 #define TMR_B_FREQ_REG 0x12 33 #define TMR_B_REG 0x13 34 35 /* Define used capacitor modes */ 36 /* Valid for parameter cap_sel */ 37 #define CAP_SEL_7_PF 0x00 38 #define CAP_SEL_12_PF 0x01 39 40 /* Define supported power modes */ 41 /* Valid for parameter power_mode */ 42 #define PM_BAT_SW_STD_LOW_DETECT 0x00 43 #define PM_BAT_SW_DIRECT_LOW_DETECT 0x01 44 #define PM_BAT_SW_OFF_LOW_DETECT 0x02 45 #define PM_BAT_SW_STD_LOW_DETECT_OFF 0x04 46 #define PM_BAT_SW_DIRECT_LOW_DETECT_OFF 0x05 47 #define PM_BAT_SW_OFF_LOW_DETECT_OFF 0x07 48 49 /* Define CLKOUT frequency divider values */ 50 /* Valid for parameter cof_selection */ 51 #define COF_32768_HZ 0x00 52 #define COF_16384_HZ 0x01 53 #define COF_8192_HZ 0x02 54 #define COF_4096_HZ 0x03 55 #define COF_1024_HZ 0x04 56 #define COF_32_HZ 0x05 57 #define COF_1_HZ 0x06 58 #define COF_OFF 0x07 59 60 /* Define timer A & B set up values */ 61 /* Valid for parameter tmrA_prescaler and tmrB_prescaler */ 62 #define TMR_CLK_4096_HZ 0x00 63 #define TMR_CLK_64_HZ 0x01 64 #define TMR_CLK_1_HZ 0x02 65 #define TMR_CLK_1_60_HZ 0x03 66 #define TMR_CLK_1_3600_HZ 0x07 67 68 /* Valid for parameter tmrA_mode and tmrB_mode */ 69 #define TMR_DISABLED 0x00 70 #define TMR_A_MODE_COUNTDOWN 0x01 71 #define TMR_A_MODE_WATCHDOG 0x02 72 #define TMR_B_MODE_ENABLED 0x01 73 74 /* Valid for parameter tmrB_pulse_cfg */ 75 #define TMR_B_PULSE_WIDTH_46_MS 0x00 76 #define TMR_B_PULSE_WIDTH_62_MS 0x01 77 #define TMR_B_PULSE_WIDTH_78_MS 0x02 78 #define TMR_B_PULSE_WIDTH_93_MS 0x03 79 #define TMR_B_PULSE_WIDTH_125_MS 0x04 80 #define TMR_B_PULSE_WIDTH_156_MS 0x05 81 #define TMR_B_PULSE_WIDTH_187_MS 0x06 82 #define TMR_B_PULSE_WIDTH_218_MS 0x07 83 84 #endif /* _I2C_PCF8523_H_ */ 85