1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * QCOM QPIC common APIs header file 4 * 5 * Copyright (c) 2023 Qualcomm Inc. 6 * Authors: Md sadre Alam <[email protected]> 7 * 8 */ 9 #ifndef __MTD_NAND_QPIC_COMMON_H__ 10 #define __MTD_NAND_QPIC_COMMON_H__ 11 12 /* NANDc reg offsets */ 13 #define NAND_FLASH_CMD 0x00 14 #define NAND_ADDR0 0x04 15 #define NAND_ADDR1 0x08 16 #define NAND_FLASH_CHIP_SELECT 0x0c 17 #define NAND_EXEC_CMD 0x10 18 #define NAND_FLASH_STATUS 0x14 19 #define NAND_BUFFER_STATUS 0x18 20 #define NAND_DEV0_CFG0 0x20 21 #define NAND_DEV0_CFG1 0x24 22 #define NAND_DEV0_ECC_CFG 0x28 23 #define NAND_AUTO_STATUS_EN 0x2c 24 #define NAND_DEV1_CFG0 0x30 25 #define NAND_DEV1_CFG1 0x34 26 #define NAND_READ_ID 0x40 27 #define NAND_READ_STATUS 0x44 28 #define NAND_DEV_CMD0 0xa0 29 #define NAND_DEV_CMD1 0xa4 30 #define NAND_DEV_CMD2 0xa8 31 #define NAND_DEV_CMD_VLD 0xac 32 #define SFLASHC_BURST_CFG 0xe0 33 #define NAND_ERASED_CW_DETECT_CFG 0xe8 34 #define NAND_ERASED_CW_DETECT_STATUS 0xec 35 #define NAND_EBI2_ECC_BUF_CFG 0xf0 36 #define FLASH_BUF_ACC 0x100 37 38 #define NAND_CTRL 0xf00 39 #define NAND_VERSION 0xf08 40 #define NAND_READ_LOCATION_0 0xf20 41 #define NAND_READ_LOCATION_1 0xf24 42 #define NAND_READ_LOCATION_2 0xf28 43 #define NAND_READ_LOCATION_3 0xf2c 44 #define NAND_READ_LOCATION_LAST_CW_0 0xf40 45 #define NAND_READ_LOCATION_LAST_CW_1 0xf44 46 #define NAND_READ_LOCATION_LAST_CW_2 0xf48 47 #define NAND_READ_LOCATION_LAST_CW_3 0xf4c 48 49 /* dummy register offsets, used by qcom_write_reg_dma */ 50 #define NAND_DEV_CMD1_RESTORE 0xdead 51 #define NAND_DEV_CMD_VLD_RESTORE 0xbeef 52 53 /* NAND_FLASH_CMD bits */ 54 #define PAGE_ACC BIT(4) 55 #define LAST_PAGE BIT(5) 56 57 /* NAND_FLASH_CHIP_SELECT bits */ 58 #define NAND_DEV_SEL 0 59 #define DM_EN BIT(2) 60 61 /* NAND_FLASH_STATUS bits */ 62 #define FS_OP_ERR BIT(4) 63 #define FS_READY_BSY_N BIT(5) 64 #define FS_MPU_ERR BIT(8) 65 #define FS_DEVICE_STS_ERR BIT(16) 66 #define FS_DEVICE_WP BIT(23) 67 68 /* NAND_BUFFER_STATUS bits */ 69 #define BS_UNCORRECTABLE_BIT BIT(8) 70 #define BS_CORRECTABLE_ERR_MSK 0x1f 71 72 /* NAND_DEVn_CFG0 bits */ 73 #define DISABLE_STATUS_AFTER_WRITE BIT(4) 74 #define CW_PER_PAGE 6 75 #define CW_PER_PAGE_MASK GENMASK(8, 6) 76 #define UD_SIZE_BYTES 9 77 #define UD_SIZE_BYTES_MASK GENMASK(18, 9) 78 #define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19) 79 #define SPARE_SIZE_BYTES 23 80 #define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) 81 #define NUM_ADDR_CYCLES 27 82 #define NUM_ADDR_CYCLES_MASK GENMASK(29, 27) 83 #define STATUS_BFR_READ BIT(30) 84 #define SET_RD_MODE_AFTER_STATUS BIT(31) 85 86 /* NAND_DEVn_CFG0 bits */ 87 #define DEV0_CFG1_ECC_DISABLE BIT(0) 88 #define WIDE_FLASH BIT(1) 89 #define NAND_RECOVERY_CYCLES 2 90 #define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2) 91 #define CS_ACTIVE_BSY BIT(5) 92 #define BAD_BLOCK_BYTE_NUM 6 93 #define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6) 94 #define BAD_BLOCK_IN_SPARE_AREA BIT(16) 95 #define WR_RD_BSY_GAP 17 96 #define WR_RD_BSY_GAP_MASK GENMASK(22, 17) 97 #define ENABLE_BCH_ECC BIT(27) 98 99 /* NAND_DEV0_ECC_CFG bits */ 100 #define ECC_CFG_ECC_DISABLE BIT(0) 101 #define ECC_SW_RESET BIT(1) 102 #define ECC_MODE 4 103 #define ECC_MODE_MASK GENMASK(5, 4) 104 #define ECC_PARITY_SIZE_BYTES_BCH 8 105 #define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8) 106 #define ECC_NUM_DATA_BYTES 16 107 #define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) 108 #define ECC_FORCE_CLK_OPEN BIT(30) 109 110 /* NAND_DEV_CMD1 bits */ 111 #define READ_ADDR 0 112 113 /* NAND_DEV_CMD_VLD bits */ 114 #define READ_START_VLD BIT(0) 115 #define READ_STOP_VLD BIT(1) 116 #define WRITE_START_VLD BIT(2) 117 #define ERASE_START_VLD BIT(3) 118 #define SEQ_READ_START_VLD BIT(4) 119 120 /* NAND_EBI2_ECC_BUF_CFG bits */ 121 #define NUM_STEPS 0 122 123 /* NAND_ERASED_CW_DETECT_CFG bits */ 124 #define ERASED_CW_ECC_MASK 1 125 #define AUTO_DETECT_RES 0 126 #define MASK_ECC BIT(ERASED_CW_ECC_MASK) 127 #define RESET_ERASED_DET BIT(AUTO_DETECT_RES) 128 #define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) 129 #define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) 130 #define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) 131 132 /* NAND_ERASED_CW_DETECT_STATUS bits */ 133 #define PAGE_ALL_ERASED BIT(7) 134 #define CODEWORD_ALL_ERASED BIT(6) 135 #define PAGE_ERASED BIT(5) 136 #define CODEWORD_ERASED BIT(4) 137 #define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED) 138 #define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED) 139 140 /* NAND_READ_LOCATION_n bits */ 141 #define READ_LOCATION_OFFSET 0 142 #define READ_LOCATION_SIZE 16 143 #define READ_LOCATION_LAST 31 144 145 /* Version Mask */ 146 #define NAND_VERSION_MAJOR_MASK 0xf0000000 147 #define NAND_VERSION_MAJOR_SHIFT 28 148 #define NAND_VERSION_MINOR_MASK 0x0fff0000 149 #define NAND_VERSION_MINOR_SHIFT 16 150 151 /* NAND OP_CMDs */ 152 #define OP_PAGE_READ 0x2 153 #define OP_PAGE_READ_WITH_ECC 0x3 154 #define OP_PAGE_READ_WITH_ECC_SPARE 0x4 155 #define OP_PAGE_READ_ONFI_READ 0x5 156 #define OP_PROGRAM_PAGE 0x6 157 #define OP_PAGE_PROGRAM_WITH_ECC 0x7 158 #define OP_PROGRAM_PAGE_SPARE 0x9 159 #define OP_BLOCK_ERASE 0xa 160 #define OP_CHECK_STATUS 0xc 161 #define OP_FETCH_ID 0xb 162 #define OP_RESET_DEVICE 0xd 163 164 /* Default Value for NAND_DEV_CMD_VLD */ 165 #define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \ 166 ERASE_START_VLD | SEQ_READ_START_VLD) 167 168 /* NAND_CTRL bits */ 169 #define BAM_MODE_EN BIT(0) 170 171 /* 172 * the NAND controller performs reads/writes with ECC in 516 byte chunks. 173 * the driver calls the chunks 'step' or 'codeword' interchangeably 174 */ 175 #define NANDC_STEP_SIZE 512 176 177 /* 178 * the largest page size we support is 8K, this will have 16 steps/codewords 179 * of 512 bytes each 180 */ 181 #define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE) 182 183 /* we read at most 3 registers per codeword scan */ 184 #define MAX_REG_RD (3 * MAX_NUM_STEPS) 185 186 /* ECC modes supported by the controller */ 187 #define ECC_NONE BIT(0) 188 #define ECC_RS_4BIT BIT(1) 189 #define ECC_BCH_4BIT BIT(2) 190 #define ECC_BCH_8BIT BIT(3) 191 192 /* 193 * Returns the actual register address for all NAND_DEV_ registers 194 * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD) 195 */ 196 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) 197 198 /* Returns the NAND register physical address */ 199 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset)) 200 201 /* Returns the dma address for reg read buffer */ 202 #define reg_buf_dma_addr(chip, vaddr) \ 203 ((chip)->reg_read_dma + \ 204 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf)) 205 206 #define QPIC_PER_CW_CMD_ELEMENTS 32 207 #define QPIC_PER_CW_CMD_SGL 32 208 #define QPIC_PER_CW_DATA_SGL 8 209 210 #define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000) 211 212 /* 213 * Flags used in DMA descriptor preparation helper functions 214 * (i.e. qcom_read_reg_dma/qcom_write_reg_dma/qcom_read_data_dma/qcom_write_data_dma) 215 */ 216 /* Don't set the EOT in current tx BAM sgl */ 217 #define NAND_BAM_NO_EOT BIT(0) 218 /* Set the NWD flag in current BAM sgl */ 219 #define NAND_BAM_NWD BIT(1) 220 /* Finish writing in the current BAM sgl and start writing in another BAM sgl */ 221 #define NAND_BAM_NEXT_SGL BIT(2) 222 /* 223 * Erased codeword status is being used two times in single transfer so this 224 * flag will determine the current value of erased codeword status register 225 */ 226 #define NAND_ERASED_CW_SET BIT(4) 227 228 #define MAX_ADDRESS_CYCLE 5 229 230 /* 231 * This data type corresponds to the BAM transaction which will be used for all 232 * NAND transfers. 233 * @bam_ce - the array of BAM command elements 234 * @cmd_sgl - sgl for NAND BAM command pipe 235 * @data_sgl - sgl for NAND BAM consumer/producer pipe 236 * @last_data_desc - last DMA desc in data channel (tx/rx). 237 * @last_cmd_desc - last DMA desc in command channel. 238 * @txn_done - completion for NAND transfer. 239 * @bam_ce_pos - the index in bam_ce which is available for next sgl 240 * @bam_ce_start - the index in bam_ce which marks the start position ce 241 * for current sgl. It will be used for size calculation 242 * for current sgl 243 * @cmd_sgl_pos - current index in command sgl. 244 * @cmd_sgl_start - start index in command sgl. 245 * @tx_sgl_pos - current index in data sgl for tx. 246 * @tx_sgl_start - start index in data sgl for tx. 247 * @rx_sgl_pos - current index in data sgl for rx. 248 * @rx_sgl_start - start index in data sgl for rx. 249 */ 250 struct bam_transaction { 251 struct bam_cmd_element *bam_ce; 252 struct scatterlist *cmd_sgl; 253 struct scatterlist *data_sgl; 254 struct dma_async_tx_descriptor *last_data_desc; 255 struct dma_async_tx_descriptor *last_cmd_desc; 256 struct completion txn_done; 257 struct_group(bam_positions, 258 u32 bam_ce_pos; 259 u32 bam_ce_start; 260 u32 cmd_sgl_pos; 261 u32 cmd_sgl_start; 262 u32 tx_sgl_pos; 263 u32 tx_sgl_start; 264 u32 rx_sgl_pos; 265 u32 rx_sgl_start; 266 267 ); 268 }; 269 270 /* 271 * This data type corresponds to the nand dma descriptor 272 * @dma_desc - low level DMA engine descriptor 273 * @list - list for desc_info 274 * 275 * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by 276 * ADM 277 * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM 278 * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM 279 * @dir - DMA transfer direction 280 */ 281 struct desc_info { 282 struct dma_async_tx_descriptor *dma_desc; 283 struct list_head node; 284 285 union { 286 struct scatterlist adm_sgl; 287 struct { 288 struct scatterlist *bam_sgl; 289 int sgl_cnt; 290 }; 291 }; 292 enum dma_data_direction dir; 293 }; 294 295 /* 296 * holds the current register values that we want to write. acts as a contiguous 297 * chunk of memory which we use to write the controller registers through DMA. 298 */ 299 struct nandc_regs { 300 __le32 cmd; 301 __le32 addr0; 302 __le32 addr1; 303 __le32 chip_sel; 304 __le32 exec; 305 306 __le32 cfg0; 307 __le32 cfg1; 308 __le32 ecc_bch_cfg; 309 310 __le32 clrflashstatus; 311 __le32 clrreadstatus; 312 313 __le32 cmd1; 314 __le32 vld; 315 316 __le32 orig_cmd1; 317 __le32 orig_vld; 318 319 __le32 ecc_buf_cfg; 320 __le32 read_location0; 321 __le32 read_location1; 322 __le32 read_location2; 323 __le32 read_location3; 324 __le32 read_location_last0; 325 __le32 read_location_last1; 326 __le32 read_location_last2; 327 __le32 read_location_last3; 328 329 __le32 erased_cw_detect_cfg_clr; 330 __le32 erased_cw_detect_cfg_set; 331 }; 332 333 /* 334 * NAND controller data struct 335 * 336 * @dev: parent device 337 * 338 * @base: MMIO base 339 * 340 * @core_clk: controller clock 341 * @aon_clk: another controller clock 342 * 343 * @regs: a contiguous chunk of memory for DMA register 344 * writes. contains the register values to be 345 * written to controller 346 * 347 * @props: properties of current NAND controller, 348 * initialized via DT match data 349 * 350 * @controller: base controller structure 351 * @host_list: list containing all the chips attached to the 352 * controller 353 * 354 * @chan: dma channel 355 * @cmd_crci: ADM DMA CRCI for command flow control 356 * @data_crci: ADM DMA CRCI for data flow control 357 * 358 * @desc_list: DMA descriptor list (list of desc_infos) 359 * 360 * @data_buffer: our local DMA buffer for page read/writes, 361 * used when we can't use the buffer provided 362 * by upper layers directly 363 * @reg_read_buf: local buffer for reading back registers via DMA 364 * 365 * @base_phys: physical base address of controller registers 366 * @base_dma: dma base address of controller registers 367 * @reg_read_dma: contains dma address for register read buffer 368 * 369 * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf 370 * functions 371 * @max_cwperpage: maximum QPIC codewords required. calculated 372 * from all connected NAND devices pagesize 373 * 374 * @reg_read_pos: marker for data read in reg_read_buf 375 * 376 * @cmd1/vld: some fixed controller register values 377 * 378 * @exec_opwrite: flag to select correct number of code word 379 * while reading status 380 */ 381 struct qcom_nand_controller { 382 struct device *dev; 383 384 void __iomem *base; 385 386 struct clk *core_clk; 387 struct clk *aon_clk; 388 389 struct nandc_regs *regs; 390 struct bam_transaction *bam_txn; 391 392 const struct qcom_nandc_props *props; 393 394 struct nand_controller *controller; 395 struct list_head host_list; 396 397 union { 398 /* will be used only by QPIC for BAM DMA */ 399 struct { 400 struct dma_chan *tx_chan; 401 struct dma_chan *rx_chan; 402 struct dma_chan *cmd_chan; 403 }; 404 405 /* will be used only by EBI2 for ADM DMA */ 406 struct { 407 struct dma_chan *chan; 408 unsigned int cmd_crci; 409 unsigned int data_crci; 410 }; 411 }; 412 413 struct list_head desc_list; 414 415 u8 *data_buffer; 416 __le32 *reg_read_buf; 417 418 phys_addr_t base_phys; 419 dma_addr_t base_dma; 420 dma_addr_t reg_read_dma; 421 422 int buf_size; 423 int buf_count; 424 int buf_start; 425 unsigned int max_cwperpage; 426 427 int reg_read_pos; 428 429 u32 cmd1, vld; 430 bool exec_opwrite; 431 }; 432 433 /* 434 * This data type corresponds to the NAND controller properties which varies 435 * among different NAND controllers. 436 * @ecc_modes - ecc mode for NAND 437 * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset 438 * @supports_bam - whether NAND controller is using BAM 439 * @nandc_part_of_qpic - whether NAND controller is part of qpic IP 440 * @qpic_version2 - flag to indicate QPIC IP version 2 441 * @use_codeword_fixup - whether NAND has different layout for boot partitions 442 */ 443 struct qcom_nandc_props { 444 u32 ecc_modes; 445 u32 dev_cmd_reg_start; 446 bool supports_bam; 447 bool nandc_part_of_qpic; 448 bool qpic_version2; 449 bool use_codeword_fixup; 450 }; 451 452 void qcom_free_bam_transaction(struct qcom_nand_controller *nandc); 453 struct bam_transaction *qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc); 454 void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc); 455 void qcom_qpic_bam_dma_done(void *data); 456 void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu); 457 int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc, 458 struct dma_chan *chan, unsigned long flags); 459 int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, 460 int reg_off, const void *vaddr, int size, unsigned int flags); 461 int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, 462 const void *vaddr, int size, unsigned int flags); 463 int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, int reg_off, 464 const void *vaddr, int size, bool flow_control); 465 int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, int num_regs, 466 unsigned int flags); 467 int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, int first, 468 int num_regs, unsigned int flags); 469 int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr, 470 int size, unsigned int flags); 471 int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr, 472 int size, unsigned int flags); 473 int qcom_submit_descs(struct qcom_nand_controller *nandc); 474 void qcom_clear_read_regs(struct qcom_nand_controller *nandc); 475 void qcom_nandc_unalloc(struct qcom_nand_controller *nandc); 476 int qcom_nandc_alloc(struct qcom_nand_controller *nandc); 477 #endif 478 479