1 /* 2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DDR_H 8 #define DDR_H 9 10 #include <lib/mmio.h> 11 #include "socfpga_handoff.h" 12 13 enum ddr_type { 14 DDR_TYPE_LPDDR4_0, 15 DDR_TYPE_LPDDR4_1, 16 DDR_TYPE_DDR4, 17 DDR_TYPE_LPDDR5_0, 18 DDR_TYPE_LPDDR5_1, 19 DDR_TYPE_DDR5, 20 DDR_TYPE_UNKNOWN 21 }; 22 23 /* Region size for ECCCFG0.ecc_region_map */ 24 enum region_size { 25 ONE_EIGHT, 26 ONE_SIXTEENTH, 27 ONE_THIRTY_SECOND, 28 ONE_SIXTY_FOURTH 29 }; 30 31 /* DATATYPE DEFINATION */ 32 typedef unsigned long long phys_addr_t; 33 typedef unsigned long long phys_size_t; 34 35 /* MACRO DEFINATION */ 36 #define IO96B_0_REG_BASE 0x18400000 37 #define IO96B_1_REG_BASE 0x18800000 38 #define IO96B_CSR_BASE 0x05000000 39 #define IO96B_CSR_REG(reg) (IO96B_CSR_BASE + reg) 40 41 #define IOSSM_CMD_MAX_WORD_SIZE 7U 42 #define IOSSM_RESP_MAX_WORD_SIZE 4U 43 44 #define CCU_REG_BASE 0x1C000000 45 #define DMI0_DMIUSMCTCR 0x7300 46 #define DMI1_DMIUSMCTCR 0x8300 47 #define CCU_DMI_ALLOCEN BIT(1) 48 #define CCU_DMI_LOOKUPEN BIT(2) 49 #define CCU_REG(reg) (CCU_REG_BASE + reg) 50 51 // CMD_RESPONSE_STATUS Register 52 #define CMD_RESPONSE_STATUS 0x45C 53 #define CMD_RESPONSE_OFFSET 0x4 54 #define CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) 55 #define CMD_RESPONSE_DATA_SHORT_OFFSET 16 56 #define STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) 57 #define STATUS_CMD_RESPONSE_ERROR_OFFSET 5 58 #define STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) 59 #define STATUS_GENERAL_ERROR_OFFSET 1 60 #define STATUS_COMMAND_RESPONSE_READY 0x1 61 #define STATUS_COMMAND_RESPONSE_READY_CLEAR 0x0 62 #define STATUS_COMMAND_RESPONSE_READY_MASK 0x1 63 #define STATUS_COMMAND_RESPONSE_READY_OFFSET 0 64 #define STATUS_COMMAND_RESPONSE(x) (((x) & \ 65 STATUS_COMMAND_RESPONSE_READY_MASK) >> \ 66 STATUS_COMMAND_RESPONSE_READY_OFFSET) 67 68 // CMD_REQ Register 69 #define CMD_STATUS 0x400 70 #define CMD_PARAM 0x438 71 #define CMD_REQ 0x43C 72 #define CMD_PARAM_OFFSET 0x4 73 #define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29) 74 #define CMD_TARGET_IP_TYPE_OFFSET 29 75 #define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24) 76 #define CMD_TARGET_IP_INSTANCE_ID_OFFSET 24 77 #define CMD_TYPE_MASK GENMASK(23, 16) 78 #define CMD_TYPE_OFFSET 16 79 #define CMD_OPCODE_MASK GENMASK(15, 0) 80 #define CMD_OPCODE_OFFSET 0 81 82 #define CMD_INIT 0 83 84 #define OPCODE_GET_MEM_INTF_INFO 0x0001 85 #define OPCODE_GET_MEM_TECHNOLOGY 0x0002 86 #define OPCODE_GET_MEM_WIDTH_INFO 0x0004 87 #define OPCODE_TRIG_MEM_CAL 0x000A 88 #define OPCODE_ECC_ENABLE_STATUS 0x0102 89 #define OPCODE_ECC_INTERRUPT_MASK 0x0105 90 #define OPCODE_ECC_SCRUB_MODE_0_START 0x0202 91 #define OPCODE_ECC_SCRUB_MODE_1_START 0x0203 92 #define OPCODE_BIST_RESULTS_STATUS 0x0302 93 #define OPCODE_BIST_MEM_INIT_START 0x0303 94 // Please update according to IOSSM mailbox spec 95 #define MBOX_ID_IOSSM 0x00 96 #define MBOX_CMD_GET_SYS_INFO 0x01 97 // Please update according to IOSSM mailbox spec 98 #define MBOX_CMD_GET_MEM_INFO 0x02 99 #define MBOX_CMD_TRIG_CONTROLLER_OP 0x04 100 #define MBOX_CMD_TRIG_MEM_CAL_OP 0x05 101 #define MBOX_CMD_POKE_REG 0xFD 102 #define MBOX_CMD_PEEK_REG 0xFE 103 #define MBOX_CMD_GET_DEBUG_LOG 0xFF 104 // Please update according to IOSSM mailbox spec 105 #define MBOX_CMD_DIRECT 0x00 106 107 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0_MASK 0x01 108 109 #define IOSSM_MB_WRITE(addr, data) mmio_write_32(addr, data) 110 111 /* DDR4 Register */ 112 #define DDR4_PWRCTL_OFFSET 0x30 113 #define DDR4_SBRCTL_OFFSET 0x0F24 114 #define DDR4_SBRSTAT_OFFSET 0x0F28 115 #define DDR4_SBRWDATA0_OFFSET 0x0F2C 116 #define DDR4_SBRSTART0_OFFSET 0x0F38 117 #define DDR4_SBRWDATA1_OFFSET 0x0F30 118 #define DDR4_SBRSTART1_OFFSET 0x0F3C 119 #define DDR4_SBRRANGE0_OFFSET 0x0F40 120 #define DDR4_SBRRANGE1_OFFSET 0x0F44 121 #define DDR4_ECCCFG0_OFFSET 0x70 122 #define DDR4_ECCCFG1_OFFSET 0x74 123 #define DDR4_PCTRL0_OFFSET 0x0490 124 125 #define LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT 30 126 #define ALL_PROTECTED 0x7F 127 #define LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT 8 128 129 130 131 #define LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK BIT(4) 132 #define DDR4_PCTRL0_PORT_EN BIT(0) 133 #define DDR4_SBRCTL_SCRUB_EN BIT(0) 134 #define DDR4_SBRSTAT_SCRUB_BUSY BIT(0) 135 #define DDR4_SBRCTL_SCRUB_BURST_1 BIT(4) 136 #define DDR4_SBRCTL_SCRUB_WRITE BIT(2) 137 #define DDR4_SBRSTAT_SCRUB_DONE BIT(1) 138 139 /* FUNCTION DEFINATION */ 140 int ddr_calibration_check(void); 141 142 int iossm_mb_init(void); 143 144 int iossm_mb_read_response(void); 145 146 int iossm_mb_send(uint32_t cmd_target_ip_type, uint32_t cmd_target_ip_instance_id, 147 uint32_t cmd_type, uint32_t cmd_opcode, uint32_t *args, 148 unsigned int len); 149 150 int ddr_iossm_mailbox_cmd(uint32_t cmd); 151 152 int ddr_init(void); 153 154 int ddr_config_handoff(handoff *hoff_ptr); 155 156 void ddr_enable_ns_access(void); 157 158 void ddr_enable_firewall(void); 159 160 bool is_ddr_init_in_progress(void); 161 162 int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type); 163 164 int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type); 165 166 int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms); 167 168 #endif 169