1 /*
2  * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * This file is limited to include the RoS firmware specific definitions for the
7  * first generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of
8  * System) is used to refer to the part of the reference design platform that
9  * excludes CSS.
10  */
11 
12 #ifndef NRD_ROS_FW_DEF1_H
13 #define NRD_ROS_FW_DEF1_H
14 
15 #include <nrd_ros_def1.h>
16 
17 /*******************************************************************************
18  * MMU mapping
19  ******************************************************************************/
20 
21 #define NRD_ROS_PERIPH_MMAP(n)						\
22 		MAP_REGION_FLAT(					\
23 			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
24 			NRD_ROS_PERIPH_BASE,				\
25 			NRD_ROS_PERIPH_SIZE,				\
26 			MT_DEVICE | MT_RW | MT_SECURE)
27 
28 #define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP				\
29 		MAP_REGION_FLAT(					\
30 			NRD_ROS_SYSTEMREG_BASE,				\
31 			NRD_ROS_SYSTEMREG_SIZE,				\
32 			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
33 
34 #define NRD_ROS_SECURE_NOR2_USER_MMAP					\
35 		MAP_REGION_FLAT(					\
36 			NRD_ROS_NOR2_FLASH_BASE,			\
37 			NRD_ROS_NOR2_FLASH_SIZE,			\
38 			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
39 
40 #define NRD_MAP_FLASH0_RO						\
41 		MAP_REGION_FLAT(					\
42 			V2M_FLASH0_BASE,				\
43 			V2M_FLASH0_SIZE,				\
44 			MT_DEVICE | MT_RO | MT_SECURE)
45 
46 /*******************************************************************************
47  * TZ config
48  ******************************************************************************/
49 
50 /*
51  * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
52  * where both the DRAM regions are marked for non-secure access. This applies
53  * to multi-chip platforms.
54  */
55 #define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n)				\
56 	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE,		\
57 		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END,		\
58 		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},	\
59 	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE,		\
60 		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END,		\
61 		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
62 
63 #endif  /* NRD_ROS_FW_DEF1_H */
64