1 /*
2  * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * This file is limited to include the CSS specific memory and interrupt map
7  * definitions for the first generation platforms based on the A75, N1 and V1
8  * CPUs. There are minor differences in the memory map of these platforms and
9  * those differences are not in the scope of this file.
10  */
11 
12 #ifndef NRD_CSS_DEF1_H
13 #define NRD_CSS_DEF1_H
14 
15 /*******************************************************************************
16  * CSS memory map related defines
17  ******************************************************************************/
18 
19 /* On-Chip ROM */
20 #define NRD_CSS_TRUSTED_ROM_BASE	UL(0x00000000)
21 #define NRD_CSS_TRUSTED_ROM_SIZE	UL(0x00080000)	/* 512KB */
22 
23 /* On-Chip RAM */
24 #define	NRD_CSS_TRUSTED_SRAM_SIZE	UL(0x00080000)	/* 512KB */
25 #define NRD_CSS_NONTRUSTED_SRAM_BASE	UL(0x06000000)
26 #define NRD_CSS_NONTRUSTED_SRAM_SIZE	UL(0x00080000)	/* 512KB */
27 
28 /* PL011 UART */
29 #define NRD_CSS_SEC_UART_BASE		UL(0x2A410000)
30 #define NRD_CSS_UART_SIZE		UL(0x10000)
31 
32 /* CSS peripherals */
33 #define NRD_CSS_PERIPH_BASE		UL(0x20000000)
34 #define NRD_CSS_PERIPH_SIZE		UL(0x40000000)
35 
36 /* Secure Watchdog */
37 #define NRD_CSS_WDOG_BASE		UL(0x2A480000)
38 
39 /* DRAM2 */
40 #define NRD_CSS_DRAM2_BASE		ULL(0x8080000000)
41 #define NRD_CSS_DRAM2_SIZE		ULL(0x180000000)
42 
43 #endif /* NRD_CSS_DEF1_H */
44