1 /** @file 2 3 Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> 4 5 Redistribution and use in source and binary forms, with or without modification, 6 are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, this 11 list of conditions and the following disclaimer in the documentation and/or 12 other materials provided with the distribution. 13 * Neither the name of Intel Corporation nor the names of its contributors may 14 be used to endorse or promote products derived from this software without 15 specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 THE POSSIBILITY OF SUCH DAMAGE. 28 29 This file is automatically generated. Please do NOT modify !!! 30 31 **/ 32 33 #ifndef __FSPMUPD_H__ 34 #define __FSPMUPD_H__ 35 36 #include <FspUpd.h> 37 38 #pragma pack(1) 39 40 41 #include <MemInfoHob.h> 42 43 /// 44 /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. 45 /// 46 typedef struct { 47 UINT8 Revision; ///< Chipset Init Info Revision 48 UINT8 Rsvd[3]; ///< Reserved 49 UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table 50 UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table 51 } CHIPSET_INIT_INFO; 52 53 54 /** Fsp M Configuration 55 **/ 56 typedef struct { 57 58 /** Offset 0x0040 - Platform Reserved Memory Size 59 The minimum platform memory size required to pass control into DXE 60 **/ 61 UINT64 PlatformMemorySize; 62 63 /** Offset 0x0048 - SPD Data Length 64 Length of SPD Data 65 0x100:256 Bytes, 0x200:512 Bytes 66 **/ 67 UINT16 MemorySpdDataLen; 68 69 /** Offset 0x004A - Enable above 4GB MMIO resource support 70 Enable/disable above 4GB MMIO resource support 71 $EN_DIS 72 **/ 73 UINT8 EnableAbove4GBMmio; 74 75 /** Offset 0x004B - Reserved 76 **/ 77 UINT8 Reserved0; 78 79 /** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0 80 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 81 **/ 82 UINT32 MemorySpdPtr00; 83 84 /** Offset 0x0050 - Memory SPD Pointer Channel 0 Dimm 1 85 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 86 **/ 87 UINT32 MemorySpdPtr01; 88 89 /** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0 90 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 91 **/ 92 UINT32 MemorySpdPtr10; 93 94 /** Offset 0x0058 - Memory SPD Pointer Channel 1 Dimm 1 95 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 96 **/ 97 UINT32 MemorySpdPtr11; 98 99 /** Offset 0x005C - Dq Byte Map CH0 100 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent 101 **/ 102 UINT8 DqByteMapCh0[12]; 103 104 /** Offset 0x0068 - Dq Byte Map CH1 105 Dq byte mapping between CPU and DRAM, Channel 1: board-dependent 106 **/ 107 UINT8 DqByteMapCh1[12]; 108 109 /** Offset 0x0074 - Dqs Map CPU to DRAM CH 0 110 Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent 111 **/ 112 UINT8 DqsMapCpu2DramCh0[8]; 113 114 /** Offset 0x007C - Dqs Map CPU to DRAM CH 1 115 Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent 116 **/ 117 UINT8 DqsMapCpu2DramCh1[8]; 118 119 /** Offset 0x0084 - RcompResister settings 120 Indicates RcompReister settings: Board-dependent 121 **/ 122 UINT16 RcompResistor[3]; 123 124 /** Offset 0x008A - RcompTarget settings 125 RcompTarget settings: board-dependent 126 **/ 127 UINT16 RcompTarget[5]; 128 129 /** Offset 0x0094 - Dqs Pins Interleaved Setting 130 Indicates DqPinsInterleaved setting: board-dependent 131 $EN_DIS 132 **/ 133 UINT8 DqPinsInterleaved; 134 135 /** Offset 0x0095 - VREF_CA 136 CA Vref routing: board-dependent 137 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, 138 2:VREF_CA to CH_A and VREF_DQ_B to CH_B 139 **/ 140 UINT8 CaVrefConfig; 141 142 /** Offset 0x0096 - Smram Mask 143 The SMM Regions AB-SEG and/or H-SEG reserved 144 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both 145 **/ 146 UINT8 SmramMask; 147 148 /** Offset 0x0097 - MRC Fast Boot 149 Enables/Disable the MRC fast path thru the MRC 150 $EN_DIS 151 **/ 152 UINT8 MrcFastBoot; 153 154 /** Offset 0x0098 - LPDDR4 Write DQ/DQS Retraining 155 Enables/Disable LPDDR4 Write DQ/DQS Retraining 156 $EN_DIS 157 **/ 158 UINT8 Lp4DqsOscEn; 159 160 /** Offset 0x0099 - Reserved 161 **/ 162 UINT8 Reserved1; 163 164 /** Offset 0x009A - Rank Margin Tool per Task 165 This option enables the user to execute Rank Margin Tool per major training step 166 in the MRC. 167 $EN_DIS 168 **/ 169 UINT8 RmtPerTask; 170 171 /** Offset 0x009B - Training Trace 172 This option enables the trained state tracing feature in MRC. This feature will 173 print out the key training parameters state across major training steps. 174 $EN_DIS 175 **/ 176 UINT8 TrainTrace; 177 178 /** Offset 0x009C - Tseg Size 179 Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build 180 0x0400000:4MB, 0x01000000:16MB 181 **/ 182 UINT32 TsegSize; 183 184 /** Offset 0x00A0 - MMIO Size 185 Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB 186 **/ 187 UINT16 MmioSize; 188 189 /** Offset 0x00A2 - LowSupplyEnData 190 Enable: Enable Low Supply for LPDDR4 Data, Disable(Default) 191 $EN_DIS 192 **/ 193 UINT8 LowSupplyEnData; 194 195 /** Offset 0x00A3 - LowSupplyEnCcc 196 Enable: Enable Low Supply for LPDDR4 Clock/Command/Control, Disable(Default) 197 $EN_DIS 198 **/ 199 UINT8 LowSupplyEnCcc; 200 201 /** Offset 0x00A4 - Memory Test on Warm Boot 202 Run Base Memory Test on Warm Boot 203 0:Disable, 1:Enable 204 **/ 205 UINT8 MemTestOnWarmBoot; 206 207 /** Offset 0x00A5 - Probeless Trace 208 Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. 209 This also requires IED to be enabled. 210 $EN_DIS 211 **/ 212 UINT8 ProbelessTrace; 213 214 /** Offset 0x00A6 - Enable SMBus 215 Enable/disable SMBus controller. 216 $EN_DIS 217 **/ 218 UINT8 SmbusEnable; 219 220 /** Offset 0x00A7 - Spd Address Tabl 221 Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used 222 if SPD Address is 00 223 **/ 224 UINT8 SpdAddressTable[4]; 225 226 /** Offset 0x00AB - Platform Debug Consent 227 To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. 228 Enabling this BIOS option may alter the default value of other debug-related BIOS 229 options.\Manual: Do not use Platform Debug Consent to override other debug-relevant 230 policies, but the user must set each debug option manually, aimed at advanced users.\n 231 Note: DCI OOB (aka BSSB) uses CCA probe. 232 0:Disabled, 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled 233 (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual 234 **/ 235 UINT8 PlatformDebugConsent; 236 237 /** Offset 0x00AC - DCI Enable 238 Determine if to enable DCI debug from host 239 $EN_DIS 240 **/ 241 UINT8 DciEn; 242 243 /** Offset 0x00AD - DCI DbC Mode 244 Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: 245 Set both USB2/3DBCEN; No Change: Comply with HW value 246 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change 247 **/ 248 UINT8 DciDbcMode; 249 250 /** Offset 0x00AE - Enable DCI ModPHY Pwoer Gate 251 Enable ModPHY Pwoer Gate when DCI is enabled 252 $EN_DIS 253 **/ 254 UINT8 DciModphyPg; 255 256 /** Offset 0x00AF - USB3 Type-C UFP2DFP Kernel/Platform Debug Support 257 This BIOS option enables kernel and platform debug for USB3 interface over a UFP 258 Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. 259 0:Disabled, 1:Enabled, 2:No Change 260 **/ 261 UINT8 DciUsb3TypecUfpDbg; 262 263 /** Offset 0x00B0 - PCH Trace Hub Mode 264 Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' 265 if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. 266 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode 267 **/ 268 UINT8 PchTraceHubMode; 269 270 /** Offset 0x00B1 - PCH Trace Hub Memory Region 0 buffer Size 271 Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 272 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. 273 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB 274 **/ 275 UINT8 PchTraceHubMemReg0Size; 276 277 /** Offset 0x00B2 - PCH Trace Hub Memory Region 1 buffer Size 278 Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 279 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. 280 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB 281 **/ 282 UINT8 PchTraceHubMemReg1Size; 283 284 /** Offset 0x00B3 - Reserved 285 **/ 286 UINT8 Reserved2[7]; 287 288 /** Offset 0x00BA - State of X2APIC_OPT_OUT bit in the DMAR table 289 0=Disable/Clear, 1=Enable/Set 290 $EN_DIS 291 **/ 292 UINT8 X2ApicOptOut; 293 294 /** Offset 0x00BB - State of DMA_CONTROL_GUARANTEE bit in the DMAR table 295 0=Disable/Clear, 1=Enable/Set 296 $EN_DIS 297 **/ 298 UINT8 DmaControlGuarantee; 299 300 /** Offset 0x00BC - Base addresses for VT-d function MMIO access 301 Base addresses for VT-d MMIO access per VT-d engine 302 **/ 303 UINT32 VtdBaseAddress[9]; 304 305 /** Offset 0x00E0 - Disable VT-d 306 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) 307 $EN_DIS 308 **/ 309 UINT8 VtdDisable; 310 311 /** Offset 0x00E1 - Vtd Programming for Igd 312 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar 313 programming disabled) 314 $EN_DIS 315 **/ 316 UINT8 VtdIgdEnable; 317 318 /** Offset 0x00E2 - Vtd Programming for Ipu 319 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar 320 programming disabled) 321 $EN_DIS 322 **/ 323 UINT8 VtdIpuEnable; 324 325 /** Offset 0x00E3 - Vtd Programming for Iop 326 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar 327 programming disabled) 328 $EN_DIS 329 **/ 330 UINT8 VtdIopEnable; 331 332 /** Offset 0x00E4 - Internal Graphics Pre-allocated Memory 333 Size of memory preallocated for internal graphics. 334 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, 335 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 336 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB 337 **/ 338 UINT8 IgdDvmt50PreAlloc; 339 340 /** Offset 0x00E5 - Internal Graphics 341 Enable/disable internal graphics. 342 $EN_DIS 343 **/ 344 UINT8 InternalGfx; 345 346 /** Offset 0x00E6 - Aperture Size 347 Select the Aperture Size. 348 0:128 MB, 1:256 MB, 2:512 MB 349 **/ 350 UINT8 ApertureSize; 351 352 /** Offset 0x00E7 - Board Type 353 MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile 354 Halo, 7=UP Server 355 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server 356 **/ 357 UINT8 UserBd; 358 359 /** Offset 0x00E8 - DDR Frequency Limit 360 Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 361 2133, 2400, 2667, 2933 and 0 for Auto. 362 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto 363 **/ 364 UINT16 DdrFreqLimit; 365 366 /** Offset 0x00EA - SA GV 367 System Agent dynamic frequency support and when enabled memory will be training 368 at three different frequencies. 369 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled 370 **/ 371 UINT8 SaGv; 372 373 /** Offset 0x00EB - DDR Speed Control 374 DDR Frequency and Gear control for all SAGV points. 375 0:Auto, 1:Manual 376 **/ 377 UINT8 DdrSpeedControl; 378 379 /** Offset 0x00EC - Low Frequency 380 SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 381 2400, 2667, 2933 and 0 for Auto. 382 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto 383 **/ 384 UINT16 FreqSaGvLow; 385 386 /** Offset 0x00EE - Mid Frequency 387 SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 388 2400, 2667, 2933 and 0 for Auto. 389 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto 390 **/ 391 UINT16 FreqSaGvMid; 392 393 /** Offset 0x00F0 - Rank Margin Tool 394 Enable/disable Rank Margin Tool. 395 $EN_DIS 396 **/ 397 UINT8 RMT; 398 399 /** Offset 0x00F1 - Channel A DIMM Control 400 Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. 401 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs 402 **/ 403 UINT8 DisableDimmChannel0; 404 405 /** Offset 0x00F2 - Channel B DIMM Control 406 Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. 407 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs 408 **/ 409 UINT8 DisableDimmChannel1; 410 411 /** Offset 0x00F3 - Scrambler Support 412 This option enables data scrambling in memory. 413 $EN_DIS 414 **/ 415 UINT8 ScramblerSupport; 416 417 /** Offset 0x00F4 - Ddr4OneDpc 418 DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, 419 or on both (default) 420 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled 421 **/ 422 UINT8 Ddr4OneDpc; 423 424 /** Offset 0x00F5 - Reserved 425 **/ 426 UINT8 Reserved3[3]; 427 428 /** Offset 0x00F8 - MMA Test Content Pointer 429 Pointer to MMA Test Content in Memory 430 **/ 431 UINT32 MmaTestContentPtr; 432 433 /** Offset 0x00FC - MMA Test Content Size 434 Size of MMA Test Content in Memory 435 **/ 436 UINT32 MmaTestContentSize; 437 438 /** Offset 0x0100 - MMA Test Config Pointer 439 Pointer to MMA Test Config in Memory 440 **/ 441 UINT32 MmaTestConfigPtr; 442 443 /** Offset 0x0104 - MMA Test Config Size 444 Size of MMA Test Config in Memory 445 **/ 446 UINT32 MmaTestConfigSize; 447 448 /** Offset 0x0108 - SPD Profile Selected 449 Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP 450 Profile 1, 3=XMP Profile 2 451 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2 452 **/ 453 UINT8 SpdProfileSelected; 454 455 /** Offset 0x0109 - Memory Reference Clock 456 100MHz, 133MHz. 457 0:133MHz, 1:100MHz 458 **/ 459 UINT8 RefClk; 460 461 /** Offset 0x010A - Memory Voltage 462 DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM 463 chips) in millivolts. <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc. 464 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 465 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts 466 **/ 467 UINT16 VddVoltage; 468 469 /** Offset 0x010C - Memory Ratio 470 Automatic or the frequency will equal ratio times reference clock. Set to Auto to 471 recalculate memory timings listed below. 472 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 473 **/ 474 UINT8 Ratio; 475 476 /** Offset 0x010D - QCLK Odd Ratio 477 Adds 133 or 100 MHz to QCLK frequency, depending on RefClk 478 $EN_DIS 479 **/ 480 UINT8 OddRatioMode; 481 482 /** Offset 0x010E - tCL 483 CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected 484 == 1 (Custom Profile). 485 **/ 486 UINT8 tCL; 487 488 /** Offset 0x010F - tCWL 489 Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected 490 == 1 (Custom Profile). 491 **/ 492 UINT8 tCWL; 493 494 /** Offset 0x0110 - tFAW 495 Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected 496 == 1 (Custom Profile). 497 **/ 498 UINT16 tFAW; 499 500 /** Offset 0x0112 - tRAS 501 RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected 502 == 1 (Custom Profile). 503 **/ 504 UINT16 tRAS; 505 506 /** Offset 0x0114 - tRCD/tRP 507 RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used 508 if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). 509 **/ 510 UINT8 tRCDtRP; 511 512 /** Offset 0x0115 - SA GV Low Gear 513 Gear Selection for SAGV Low point 514 0:Gear1, 1:Gear2 515 **/ 516 UINT8 SaGvLowGear2; 517 518 /** Offset 0x0116 - tREFI 519 Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected 520 == 1 (Custom Profile). 521 **/ 522 UINT16 tREFI; 523 524 /** Offset 0x0118 - tRFC 525 Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected 526 == 1 (Custom Profile). 527 **/ 528 UINT16 tRFC; 529 530 /** Offset 0x011A - tRRD 531 Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected 532 == 1 (Custom Profile). 533 **/ 534 UINT8 tRRD; 535 536 /** Offset 0x011B - tRTP 537 Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal 538 values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected 539 == 1 (Custom Profile). 540 **/ 541 UINT8 tRTP; 542 543 /** Offset 0x011C - tWR 544 Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 545 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). 546 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, 547 34:34, 40:40 548 **/ 549 UINT8 tWR; 550 551 /** Offset 0x011D - tWTR 552 Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected 553 == 1 (Custom Profile). 554 **/ 555 UINT8 tWTR; 556 557 /** Offset 0x011E - NMode 558 System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N 559 **/ 560 UINT8 NModeSupport; 561 562 /** Offset 0x011F - DllBwEn[0] 563 DllBwEn[0], for 1067 (0..7) 564 **/ 565 UINT8 DllBwEn0; 566 567 /** Offset 0x0120 - DllBwEn[1] 568 DllBwEn[1], for 1333 (0..7) 569 **/ 570 UINT8 DllBwEn1; 571 572 /** Offset 0x0121 - DllBwEn[2] 573 DllBwEn[2], for 1600 (0..7) 574 **/ 575 UINT8 DllBwEn2; 576 577 /** Offset 0x0122 - DllBwEn[3] 578 DllBwEn[3], for 1867 and up (0..7) 579 **/ 580 UINT8 DllBwEn3; 581 582 /** Offset 0x0123 - ISVT IO Port Address 583 ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default 584 **/ 585 UINT8 IsvtIoPort; 586 587 /** Offset 0x0124 - Enable Intel HD Audio (Azalia) 588 0: Disable, 1: Enable (Default) Azalia controller 589 $EN_DIS 590 **/ 591 UINT8 PchHdaEnable; 592 593 /** Offset 0x0125 - CPU Trace Hub Mode 594 Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' 595 if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. 596 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode 597 **/ 598 UINT8 CpuTraceHubMode; 599 600 /** Offset 0x0126 - CPU Trace Hub Memory Region 0 601 CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 602 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. 603 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB 604 **/ 605 UINT8 CpuTraceHubMemReg0Size; 606 607 /** Offset 0x0127 - CPU Trace Hub Memory Region 1 608 CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 609 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. 610 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB 611 **/ 612 UINT8 CpuTraceHubMemReg1Size; 613 614 /** Offset 0x0128 - SA GV Mid Gear 615 Gear Selection for SAGV Mid point 616 0:Gear1, 1:Gear2 617 **/ 618 UINT8 SaGvMidGear2; 619 620 /** Offset 0x0129 - SA GV High Gear 621 Gear Selection for SAGV High point, or when SAGV is disabled 622 0:Gear1, 1:Gear2 623 **/ 624 UINT8 SaGvHighGear2; 625 626 /** Offset 0x012A - HECI Timeouts 627 0: Disable, 1: Enable (Default) timeout check for HECI 628 $EN_DIS 629 **/ 630 UINT8 HeciTimeouts; 631 632 /** Offset 0x012B - Reserved 633 **/ 634 UINT8 Reserved4; 635 636 /** Offset 0x012C - HECI1 BAR address 637 BAR address of HECI1 638 **/ 639 UINT32 Heci1BarAddress; 640 641 /** Offset 0x0130 - HECI2 BAR address 642 BAR address of HECI2 643 **/ 644 UINT32 Heci2BarAddress; 645 646 /** Offset 0x0134 - HECI3 BAR address 647 BAR address of HECI3 648 **/ 649 UINT32 Heci3BarAddress; 650 651 /** Offset 0x0138 - HG dGPU Power Delay 652 HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 653 300=300 microseconds 654 **/ 655 UINT16 HgDelayAfterPwrEn; 656 657 /** Offset 0x013A - HG dGPU Reset Delay 658 HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 659 microseconds 660 **/ 661 UINT16 HgDelayAfterHoldReset; 662 663 /** Offset 0x013C - MMIO size adjustment for AUTO mode 664 Positive number means increasing MMIO size, Negative value means decreasing MMIO 665 size: 0 (Default)=no change to AUTO mode MMIO size 666 **/ 667 UINT16 MmioSizeAdjustment; 668 669 /** Offset 0x013E - PCIe ASPM programming will happen in relation to the Oprom 670 Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): 671 Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after 672 Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume 673 0:Before, 1:After 674 **/ 675 UINT8 InitPcieAspmAfterOprom; 676 677 /** Offset 0x013F - Selection of the primary display device 678 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics 679 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics 680 **/ 681 UINT8 PrimaryDisplay; 682 683 /** Offset 0x0140 - Selection of PSMI Region size 684 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 685 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB 686 **/ 687 UINT8 PsmiRegionSize; 688 689 /** Offset 0x0141 - Reserved 690 **/ 691 UINT8 Reserved5[3]; 692 693 /** Offset 0x0144 - Temporary MMIO address for GMADR 694 Obsolete field now and it has been extended to 64 bit address, used GmAdr64 695 **/ 696 UINT32 GmAdr; 697 698 /** Offset 0x0148 - Temporary MMIO address for GTTMMADR 699 The reference code will use this as Temporary MMIO address space to access GTTMMADR 700 Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr 701 to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO 702 + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) 703 **/ 704 UINT32 GttMmAdr; 705 706 /** Offset 0x014C - Selection of iGFX GTT Memory size 707 1=2MB, 2=4MB, 3=8MB, Default is 3 708 1:2MB, 2:4MB, 3:8MB 709 **/ 710 UINT16 GttSize; 711 712 /** Offset 0x014E - Reserved 713 **/ 714 UINT8 Reserved6[24]; 715 716 /** Offset 0x0166 - Enable/Disable MRC TXT dependency 717 When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): 718 MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization 719 $EN_DIS 720 **/ 721 UINT8 TxtImplemented; 722 723 /** Offset 0x0167 - Enable/Disable SA OcSupport 724 Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport 725 $EN_DIS 726 **/ 727 UINT8 SaOcSupport; 728 729 /** Offset 0x0168 - GT slice Voltage Mode 730 0(Default): Adaptive, 1: Override 731 0: Adaptive, 1: Override 732 **/ 733 UINT8 GtVoltageMode; 734 735 /** Offset 0x0169 - Maximum GTs turbo ratio override 736 0(Default)=Minimal/Auto, 60=Maximum 737 **/ 738 UINT8 GtMaxOcRatio; 739 740 /** Offset 0x016A - The voltage offset applied to GT slice 741 0(Default)=Minimal, 1000=Maximum 742 **/ 743 UINT16 GtVoltageOffset; 744 745 /** Offset 0x016C - The GT slice voltage override which is applied to the entire range of GT frequencies 746 0(Default)=Minimal, 2000=Maximum 747 **/ 748 UINT16 GtVoltageOverride; 749 750 /** Offset 0x016E - adaptive voltage applied during turbo frequencies 751 0(Default)=Minimal, 2000=Maximum 752 **/ 753 UINT16 GtExtraTurboVoltage; 754 755 /** Offset 0x0170 - voltage offset applied to the SA 756 0(Default)=Minimal, 1000=Maximum 757 **/ 758 UINT16 SaVoltageOffset; 759 760 /** Offset 0x0172 - PCIe root port Function number for Hybrid Graphics dGPU 761 Root port Index number to indicate which PCIe root port has dGPU 762 **/ 763 UINT8 RootPortIndex; 764 765 /** Offset 0x0173 - Realtime Memory Timing 766 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform 767 realtime memory timing changes after MRC_DONE. 768 0: Disabled, 1: Enabled 769 **/ 770 UINT8 RealtimeMemoryTiming; 771 772 /** Offset 0x0174 - Enable/Disable SA IPU 773 Enable(Default): Enable SA IPU, Disable: Disable SA IPU 774 $EN_DIS 775 **/ 776 UINT8 SaIpuEnable; 777 778 /** Offset 0x0175 - IPU IMR Configuration 779 0:IPU Camera, 1:IPU Gen Default is 0 780 0:IPU Camera, 1:IPU Gen 781 **/ 782 UINT8 SaIpuImrConfiguration; 783 784 /** Offset 0x0176 - IMGU CLKOUT Configuration 785 The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. 786 $EN_DIS 787 **/ 788 UINT8 ImguClkOutEn[6]; 789 790 /** Offset 0x017C - Reserved 791 **/ 792 UINT8 Reserved7[10]; 793 794 /** Offset 0x0186 - Selection of PSMI Support On/Off 795 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support 796 $EN_DIS 797 **/ 798 UINT8 GtPsmiSupport; 799 800 /** Offset 0x0187 - Reserved 801 **/ 802 UINT8 Reserved8; 803 804 /** Offset 0x0188 - Program GPIOs for LFP on DDI port-A device 805 0=Disabled,1(Default)=eDP, 2=MIPI DSI 806 0:Disabled, 1:eDP, 2:MIPI DSI 807 **/ 808 UINT8 DdiPortAConfig; 809 810 /** Offset 0x0189 - Reserved 811 **/ 812 UINT8 Reserved9[2]; 813 814 /** Offset 0x018B - Enable or disable HPD of DDI port B 815 0=Disable, 1(Default)=Enable 816 $EN_DIS 817 **/ 818 UINT8 DdiPortBHpd; 819 820 /** Offset 0x018C - Enable or disable HPD of DDI port C 821 0(Default)=Disable, 1=Enable 822 $EN_DIS 823 **/ 824 UINT8 DdiPortCHpd; 825 826 /** Offset 0x018D - Enable or disable HPD of DDI port 1 827 0=Disable, 1(Default)=Enable 828 $EN_DIS 829 **/ 830 UINT8 DdiPort1Hpd; 831 832 /** Offset 0x018E - Enable or disable HPD of DDI port 2 833 0(Default)=Disable, 1=Enable 834 $EN_DIS 835 **/ 836 UINT8 DdiPort2Hpd; 837 838 /** Offset 0x018F - Enable or disable HPD of DDI port 3 839 0(Default)=Disable, 1=Enable 840 $EN_DIS 841 **/ 842 UINT8 DdiPort3Hpd; 843 844 /** Offset 0x0190 - Enable or disable HPD of DDI port 4 845 0(Default)=Disable, 1=Enable 846 $EN_DIS 847 **/ 848 UINT8 DdiPort4Hpd; 849 850 /** Offset 0x0191 - Reserved 851 **/ 852 UINT8 Reserved10; 853 854 /** Offset 0x0192 - Enable or disable DDC of DDI port B 855 0=Disable, 1(Default)=Enable 856 $EN_DIS 857 **/ 858 UINT8 DdiPortBDdc; 859 860 /** Offset 0x0193 - Enable or disable DDC of DDI port C 861 0(Default)=Disable, 1=Enable 862 $EN_DIS 863 **/ 864 UINT8 DdiPortCDdc; 865 866 /** Offset 0x0194 - Enable DDC setting of DDI Port 1 867 0(Default)=Disable, 1=Enable 868 $EN_DIS 869 **/ 870 UINT8 DdiPort1Ddc; 871 872 /** Offset 0x0195 - Enable DDC setting of DDI Port 2 873 0(Default)=Disable, 1=Enable 874 $EN_DIS 875 **/ 876 UINT8 DdiPort2Ddc; 877 878 /** Offset 0x0196 - Enable DDC setting of DDI Port 3 879 0(Default)=Disable, 1=Enable 880 $EN_DIS 881 **/ 882 UINT8 DdiPort3Ddc; 883 884 /** Offset 0x0197 - Enable DDC setting of DDI Port 4 885 0(Default)=Disable, 1=Enable 886 $EN_DIS 887 **/ 888 UINT8 DdiPort4Ddc; 889 890 /** Offset 0x0198 - Reserved 891 **/ 892 UINT8 Reserved11[130]; 893 894 /** Offset 0x021A - DMI Max Link Speed 895 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 896 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 897 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 898 **/ 899 UINT8 DmiMaxLinkSpeed; 900 901 /** Offset 0x021B - DMI Equalization Phase 2 902 DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): 903 AUTO - Use the current default method 904 0:Disable phase2, 1:Enable phase2, 2:Auto 905 **/ 906 UINT8 DmiGen3EqPh2Enable; 907 908 /** Offset 0x021C - DMI Gen3 Equalization Phase3 909 DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, 910 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software 911 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static 912 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just 913 Phase1), Disabled(0x4): Bypass Equalization Phase 3 914 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 915 **/ 916 UINT8 DmiGen3EqPh3Method; 917 918 /** Offset 0x021D - Enable/Disable DMI GEN3 Static EQ Phase1 programming 919 Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static 920 Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming 921 $EN_DIS 922 **/ 923 UINT8 DmiGen3ProgramStaticEq; 924 925 /** Offset 0x021E - DeEmphasis control for DMI 926 DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB 927 0: -6dB, 1: -3.5dB 928 **/ 929 UINT8 DmiDeEmphasis; 930 931 /** Offset 0x021F - DMI Gen3 Root port preset values per lane 932 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane 933 **/ 934 UINT8 DmiGen3RootPortPreset[8]; 935 936 /** Offset 0x0227 - DMI Gen3 End port preset values per lane 937 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane 938 **/ 939 UINT8 DmiGen3EndPointPreset[8]; 940 941 /** Offset 0x022F - DMI Gen3 End port Hint values per lane 942 Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane 943 **/ 944 UINT8 DmiGen3EndPointHint[8]; 945 946 /** Offset 0x0237 - DMI Gen3 RxCTLEp per-Bundle control 947 Range: 0-15, 0 is default for each bundle, must be specified based upon platform design 948 **/ 949 UINT8 DmiGen3RxCtlePeaking[4]; 950 951 /** Offset 0x023B - BIST on Reset 952 Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable. 953 $EN_DIS 954 **/ 955 UINT8 BistOnReset; 956 957 /** Offset 0x023C - Skip Stop PBET Timer Enable/Disable 958 Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable 959 $EN_DIS 960 **/ 961 UINT8 SkipStopPbet; 962 963 /** Offset 0x023D - Over clocking support 964 Over clocking support; <b>0: Disable</b>; 1: Enable 965 $EN_DIS 966 **/ 967 UINT8 OcSupport; 968 969 /** Offset 0x023E - Over clocking Lock 970 Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable. 971 $EN_DIS 972 **/ 973 UINT8 OcLock; 974 975 /** Offset 0x023F - Maximum Core Turbo Ratio Override 976 Maximum core turbo ratio override allows to increase CPU core frequency beyond the 977 fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 978 **/ 979 UINT8 CoreMaxOcRatio; 980 981 /** Offset 0x0240 - Core voltage mode 982 Core voltage mode; <b>0: Adaptive</b>; 1: Override. 983 $EN_DIS 984 **/ 985 UINT8 CoreVoltageMode; 986 987 /** Offset 0x0241 - Maximum clr turbo ratio override 988 Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the 989 fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 990 **/ 991 UINT8 RingMaxOcRatio; 992 993 /** Offset 0x0242 - Hyper Threading Enable/Disable 994 Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> 995 $EN_DIS 996 **/ 997 UINT8 HyperThreading; 998 999 /** Offset 0x0243 - Enable or Disable CPU Ratio Override 1000 Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. 1001 $EN_DIS 1002 **/ 1003 UINT8 CpuRatioOverride; 1004 1005 /** Offset 0x0244 - CPU ratio value 1006 CPU ratio value. Valid Range 0 to 63 1007 **/ 1008 UINT8 CpuRatio; 1009 1010 /** Offset 0x0245 - Boot frequency 1011 Sets the boot frequency starting from reset vector.- 0: Maximum battery performance. 1012 1: Maximum non-turbo performance. <b>2: Turbo performance </b> 1013 0:0, 1:1, 2:2 1014 **/ 1015 UINT8 BootFrequency; 1016 1017 /** Offset 0x0246 - Number of active cores 1018 Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2: 1019 2 </b>;<b>3: 3 </b> 1020 0:All, 1:1, 2:2, 3:3 1021 **/ 1022 UINT8 ActiveCoreCount; 1023 1024 /** Offset 0x0247 - Processor Early Power On Configuration FCLK setting 1025 <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 1026 2: 400 MHz. - 3: Reserved 1027 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved 1028 **/ 1029 UINT8 FClkFrequency; 1030 1031 /** Offset 0x0248 - Set JTAG power in C10 and deeper power states 1032 False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 1033 and deeper power states for debug purpose. <b>0: False</b>; 1: True. 1034 0: False, 1: True 1035 **/ 1036 UINT8 JtagC10PowerGateDisable; 1037 1038 /** Offset 0x0249 - Enable or Disable VMX 1039 Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. 1040 $EN_DIS 1041 **/ 1042 UINT8 VmxEnable; 1043 1044 /** Offset 0x024A - AVX2 Ratio Offset 1045 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio 1046 vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. 1047 **/ 1048 UINT8 Avx2RatioOffset; 1049 1050 /** Offset 0x024B - AVX3 Ratio Offset 1051 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio 1052 vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. 1053 **/ 1054 UINT8 Avx3RatioOffset; 1055 1056 /** Offset 0x024C - BCLK Adaptive Voltage Enable 1057 When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0: 1058 Disable;<b> 1: Enable 1059 $EN_DIS 1060 **/ 1061 UINT8 BclkAdaptiveVoltage; 1062 1063 /** Offset 0x024D - Reserved 1064 **/ 1065 UINT8 Reserved12; 1066 1067 /** Offset 0x024E - core voltage override 1068 The core voltage override which is applied to the entire range of cpu core frequencies. 1069 Valid Range 0 to 2000 1070 **/ 1071 UINT16 CoreVoltageOverride; 1072 1073 /** Offset 0x0250 - Core Turbo voltage Adaptive 1074 Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. 1075 Valid Range 0 to 2000 1076 **/ 1077 UINT16 CoreVoltageAdaptive; 1078 1079 /** Offset 0x0252 - Core Turbo voltage Offset 1080 The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 1081 **/ 1082 UINT16 CoreVoltageOffset; 1083 1084 /** Offset 0x0254 - Core PLL voltage offset 1085 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 1086 **/ 1087 UINT8 CorePllVoltageOffset; 1088 1089 /** Offset 0x0255 - Ring Downbin 1090 Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always 1091 lower than the core ratio.0: Disable; <b>1: Enable.</b> 1092 $EN_DIS 1093 **/ 1094 UINT8 RingDownBin; 1095 1096 /** Offset 0x0256 - Ring voltage mode 1097 Ring voltage mode; <b>0: Adaptive</b>; 1: Override. 1098 $EN_DIS 1099 **/ 1100 UINT8 RingVoltageMode; 1101 1102 /** Offset 0x0257 - TjMax Offset 1103 TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support 1104 TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 1105 **/ 1106 UINT8 TjMaxOffset; 1107 1108 /** Offset 0x0258 - Ring voltage override 1109 The ring voltage override which is applied to the entire range of cpu ring frequencies. 1110 Valid Range 0 to 2000 1111 **/ 1112 UINT16 RingVoltageOverride; 1113 1114 /** Offset 0x025A - Ring Turbo voltage Adaptive 1115 Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. 1116 Valid Range 0 to 2000 1117 **/ 1118 UINT16 RingVoltageAdaptive; 1119 1120 /** Offset 0x025C - Ring Turbo voltage Offset 1121 The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 1122 **/ 1123 UINT16 RingVoltageOffset; 1124 1125 /** Offset 0x025E - Enable CPU CrashLog 1126 Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>. 1127 $EN_DIS 1128 **/ 1129 UINT8 CpuCrashLogEnable; 1130 1131 /** Offset 0x025F - Reserved 1132 **/ 1133 UINT8 Reserved13[9]; 1134 1135 /** Offset 0x0268 - CPU Run Control 1136 Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2: 1137 No Change</b> 1138 0:Disabled, 1:Enabled, 2:No Change 1139 **/ 1140 UINT8 DebugInterfaceEnable; 1141 1142 /** Offset 0x0269 - CPU Run Control Lock 1143 Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>. 1144 $EN_DIS 1145 **/ 1146 UINT8 DebugInterfaceLockEnable; 1147 1148 /** Offset 0x026A - BiosGuard 1149 Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable 1150 $EN_DIS 1151 **/ 1152 UINT8 BiosGuard; 1153 1154 /** Offset 0x026B 1155 **/ 1156 UINT8 BiosGuardToolsInterface; 1157 1158 /** Offset 0x026C - Txt 1159 Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable 1160 $EN_DIS 1161 **/ 1162 UINT8 Txt; 1163 1164 /** Offset 0x026D - Reserved 1165 **/ 1166 UINT8 Reserved14[3]; 1167 1168 /** Offset 0x0270 - PrmrrSize 1169 Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable 1170 **/ 1171 UINT32 PrmrrSize; 1172 1173 /** Offset 0x0274 - SinitMemorySize 1174 Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable 1175 **/ 1176 UINT32 SinitMemorySize; 1177 1178 /** Offset 0x0278 - TxtDprMemoryBase 1179 Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable 1180 **/ 1181 UINT64 TxtDprMemoryBase; 1182 1183 /** Offset 0x0280 - TxtHeapMemorySize 1184 Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable 1185 **/ 1186 UINT32 TxtHeapMemorySize; 1187 1188 /** Offset 0x0284 - TxtDprMemorySize 1189 Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable 1190 **/ 1191 UINT32 TxtDprMemorySize; 1192 1193 /** Offset 0x0288 - BiosAcmBase 1194 Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable 1195 **/ 1196 UINT32 BiosAcmBase; 1197 1198 /** Offset 0x028C - BiosAcmSize 1199 Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable 1200 **/ 1201 UINT32 BiosAcmSize; 1202 1203 /** Offset 0x0290 - ApStartupBase 1204 Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable 1205 **/ 1206 UINT32 ApStartupBase; 1207 1208 /** Offset 0x0294 - TgaSize 1209 Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable 1210 **/ 1211 UINT32 TgaSize; 1212 1213 /** Offset 0x0298 - TxtLcpPdBase 1214 Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable 1215 **/ 1216 UINT64 TxtLcpPdBase; 1217 1218 /** Offset 0x02A0 - TxtLcpPdSize 1219 Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable 1220 **/ 1221 UINT64 TxtLcpPdSize; 1222 1223 /** Offset 0x02A8 - IsTPMPresence 1224 IsTPMPresence default values 1225 **/ 1226 UINT8 IsTPMPresence; 1227 1228 /** Offset 0x02A9 - Reserved 1229 **/ 1230 UINT8 Reserved15[6]; 1231 1232 /** Offset 0x02AF - Enable PCH HSIO PCIE Rx Set Ctle 1233 Enable PCH PCIe Gen 3 Set CTLE Value. 1234 **/ 1235 UINT8 PchPcieHsioRxSetCtleEnable[24]; 1236 1237 /** Offset 0x02C7 - PCH HSIO PCIE Rx Set Ctle Value 1238 PCH PCIe Gen 3 Set CTLE Value. 1239 **/ 1240 UINT8 PchPcieHsioRxSetCtle[24]; 1241 1242 /** Offset 0x02DF - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override 1243 0: Disable; 1: Enable. 1244 **/ 1245 UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; 1246 1247 /** Offset 0x02F7 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value 1248 PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. 1249 **/ 1250 UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; 1251 1252 /** Offset 0x030F - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override 1253 0: Disable; 1: Enable. 1254 **/ 1255 UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; 1256 1257 /** Offset 0x0327 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value 1258 PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. 1259 **/ 1260 UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; 1261 1262 /** Offset 0x033F - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override 1263 0: Disable; 1: Enable. 1264 **/ 1265 UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; 1266 1267 /** Offset 0x0357 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value 1268 PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. 1269 **/ 1270 UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; 1271 1272 /** Offset 0x036F - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override 1273 0: Disable; 1: Enable. 1274 **/ 1275 UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; 1276 1277 /** Offset 0x0387 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value 1278 PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. 1279 **/ 1280 UINT8 PchPcieHsioTxGen1DeEmph[24]; 1281 1282 /** Offset 0x039F - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override 1283 0: Disable; 1: Enable. 1284 **/ 1285 UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; 1286 1287 /** Offset 0x03B7 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value 1288 PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. 1289 **/ 1290 UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; 1291 1292 /** Offset 0x03CF - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override 1293 0: Disable; 1: Enable. 1294 **/ 1295 UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; 1296 1297 /** Offset 0x03E7 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value 1298 PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. 1299 **/ 1300 UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; 1301 1302 /** Offset 0x03FF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 1303 0: Disable; 1: Enable. 1304 **/ 1305 UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; 1306 1307 /** Offset 0x0407 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value 1308 PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. 1309 **/ 1310 UINT8 PchSataHsioRxGen1EqBoostMag[8]; 1311 1312 /** Offset 0x040F - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 1313 0: Disable; 1: Enable. 1314 **/ 1315 UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; 1316 1317 /** Offset 0x0417 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value 1318 PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. 1319 **/ 1320 UINT8 PchSataHsioRxGen2EqBoostMag[8]; 1321 1322 /** Offset 0x041F - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 1323 0: Disable; 1: Enable. 1324 **/ 1325 UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; 1326 1327 /** Offset 0x0427 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value 1328 PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. 1329 **/ 1330 UINT8 PchSataHsioRxGen3EqBoostMag[8]; 1331 1332 /** Offset 0x042F - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override 1333 0: Disable; 1: Enable. 1334 **/ 1335 UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; 1336 1337 /** Offset 0x0437 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value 1338 PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. 1339 **/ 1340 UINT8 PchSataHsioTxGen1DownscaleAmp[8]; 1341 1342 /** Offset 0x043F - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override 1343 0: Disable; 1: Enable. 1344 **/ 1345 UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; 1346 1347 /** Offset 0x0447 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value 1348 PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. 1349 **/ 1350 UINT8 PchSataHsioTxGen2DownscaleAmp[8]; 1351 1352 /** Offset 0x044F - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override 1353 0: Disable; 1: Enable. 1354 **/ 1355 UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; 1356 1357 /** Offset 0x0457 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value 1358 PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. 1359 **/ 1360 UINT8 PchSataHsioTxGen3DownscaleAmp[8]; 1361 1362 /** Offset 0x045F - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override 1363 0: Disable; 1: Enable. 1364 **/ 1365 UINT8 PchSataHsioTxGen1DeEmphEnable[8]; 1366 1367 /** Offset 0x0467 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting 1368 PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. 1369 **/ 1370 UINT8 PchSataHsioTxGen1DeEmph[8]; 1371 1372 /** Offset 0x046F - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 1373 0: Disable; 1: Enable. 1374 **/ 1375 UINT8 PchSataHsioTxGen2DeEmphEnable[8]; 1376 1377 /** Offset 0x0477 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting 1378 PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. 1379 **/ 1380 UINT8 PchSataHsioTxGen2DeEmph[8]; 1381 1382 /** Offset 0x047F - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 1383 0: Disable; 1: Enable. 1384 **/ 1385 UINT8 PchSataHsioTxGen3DeEmphEnable[8]; 1386 1387 /** Offset 0x0487 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting 1388 PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. 1389 **/ 1390 UINT8 PchSataHsioTxGen3DeEmph[8]; 1391 1392 /** Offset 0x048F - PCH LPC Enhance the port 8xh decoding 1393 Original LPC only decodes one byte of port 80h. 1394 $EN_DIS 1395 **/ 1396 UINT8 PchLpcEnhancePort8xhDecoding; 1397 1398 /** Offset 0x0490 - PCH Port80 Route 1399 Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. 1400 $EN_DIS 1401 **/ 1402 UINT8 PchPort80Route; 1403 1404 /** Offset 0x0491 - Enable SMBus ARP support 1405 Enable SMBus ARP support. 1406 $EN_DIS 1407 **/ 1408 UINT8 SmbusArpEnable; 1409 1410 /** Offset 0x0492 - Reserved 1411 **/ 1412 UINT8 Reserved16[2]; 1413 1414 /** Offset 0x0494 - SMBUS Base Address 1415 SMBUS Base Address (IO space). 1416 **/ 1417 UINT16 PchSmbusIoBase; 1418 1419 /** Offset 0x0496 - Enable SMBus Alert Pin 1420 Enable SMBus Alert Pin. 1421 $EN_DIS 1422 **/ 1423 UINT8 PchSmbAlertEnable; 1424 1425 /** Offset 0x0497 - Usage type for ClkSrc 1426 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use 1427 (free running), 0xFF: not used 1428 **/ 1429 UINT8 PcieClkSrcUsage[16]; 1430 1431 /** Offset 0x04A7 - ClkReq-to-ClkSrc mapping 1432 Number of ClkReq signal assigned to ClkSrc 1433 **/ 1434 UINT8 PcieClkSrcClkReq[16]; 1435 1436 /** Offset 0x04B7 - Reserved 1437 **/ 1438 UINT8 Reserved17[5]; 1439 1440 /** Offset 0x04BC - Enable PCIE RP Mask 1441 Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 1442 for port1, bit1 for port2, and so on. 1443 **/ 1444 UINT32 PcieRpEnableMask; 1445 1446 /** Offset 0x04C0 - Debug Interfaces 1447 Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, 1448 BIT2 - Not used. 1449 **/ 1450 UINT8 PcdDebugInterfaceFlags; 1451 1452 /** Offset 0x04C1 - Serial Io Uart Debug Controller Number 1453 Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT 1454 Core interface, it cannot be used for debug purpose. 1455 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 1456 **/ 1457 UINT8 SerialIoUartDebugControllerNumber; 1458 1459 /** Offset 0x04C2 - Serial Io Uart Debug Auto Flow 1460 Enables UART hardware flow control, CTS and RTS lines. 1461 $EN_DIS 1462 **/ 1463 UINT8 SerialIoUartDebugAutoFlow; 1464 1465 /** Offset 0x04C3 - Reserved 1466 **/ 1467 UINT8 Reserved18; 1468 1469 /** Offset 0x04C4 - Serial Io Uart Debug BaudRate 1470 Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 1471 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 1472 **/ 1473 UINT32 SerialIoUartDebugBaudRate; 1474 1475 /** Offset 0x04C8 - Serial Io Uart Debug Parity 1476 Set default Parity. 1477 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity 1478 **/ 1479 UINT8 SerialIoUartDebugParity; 1480 1481 /** Offset 0x04C9 - Serial Io Uart Debug Stop Bits 1482 Set default stop bits. 1483 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits 1484 **/ 1485 UINT8 SerialIoUartDebugStopBits; 1486 1487 /** Offset 0x04CA - Serial Io Uart Debug Data Bits 1488 Set default word length. 0: Default, 5,6,7,8 1489 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS 1490 **/ 1491 UINT8 SerialIoUartDebugDataBits; 1492 1493 /** Offset 0x04CB - Reserved 1494 **/ 1495 UINT8 Reserved19[5]; 1496 1497 /** Offset 0x04D0 - ISA Serial Base selection 1498 Select ISA Serial Base address. Default is 0x3F8. 1499 0:0x3F8, 1:0x2F8 1500 **/ 1501 UINT8 PcdIsaSerialUartBase; 1502 1503 /** Offset 0x04D1 - GT PLL voltage offset 1504 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 1505 **/ 1506 UINT8 GtPllVoltageOffset; 1507 1508 /** Offset 0x04D2 - Ring PLL voltage offset 1509 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 1510 **/ 1511 UINT8 RingPllVoltageOffset; 1512 1513 /** Offset 0x04D3 - System Agent PLL voltage offset 1514 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 1515 **/ 1516 UINT8 SaPllVoltageOffset; 1517 1518 /** Offset 0x04D4 - Memory Controller PLL voltage offset 1519 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 1520 **/ 1521 UINT8 McPllVoltageOffset; 1522 1523 /** Offset 0x04D5 - MRC Safe Config 1524 Enables/Disable MRC Safe Config 1525 $EN_DIS 1526 **/ 1527 UINT8 MrcSafeConfig; 1528 1529 /** Offset 0x04D6 - PcdSerialDebugBaudRate 1530 Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. 1531 3:9600, 4:19200, 6:56700, 7:115200 1532 **/ 1533 UINT8 PcdSerialDebugBaudRate; 1534 1535 /** Offset 0x04D7 - HobBufferSize 1536 Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB 1537 total HOB size). 1538 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value 1539 **/ 1540 UINT8 HobBufferSize; 1541 1542 /** Offset 0x04D8 - Early Command Training 1543 Enables/Disable Early Command Training 1544 $EN_DIS 1545 **/ 1546 UINT8 ECT; 1547 1548 /** Offset 0x04D9 - SenseAmp Offset Training 1549 Enables/Disable SenseAmp Offset Training 1550 $EN_DIS 1551 **/ 1552 UINT8 SOT; 1553 1554 /** Offset 0x04DA - Early ReadMPR Timing Centering 2D 1555 Enables/Disable Early ReadMPR Timing Centering 2D 1556 $EN_DIS 1557 **/ 1558 UINT8 ERDMPRTC2D; 1559 1560 /** Offset 0x04DB - Read MPR Training 1561 Enables/Disable Read MPR Training 1562 $EN_DIS 1563 **/ 1564 UINT8 RDMPRT; 1565 1566 /** Offset 0x04DC - Receive Enable Training 1567 Enables/Disable Receive Enable Training 1568 $EN_DIS 1569 **/ 1570 UINT8 RCVET; 1571 1572 /** Offset 0x04DD - Jedec Write Leveling 1573 Enables/Disable Jedec Write Leveling 1574 $EN_DIS 1575 **/ 1576 UINT8 JWRL; 1577 1578 /** Offset 0x04DE - Early Write Time Centering 2D 1579 Enables/Disable Early Write Time Centering 2D 1580 $EN_DIS 1581 **/ 1582 UINT8 EWRTC2D; 1583 1584 /** Offset 0x04DF - Early Read Time Centering 2D 1585 Enables/Disable Early Read Time Centering 2D 1586 $EN_DIS 1587 **/ 1588 UINT8 ERDTC2D; 1589 1590 /** Offset 0x04E0 - Write Timing Centering 1D 1591 Enables/Disable Write Timing Centering 1D 1592 $EN_DIS 1593 **/ 1594 UINT8 WRTC1D; 1595 1596 /** Offset 0x04E1 - Write Voltage Centering 1D 1597 Enables/Disable Write Voltage Centering 1D 1598 $EN_DIS 1599 **/ 1600 UINT8 WRVC1D; 1601 1602 /** Offset 0x04E2 - Read Timing Centering 1D 1603 Enables/Disable Read Timing Centering 1D 1604 $EN_DIS 1605 **/ 1606 UINT8 RDTC1D; 1607 1608 /** Offset 0x04E3 - Dimm ODT Training 1609 Enables/Disable Dimm ODT Training 1610 $EN_DIS 1611 **/ 1612 UINT8 DIMMODTT; 1613 1614 /** Offset 0x04E4 - DIMM RON Training 1615 Enables/Disable DIMM RON Training 1616 $EN_DIS 1617 **/ 1618 UINT8 DIMMRONT; 1619 1620 /** Offset 0x04E5 - Write Drive Strength/Equalization 2D 1621 Enables/Disable Write Drive Strength/Equalization 2D 1622 $EN_DIS 1623 **/ 1624 UINT8 WRDSEQT; 1625 1626 /** Offset 0x04E6 - Write Slew Rate Training 1627 Enables/Disable Write Slew Rate Training 1628 $EN_DIS 1629 **/ 1630 UINT8 WRSRT; 1631 1632 /** Offset 0x04E7 - Read ODT Training 1633 Enables/Disable Read ODT Training 1634 $EN_DIS 1635 **/ 1636 UINT8 RDODTT; 1637 1638 /** Offset 0x04E8 - Read Equalization Training 1639 Enables/Disable Read Equalization Training 1640 $EN_DIS 1641 **/ 1642 UINT8 RDEQT; 1643 1644 /** Offset 0x04E9 - Read Amplifier Training 1645 Enables/Disable Read Amplifier Training 1646 $EN_DIS 1647 **/ 1648 UINT8 RDAPT; 1649 1650 /** Offset 0x04EA - Write Timing Centering 2D 1651 Enables/Disable Write Timing Centering 2D 1652 $EN_DIS 1653 **/ 1654 UINT8 WRTC2D; 1655 1656 /** Offset 0x04EB - Read Timing Centering 2D 1657 Enables/Disable Read Timing Centering 2D 1658 $EN_DIS 1659 **/ 1660 UINT8 RDTC2D; 1661 1662 /** Offset 0x04EC - Write Voltage Centering 2D 1663 Enables/Disable Write Voltage Centering 2D 1664 $EN_DIS 1665 **/ 1666 UINT8 WRVC2D; 1667 1668 /** Offset 0x04ED - Read Voltage Centering 2D 1669 Enables/Disable Read Voltage Centering 2D 1670 $EN_DIS 1671 **/ 1672 UINT8 RDVC2D; 1673 1674 /** Offset 0x04EE - Command Voltage Centering 1675 Enables/Disable Command Voltage Centering 1676 $EN_DIS 1677 **/ 1678 UINT8 CMDVC; 1679 1680 /** Offset 0x04EF - Late Command Training 1681 Enables/Disable Late Command Training 1682 $EN_DIS 1683 **/ 1684 UINT8 LCT; 1685 1686 /** Offset 0x04F0 - Round Trip Latency Training 1687 Enables/Disable Round Trip Latency Training 1688 $EN_DIS 1689 **/ 1690 UINT8 RTL; 1691 1692 /** Offset 0x04F1 - Turn Around Timing Training 1693 Enables/Disable Turn Around Timing Training 1694 $EN_DIS 1695 **/ 1696 UINT8 TAT; 1697 1698 /** Offset 0x04F2 - Margin Limit Check 1699 Margin Limit Check. Choose level of margin check 1700 0:Disable, 1:L1, 2:L2, 3:Both 1701 **/ 1702 UINT8 MarginLimitCheck; 1703 1704 /** Offset 0x04F3 - Reserved 1705 **/ 1706 UINT8 Reserved20; 1707 1708 /** Offset 0x04F4 - Margin Limit L2 1709 % of L1 check for margin limit check 1710 **/ 1711 UINT16 MarginLimitL2; 1712 1713 /** Offset 0x04F6 - Memory Test 1714 Enables/Disable Memory Test 1715 $EN_DIS 1716 **/ 1717 UINT8 MEMTST; 1718 1719 /** Offset 0x04F7 - DIMM SPD Alias Test 1720 Enables/Disable DIMM SPD Alias Test 1721 $EN_DIS 1722 **/ 1723 UINT8 ALIASCHK; 1724 1725 /** Offset 0x04F8 - Receive Enable Centering 1D 1726 Enables/Disable Receive Enable Centering 1D 1727 $EN_DIS 1728 **/ 1729 UINT8 RCVENC1D; 1730 1731 /** Offset 0x04F9 - Retrain Margin Check 1732 Enables/Disable Retrain Margin Check 1733 $EN_DIS 1734 **/ 1735 UINT8 RMC; 1736 1737 /** Offset 0x04FA - Write Drive Strength Up/Dn independently 1738 Enables/Disable Write Drive Strength Up/Dn independently 1739 $EN_DIS 1740 **/ 1741 UINT8 WRDSUDT; 1742 1743 /** Offset 0x04FB - Read Voltage Centering 1744 Enables/Disable Read Voltage Centering 1745 $EN_DIS 1746 **/ 1747 UINT8 RDVC1D; 1748 1749 /** Offset 0x04FC - Write TCO Comp Training 1750 Enables/Disable Write TCO Comp Training 1751 $EN_DIS 1752 **/ 1753 UINT8 TXTCO; 1754 1755 /** Offset 0x04FD - Clock TCO Comp Training 1756 Enables/Disable Clock TCO Comp Training 1757 $EN_DIS 1758 **/ 1759 UINT8 CLKTCO; 1760 1761 /** Offset 0x04FE - Dimm ODT CA Training 1762 Enables/Disable Dimm ODT CA Training 1763 $EN_DIS 1764 **/ 1765 UINT8 DIMMODTCA; 1766 1767 /** Offset 0x04FF - Write TCO Dqs Training 1768 Enables/Disable Write TCO Dqs Training 1769 $EN_DIS 1770 **/ 1771 UINT8 TXTCODQS; 1772 1773 /** Offset 0x0500 - Duty Cycle Correction 1774 Enables/Disable Duty Cycle Correction 1775 $EN_DIS 1776 **/ 1777 UINT8 DCC; 1778 1779 /** Offset 0x0501 - DQ DFE Training 1780 Enable/Disable DQ DFE Training 1781 $EN_DIS 1782 **/ 1783 UINT8 DQDFE; 1784 1785 /** Offset 0x0502 - Sense Amplifier Correction Training 1786 Enable/Disable Sense Amplifier Correction Training 1787 $EN_DIS 1788 **/ 1789 UINT8 SOTC; 1790 1791 /** Offset 0x0503 - ECC Support 1792 Enables/Disable ECC Support 1793 $EN_DIS 1794 **/ 1795 UINT8 EccSupport; 1796 1797 /** Offset 0x0504 - Memory Remap 1798 Enables/Disable Memory Remap 1799 $EN_DIS 1800 **/ 1801 UINT8 RemapEnable; 1802 1803 /** Offset 0x0505 - MRC Time Measure 1804 Enable/Disable MRC Time Measure 1805 $EN_DIS 1806 **/ 1807 UINT8 MrcTimeMeasure; 1808 1809 /** Offset 0x0506 - MRC Force Training on Warm 1810 Enables/Disable the MRC training on warm boot 1811 $EN_DIS 1812 **/ 1813 UINT8 MrcTrainOnWarm; 1814 1815 /** Offset 0x0507 - Rank Interleave support 1816 Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at 1817 the same time. 1818 $EN_DIS 1819 **/ 1820 UINT8 RankInterleave; 1821 1822 /** Offset 0x0508 - Enhanced Interleave support 1823 Enables/Disable Enhanced Interleave support 1824 $EN_DIS 1825 **/ 1826 UINT8 EnhancedInterleave; 1827 1828 /** Offset 0x0509 - Memory Trace 1829 Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of 1830 equal size. This option may change TOLUD and REMAP values as needed. 1831 $EN_DIS 1832 **/ 1833 UINT8 MemoryTrace; 1834 1835 /** Offset 0x050A - Ch Hash Support 1836 Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode 1837 $EN_DIS 1838 **/ 1839 UINT8 ChHashEnable; 1840 1841 /** Offset 0x050B - Extern Therm Status 1842 Enables/Disable Extern Therm Status 1843 $EN_DIS 1844 **/ 1845 UINT8 EnableExtts; 1846 1847 /** Offset 0x050C - Closed Loop Therm Manage 1848 Enables/Disable Closed Loop Therm Manage 1849 $EN_DIS 1850 **/ 1851 UINT8 EnableCltm; 1852 1853 /** Offset 0x050D - Open Loop Therm Manage 1854 Enables/Disable Open Loop Therm Manage 1855 $EN_DIS 1856 **/ 1857 UINT8 EnableOltm; 1858 1859 /** Offset 0x050E - DDR PowerDown and idle counter 1860 Enables/Disable DDR PowerDown and idle counter 1861 $EN_DIS 1862 **/ 1863 UINT8 EnablePwrDn; 1864 1865 /** Offset 0x050F - DDR PowerDown and idle counter - LPDDR 1866 Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) 1867 $EN_DIS 1868 **/ 1869 UINT8 EnablePwrDnLpddr; 1870 1871 /** Offset 0x0510 - Use user provided power weights, scale factor, and channel power floor values 1872 Enables/Disable Use user provided power weights, scale factor, and channel power 1873 floor values 1874 $EN_DIS 1875 **/ 1876 UINT8 UserPowerWeightsEn; 1877 1878 /** Offset 0x0511 - RAPL PL Lock 1879 Enables/Disable RAPL PL Lock 1880 $EN_DIS 1881 **/ 1882 UINT8 RaplLim2Lock; 1883 1884 /** Offset 0x0512 - RAPL PL 2 enable 1885 Enables/Disable RAPL PL 2 enable 1886 $EN_DIS 1887 **/ 1888 UINT8 RaplLim2Ena; 1889 1890 /** Offset 0x0513 - RAPL PL 1 enable 1891 Enables/Disable RAPL PL 1 enable 1892 $EN_DIS 1893 **/ 1894 UINT8 RaplLim1Ena; 1895 1896 /** Offset 0x0514 - SelfRefresh Enable 1897 Enables/Disable SelfRefresh Enable 1898 $EN_DIS 1899 **/ 1900 UINT8 SrefCfgEna; 1901 1902 /** Offset 0x0515 - Throttler CKEMin Defeature - LPDDR 1903 Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) 1904 $EN_DIS 1905 **/ 1906 UINT8 ThrtCkeMinDefeatLpddr; 1907 1908 /** Offset 0x0516 - Throttler CKEMin Defeature 1909 Enables/Disable Throttler CKEMin Defeature 1910 $EN_DIS 1911 **/ 1912 UINT8 ThrtCkeMinDefeat; 1913 1914 /** Offset 0x0517 - Enable RH Prevention 1915 Enables/Disable RH Prevention 1916 $EN_DIS 1917 **/ 1918 UINT8 RhPrevention; 1919 1920 /** Offset 0x0518 - Exit On Failure (MRC) 1921 Enables/Disable Exit On Failure (MRC) 1922 $EN_DIS 1923 **/ 1924 UINT8 ExitOnFailure; 1925 1926 /** Offset 0x0519 - LPDDR Thermal Sensor 1927 Enables/Disable LPDDR Thermal Sensor 1928 $EN_DIS 1929 **/ 1930 UINT8 DdrThermalSensor; 1931 1932 /** Offset 0x051A - EV Loader 1933 Enable/Disable EV Loader Functionality 1934 $EN_DIS 1935 **/ 1936 UINT8 EvLoader; 1937 1938 /** Offset 0x051B - Reserved 1939 **/ 1940 UINT8 Reserved21; 1941 1942 /** Offset 0x051C - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP 1943 Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP 1944 $EN_DIS 1945 **/ 1946 UINT8 Ddr4DdpSharedClock; 1947 1948 /** Offset 0x051D - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP 1949 ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP 1950 $EN_DIS 1951 **/ 1952 UINT8 Ddr4DdpSharedZq; 1953 1954 /** Offset 0x051E - Ch Hash Interleaved Bit 1955 Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave 1956 the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 1957 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 1958 **/ 1959 UINT8 ChHashInterleaveBit; 1960 1961 /** Offset 0x051F - Reserved 1962 **/ 1963 UINT8 Reserved22; 1964 1965 /** Offset 0x0520 - Ch Hash Mask 1966 Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to 1967 BITS [19:6] Default is 0x30CC 1968 **/ 1969 UINT16 ChHashMask; 1970 1971 /** Offset 0x0522 - Reserved 1972 **/ 1973 UINT8 Reserved23[2]; 1974 1975 /** Offset 0x0524 - Base reference clock value 1976 Base reference clock value, in Hertz(Default is 125Hz) 1977 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz 1978 **/ 1979 UINT32 BClkFrequency; 1980 1981 /** Offset 0x0528 - Extended Bank Hashing 1982 Eanble/Disable ExtendedBankHashing 1983 $EN_DIS 1984 **/ 1985 UINT8 ExtendedBankHashing; 1986 1987 /** Offset 0x0529 - Energy Scale Factor 1988 Energy Scale Factor, Default is 4 1989 **/ 1990 UINT8 EnergyScaleFact; 1991 1992 /** Offset 0x052A - CMD Slew Rate Training 1993 Enable/Disable CMD Slew Rate Training 1994 $EN_DIS 1995 **/ 1996 UINT8 CMDSR; 1997 1998 /** Offset 0x052B - Reserved 1999 **/ 2000 UINT8 Reserved24; 2001 2002 /** Offset 0x052C - EPG DIMM Idd3N 2003 Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on 2004 a per DIMM basis. Default is 26 2005 **/ 2006 UINT16 Idd3n; 2007 2008 /** Offset 0x052E - EPG DIMM Idd3P 2009 Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated 2010 on a per DIMM basis. Default is 11 2011 **/ 2012 UINT16 Idd3p; 2013 2014 /** Offset 0x0530 - CMD Drive Strength and Tx Equalization 2015 Enable/Disable CMD Drive Strength and Tx Equalization 2016 $EN_DIS 2017 **/ 2018 UINT8 CMDDSEQ; 2019 2020 /** Offset 0x0531 - CMD Normalization 2021 Enable/Disable CMD Normalization 2022 $EN_DIS 2023 **/ 2024 UINT8 CMDNORM; 2025 2026 /** Offset 0x0532 - Early DQ Write Drive Strength and Equalization Training 2027 Enable/Disable Early DQ Write Drive Strength and Equalization Training 2028 $EN_DIS 2029 **/ 2030 UINT8 EWRDSEQ; 2031 2032 /** Offset 0x0533 - RH Activation Probability 2033 RH Activation Probability, Probability value is 1/2^(inputvalue) 2034 **/ 2035 UINT8 RhActProbability; 2036 2037 /** Offset 0x0534 - RAPL PL 2 WindowX 2038 Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) 2039 **/ 2040 UINT8 RaplLim2WindX; 2041 2042 /** Offset 0x0535 - RAPL PL 2 WindowY 2043 Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) 2044 **/ 2045 UINT8 RaplLim2WindY; 2046 2047 /** Offset 0x0536 - RAPL PL 1 WindowX 2048 Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) 2049 **/ 2050 UINT8 RaplLim1WindX; 2051 2052 /** Offset 0x0537 - RAPL PL 1 WindowY 2053 Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) 2054 **/ 2055 UINT8 RaplLim1WindY; 2056 2057 /** Offset 0x0538 - RAPL PL 2 Power 2058 range[0;2^14-1]= [2047.875;0]in W, (224= Def) 2059 **/ 2060 UINT16 RaplLim2Pwr; 2061 2062 /** Offset 0x053A - RAPL PL 1 Power 2063 range[0;2^14-1]= [2047.875;0]in W, (224= Def) 2064 **/ 2065 UINT16 RaplLim1Pwr; 2066 2067 /** Offset 0x053C - Warm Threshold Ch0 Dimm0 2068 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 2069 **/ 2070 UINT8 WarmThresholdCh0Dimm0; 2071 2072 /** Offset 0x053D - Warm Threshold Ch0 Dimm1 2073 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 2074 **/ 2075 UINT8 WarmThresholdCh0Dimm1; 2076 2077 /** Offset 0x053E - Warm Threshold Ch1 Dimm0 2078 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 2079 **/ 2080 UINT8 WarmThresholdCh1Dimm0; 2081 2082 /** Offset 0x053F - Warm Threshold Ch1 Dimm1 2083 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 2084 **/ 2085 UINT8 WarmThresholdCh1Dimm1; 2086 2087 /** Offset 0x0540 - Hot Threshold Ch0 Dimm0 2088 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 2089 **/ 2090 UINT8 HotThresholdCh0Dimm0; 2091 2092 /** Offset 0x0541 - Hot Threshold Ch0 Dimm1 2093 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 2094 **/ 2095 UINT8 HotThresholdCh0Dimm1; 2096 2097 /** Offset 0x0542 - Hot Threshold Ch1 Dimm0 2098 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 2099 **/ 2100 UINT8 HotThresholdCh1Dimm0; 2101 2102 /** Offset 0x0543 - Hot Threshold Ch1 Dimm1 2103 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 2104 **/ 2105 UINT8 HotThresholdCh1Dimm1; 2106 2107 /** Offset 0x0544 - Warm Budget Ch0 Dimm0 2108 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM 2109 **/ 2110 UINT8 WarmBudgetCh0Dimm0; 2111 2112 /** Offset 0x0545 - Warm Budget Ch0 Dimm1 2113 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM 2114 **/ 2115 UINT8 WarmBudgetCh0Dimm1; 2116 2117 /** Offset 0x0546 - Warm Budget Ch1 Dimm0 2118 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM 2119 **/ 2120 UINT8 WarmBudgetCh1Dimm0; 2121 2122 /** Offset 0x0547 - Warm Budget Ch1 Dimm1 2123 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM 2124 **/ 2125 UINT8 WarmBudgetCh1Dimm1; 2126 2127 /** Offset 0x0548 - Hot Budget Ch0 Dimm0 2128 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM 2129 **/ 2130 UINT8 HotBudgetCh0Dimm0; 2131 2132 /** Offset 0x0549 - Hot Budget Ch0 Dimm1 2133 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM 2134 **/ 2135 UINT8 HotBudgetCh0Dimm1; 2136 2137 /** Offset 0x054A - Hot Budget Ch1 Dimm0 2138 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM 2139 **/ 2140 UINT8 HotBudgetCh1Dimm0; 2141 2142 /** Offset 0x054B - Hot Budget Ch1 Dimm1 2143 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM 2144 **/ 2145 UINT8 HotBudgetCh1Dimm1; 2146 2147 /** Offset 0x054C - Idle Energy Ch0Dimm0 2148 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) 2149 **/ 2150 UINT8 IdleEnergyCh0Dimm0; 2151 2152 /** Offset 0x054D - Idle Energy Ch0Dimm1 2153 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) 2154 **/ 2155 UINT8 IdleEnergyCh0Dimm1; 2156 2157 /** Offset 0x054E - Idle Energy Ch1Dimm0 2158 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) 2159 **/ 2160 UINT8 IdleEnergyCh1Dimm0; 2161 2162 /** Offset 0x054F - Idle Energy Ch1Dimm1 2163 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) 2164 **/ 2165 UINT8 IdleEnergyCh1Dimm1; 2166 2167 /** Offset 0x0550 - PowerDown Energy Ch0Dimm0 2168 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) 2169 **/ 2170 UINT8 PdEnergyCh0Dimm0; 2171 2172 /** Offset 0x0551 - PowerDown Energy Ch0Dimm1 2173 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) 2174 **/ 2175 UINT8 PdEnergyCh0Dimm1; 2176 2177 /** Offset 0x0552 - PowerDown Energy Ch1Dimm0 2178 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) 2179 **/ 2180 UINT8 PdEnergyCh1Dimm0; 2181 2182 /** Offset 0x0553 - PowerDown Energy Ch1Dimm1 2183 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) 2184 **/ 2185 UINT8 PdEnergyCh1Dimm1; 2186 2187 /** Offset 0x0554 - Activate Energy Ch0Dimm0 2188 Activate Energy Contribution, range[255;0],(172= Def) 2189 **/ 2190 UINT8 ActEnergyCh0Dimm0; 2191 2192 /** Offset 0x0555 - Activate Energy Ch0Dimm1 2193 Activate Energy Contribution, range[255;0],(172= Def) 2194 **/ 2195 UINT8 ActEnergyCh0Dimm1; 2196 2197 /** Offset 0x0556 - Activate Energy Ch1Dimm0 2198 Activate Energy Contribution, range[255;0],(172= Def) 2199 **/ 2200 UINT8 ActEnergyCh1Dimm0; 2201 2202 /** Offset 0x0557 - Activate Energy Ch1Dimm1 2203 Activate Energy Contribution, range[255;0],(172= Def) 2204 **/ 2205 UINT8 ActEnergyCh1Dimm1; 2206 2207 /** Offset 0x0558 - Read Energy Ch0Dimm0 2208 Read Energy Contribution, range[255;0],(212= Def) 2209 **/ 2210 UINT8 RdEnergyCh0Dimm0; 2211 2212 /** Offset 0x0559 - Read Energy Ch0Dimm1 2213 Read Energy Contribution, range[255;0],(212= Def) 2214 **/ 2215 UINT8 RdEnergyCh0Dimm1; 2216 2217 /** Offset 0x055A - Read Energy Ch1Dimm0 2218 Read Energy Contribution, range[255;0],(212= Def) 2219 **/ 2220 UINT8 RdEnergyCh1Dimm0; 2221 2222 /** Offset 0x055B - Read Energy Ch1Dimm1 2223 Read Energy Contribution, range[255;0],(212= Def) 2224 **/ 2225 UINT8 RdEnergyCh1Dimm1; 2226 2227 /** Offset 0x055C - Write Energy Ch0Dimm0 2228 Write Energy Contribution, range[255;0],(221= Def) 2229 **/ 2230 UINT8 WrEnergyCh0Dimm0; 2231 2232 /** Offset 0x055D - Write Energy Ch0Dimm1 2233 Write Energy Contribution, range[255;0],(221= Def) 2234 **/ 2235 UINT8 WrEnergyCh0Dimm1; 2236 2237 /** Offset 0x055E - Write Energy Ch1Dimm0 2238 Write Energy Contribution, range[255;0],(221= Def) 2239 **/ 2240 UINT8 WrEnergyCh1Dimm0; 2241 2242 /** Offset 0x055F - Write Energy Ch1Dimm1 2243 Write Energy Contribution, range[255;0],(221= Def) 2244 **/ 2245 UINT8 WrEnergyCh1Dimm1; 2246 2247 /** Offset 0x0560 - Throttler CKEMin Timer 2248 Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). 2249 Dfault is 0x30 2250 **/ 2251 UINT8 ThrtCkeMinTmr; 2252 2253 /** Offset 0x0561 - Cke Rank Mapping 2254 Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies 2255 which rank CKE[i] goes to. 2256 **/ 2257 UINT8 CkeRankMapping; 2258 2259 /** Offset 0x0562 - Rapl Power Floor Ch0 2260 Power budget ,range[255;0],(0= 5.3W Def) 2261 **/ 2262 UINT8 RaplPwrFlCh0; 2263 2264 /** Offset 0x0563 - Rapl Power Floor Ch1 2265 Power budget ,range[255;0],(0= 5.3W Def) 2266 **/ 2267 UINT8 RaplPwrFlCh1; 2268 2269 /** Offset 0x0564 - Command Rate Support 2270 CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs 2271 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS 2272 **/ 2273 UINT8 EnCmdRate; 2274 2275 /** Offset 0x0565 - REFRESH_2X_MODE 2276 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot 2277 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only 2278 **/ 2279 UINT8 Refresh2X; 2280 2281 /** Offset 0x0566 - Energy Performance Gain 2282 Enable/disable(default) Energy Performance Gain. 2283 $EN_DIS 2284 **/ 2285 UINT8 EpgEnable; 2286 2287 /** Offset 0x0567 - Row Hammer Solution 2288 Type of method used to prevent Row Hammer. Default is 2x Refresh 2289 0:Hardware RHP, 1:2x Refresh 2290 **/ 2291 UINT8 RhSolution; 2292 2293 /** Offset 0x0568 - User Manual Threshold 2294 Disabled: Predefined threshold will be used.\n 2295 Enabled: User Input will be used. 2296 $EN_DIS 2297 **/ 2298 UINT8 UserThresholdEnable; 2299 2300 /** Offset 0x0569 - User Manual Budget 2301 Disabled: Configuration of memories will defined the Budget value.\n 2302 Enabled: User Input will be used. 2303 $EN_DIS 2304 **/ 2305 UINT8 UserBudgetEnable; 2306 2307 /** Offset 0x056A - TcritMax 2308 Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax 2309 has to be greater than THIGHMax .\n 2310 Critical temperature will be TcritMax 2311 **/ 2312 UINT8 TsodTcritMax; 2313 2314 /** Offset 0x056B - Event mode 2315 Disable:Comparator mode.\n 2316 Enable:Interrupt mode 2317 $EN_DIS 2318 **/ 2319 UINT8 TsodEventMode; 2320 2321 /** Offset 0x056C - EVENT polarity 2322 Disable:Active LOW.\n 2323 Enable:Active HIGH 2324 $EN_DIS 2325 **/ 2326 UINT8 TsodEventPolarity; 2327 2328 /** Offset 0x056D - Critical event only 2329 Disable:Trips on alarm or critical.\n 2330 Enable:Trips only if criticaal temperature is reached 2331 $EN_DIS 2332 **/ 2333 UINT8 TsodCriticalEventOnly; 2334 2335 /** Offset 0x056E - Event output control 2336 Disable:Event output disable.\n 2337 Enable:Event output enabled 2338 $EN_DIS 2339 **/ 2340 UINT8 TsodEventOutputControl; 2341 2342 /** Offset 0x056F - Alarm window lock bit 2343 Disable:Alarm trips are not locked and can be changed.\n 2344 Enable:Alarm trips are locked and cannot be changed 2345 $EN_DIS 2346 **/ 2347 UINT8 TsodAlarmwindowLockBit; 2348 2349 /** Offset 0x0570 - Critical trip lock bit 2350 Disable:Critical trip is not locked and can be changed.\n 2351 Enable:Critical trip is locked and cannot be changed 2352 $EN_DIS 2353 **/ 2354 UINT8 TsodCriticaltripLockBit; 2355 2356 /** Offset 0x0571 - Shutdown mode 2357 Disable:Temperature sensor enable.\n 2358 Enable:Temperature sensor disable 2359 $EN_DIS 2360 **/ 2361 UINT8 TsodShutdownMode; 2362 2363 /** Offset 0x0572 - ThighMax 2364 Thigh = ThighMax (Default is 93) 2365 **/ 2366 UINT8 TsodThigMax; 2367 2368 /** Offset 0x0573 - User Manual Thig and Tcrit 2369 Disabled(Default): Temperature will be given by the configuration of memories and 2370 1x or 2xrefresh rate.\n 2371 Enabled: User Input will define for Thigh and Tcrit. 2372 $EN_DIS 2373 **/ 2374 UINT8 TsodManualEnable; 2375 2376 /** Offset 0x0574 - Force OLTM or 2X Refresh when needed 2377 Disabled(Default): = Force OLTM.\n 2378 Enabled: = Force 2x Refresh. 2379 $EN_DIS 2380 **/ 2381 UINT8 ForceOltmOrRefresh2x; 2382 2383 /** Offset 0x0575 - Pwr Down Idle Timer 2384 The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means 2385 AUTO: 64 for ULX/ULT, 128 for DT/Halo 2386 **/ 2387 UINT8 PwdwnIdleCounter; 2388 2389 /** Offset 0x0576 - Reserved 2390 **/ 2391 UINT8 Reserved25; 2392 2393 /** Offset 0x0577 - Bitmask of ranks that have CA bus terminated 2394 Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, 2395 Rank0 is terminating and Rank1 is non-terminating</b> 2396 **/ 2397 UINT8 CmdRanksTerminated; 2398 2399 /** Offset 0x0578 - Throttler CKEMin Timer for LPDDR 2400 LPDDR Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH 2401 (4). Dfault is 0x40 2402 **/ 2403 UINT8 ThrtCkeMinTmrLpddr; 2404 2405 /** Offset 0x0579 - Retrain on Fast Fail 2406 Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled 2407 $EN_DIS 2408 **/ 2409 UINT8 RetrainOnFastFail; 2410 2411 /** Offset 0x057A - Rank Margin Tool Per Bit 2412 Enable/disable Rank Margin Tool Per Bit. 2413 $EN_DIS 2414 **/ 2415 UINT8 RMTBIT; 2416 2417 /** Offset 0x057B - PcdSerialDebugLevel 2418 Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, 2419 Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, 2420 Info & Verbose. 2421 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load 2422 Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose 2423 **/ 2424 UINT8 PcdSerialDebugLevel; 2425 2426 /** Offset 0x057C - Fivr Faults 2427 Fivr Faults; 0: Disabled; <b>1: Enabled.</b> 2428 $EN_DIS 2429 **/ 2430 UINT8 FivrFaults; 2431 2432 /** Offset 0x057D - Fivr Efficiency 2433 Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b> 2434 $EN_DIS 2435 **/ 2436 UINT8 FivrEfficiency; 2437 2438 /** Offset 0x057E - Safe Mode Support 2439 This option configures the varous items in the IO and MC to be more conservative.(def=Disable) 2440 $EN_DIS 2441 **/ 2442 UINT8 SafeMode; 2443 2444 /** Offset 0x057F - Ask MRC to clear memory content 2445 Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory. 2446 $EN_DIS 2447 **/ 2448 UINT8 CleanMemory; 2449 2450 /** Offset 0x0580 - LpDdrDqDqsReTraining 2451 Enables/Disable LpDdrDqDqsReTraining 2452 $EN_DIS 2453 **/ 2454 UINT8 LpDdrDqDqsReTraining; 2455 2456 /** Offset 0x0581 - Reserved 2457 **/ 2458 UINT8 Reserved26; 2459 2460 /** Offset 0x0582 - Post Code Output Port 2461 This option configures Post Code Output Port 2462 **/ 2463 UINT16 PostCodeOutputPort; 2464 2465 /** Offset 0x0584 - RMTLoopCount 2466 Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO 2467 **/ 2468 UINT8 RMTLoopCount; 2469 2470 /** Offset 0x0585 - TCSS Compatible Revision ID Enable 2471 Set TCSS Crid . 0:Stepping Revision ID 1:Compatible Revision ID 2472 $EN_DIS 2473 **/ 2474 UINT8 CridEnable; 2475 2476 /** Offset 0x0586 - Reserved 2477 **/ 2478 UINT8 Reserved27[18]; 2479 2480 /** Offset 0x0598 - Generate BIOS Data ACPI Table 2481 Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it 2482 $EN_DIS 2483 **/ 2484 UINT8 BdatEnable; 2485 2486 /** Offset 0x0599 - BdatTestType 2487 Indicates the type of Memory Training data to populate into the BDAT ACPI table. 2488 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D 2489 **/ 2490 UINT8 BdatTestType; 2491 2492 /** Offset 0x059A - Size of PCIe IMR. 2493 Size of PCIe IMR in megabytes 2494 **/ 2495 UINT16 PcieImrSize; 2496 2497 /** Offset 0x059C - Enable PCIe IMR 2498 0: Disable(AUTO), 1: Enable 2499 $EN_DIS 2500 **/ 2501 UINT8 PcieImrEnabled; 2502 2503 /** Offset 0x059D - Reserved 2504 **/ 2505 UINT8 Reserved28[2]; 2506 2507 /** Offset 0x059F - SerialDebugMrcLevel 2508 MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, 2509 Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, 2510 Info & Verbose. 2511 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load 2512 Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose 2513 **/ 2514 UINT8 SerialDebugMrcLevel; 2515 2516 /** Offset 0x05A0 - Reserved 2517 **/ 2518 UINT8 Reserved29[18]; 2519 2520 /** Offset 0x05B2 - Skip external display device scanning 2521 Enable: Do not scan for external display device, Disable (Default): Scan external 2522 display devices 2523 $EN_DIS 2524 **/ 2525 UINT8 SkipExtGfxScan; 2526 2527 /** Offset 0x05B3 - Lock PCU Thermal Management registers 2528 Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 2529 $EN_DIS 2530 **/ 2531 UINT8 LockPTMregs; 2532 2533 /** Offset 0x05B4 - Reserved 2534 **/ 2535 UINT8 Reserved30; 2536 2537 /** Offset 0x05B5 - Panel Power Enable 2538 Control for enabling/disabling VDD force bit (Required only for early enabling of 2539 eDP panel). 0=Disable, 1(Default)=Enable 2540 $EN_DIS 2541 **/ 2542 UINT8 PanelPowerEnable; 2543 2544 /** Offset 0x05B6 - Reserved 2545 **/ 2546 UINT8 Reserved31[100]; 2547 2548 /** Offset 0x061A - TotalFlashSize 2549 Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable 2550 **/ 2551 UINT16 TotalFlashSize; 2552 2553 /** Offset 0x061C - BiosSize 2554 The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != 2555 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected 2556 Range) so that a BIOS Update Script can be stored in the DPR. 2557 **/ 2558 UINT16 BiosSize; 2559 2560 /** Offset 0x061E - TxtAcheckRequest 2561 Enable/Disable. When Enabled, after memory training is done MRC will request an 2562 ACHECK (Memory Alias Check) be done by TXT. 2563 $EN_DIS 2564 **/ 2565 UINT8 TxtAcheckRequest; 2566 2567 /** Offset 0x061F - Reserved 2568 **/ 2569 UINT8 Reserved32[11]; 2570 2571 /** Offset 0x062A - Smbus dynamic power gating 2572 Disable or Enable Smbus dynamic power gating. 2573 $EN_DIS 2574 **/ 2575 UINT8 SmbusDynamicPowerGating; 2576 2577 /** Offset 0x062B - Disable and Lock Watch Dog Register 2578 Set 1 to clear WDT status, then disable and lock WDT registers. 2579 $EN_DIS 2580 **/ 2581 UINT8 WdtDisableAndLock; 2582 2583 /** Offset 0x062C - SMBUS SPD Write Disable 2584 Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write 2585 Disable bit. For security recommendations, SPD write disable bit must be set. 2586 $EN_DIS 2587 **/ 2588 UINT8 SmbusSpdWriteDisable; 2589 2590 /** Offset 0x062D - VC Type 2591 Virtual Channel Type Select: 0: VC0, 1: VC1. 2592 0: VC0, 1: VC1 2593 **/ 2594 UINT8 PchHdaVcType; 2595 2596 /** Offset 0x062E - Universal Audio Architecture compliance for DSP enabled system 2597 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox 2598 driver or SST driver supported). 2599 $EN_DIS 2600 **/ 2601 UINT8 PchHdaDspUaaCompliance; 2602 2603 /** Offset 0x062F - Enable HD Audio Link 2604 Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. 2605 $EN_DIS 2606 **/ 2607 UINT8 PchHdaAudioLinkHdaEnable; 2608 2609 /** Offset 0x0630 - Reserved 2610 **/ 2611 UINT8 Reserved33[3]; 2612 2613 /** Offset 0x0633 - Enable HD Audio DMIC_N Link 2614 Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. 2615 **/ 2616 UINT8 PchHdaAudioLinkDmicEnable[2]; 2617 2618 /** Offset 0x0635 - Reserved 2619 **/ 2620 UINT8 Reserved34[19]; 2621 2622 /** Offset 0x0648 - Enable HD Audio DSP 2623 Enable/disable HD Audio DSP feature. 2624 $EN_DIS 2625 **/ 2626 UINT8 PchHdaDspEnable; 2627 2628 /** Offset 0x0649 - Reserved 2629 **/ 2630 UINT8 Reserved35[11]; 2631 2632 /** Offset 0x0654 - Enable HD Audio SSP0 Link 2633 Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 2634 **/ 2635 UINT8 PchHdaAudioLinkSspEnable[6]; 2636 2637 /** Offset 0x065A - Enable HD Audio SoundWire#N Link 2638 Enable/disable HD Audio SNDW#N link. Muxed with HDA. 2639 **/ 2640 UINT8 PchHdaAudioLinkSndwEnable[4]; 2641 2642 /** Offset 0x065E - iDisp-Link Frequency 2643 iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 2644 4: 96MHz, 3: 48MHz 2645 **/ 2646 UINT8 PchHdaIDispLinkFrequency; 2647 2648 /** Offset 0x065F - iDisp-Link T-mode 2649 iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 2650 0: 2T, 2: 4T, 3: 8T, 4: 16T 2651 **/ 2652 UINT8 PchHdaIDispLinkTmode; 2653 2654 /** Offset 0x0660 - iDisplay Audio Codec disconnection 2655 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. 2656 $EN_DIS 2657 **/ 2658 UINT8 PchHdaIDispCodecDisconnect; 2659 2660 /** Offset 0x0661 - Force ME DID Init Status 2661 Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set 2662 ME DID init stat value 2663 $EN_DIS 2664 **/ 2665 UINT8 DidInitStat; 2666 2667 /** Offset 0x0662 - CPU Replaced Polling Disable 2668 Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop 2669 $EN_DIS 2670 **/ 2671 UINT8 DisableCpuReplacedPolling; 2672 2673 /** Offset 0x0663 - Check HECI message before send 2674 Test, 0: disable, 1: enable, Enable/Disable message check. 2675 $EN_DIS 2676 **/ 2677 UINT8 DisableMessageCheck; 2678 2679 /** Offset 0x0664 - Skip MBP HOB 2680 Test, 0: disable, 1: enable, Enable/Disable MOB HOB. 2681 $EN_DIS 2682 **/ 2683 UINT8 SkipMbpHob; 2684 2685 /** Offset 0x0665 - HECI2 Interface Communication 2686 Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. 2687 $EN_DIS 2688 **/ 2689 UINT8 HeciCommunication2; 2690 2691 /** Offset 0x0666 - Enable KT device 2692 Test, 0: disable, 1: enable, Enable or Disable KT device. 2693 $EN_DIS 2694 **/ 2695 UINT8 KtDeviceEnable; 2696 2697 /** Offset 0x0667 - Skip CPU replacement check 2698 Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check 2699 $EN_DIS 2700 **/ 2701 UINT8 SkipCpuReplacementCheck; 2702 2703 /** Offset 0x0668 - Serial Io Uart Debug Mode 2704 Select SerialIo Uart Controller mode 2705 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 2706 4:SerialIoUartSkipInit 2707 **/ 2708 UINT8 SerialIoUartDebugMode; 2709 2710 /** Offset 0x0669 - Reserved 2711 **/ 2712 UINT8 Reserved36[19]; 2713 2714 /** Offset 0x067C - Avx2 Voltage Guardband Scaling Factor 2715 AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in 2716 1/100 units, where a value of 125 would apply a 1.25 scale factor. 2717 **/ 2718 UINT8 Avx2VoltageScaleFactor; 2719 2720 /** Offset 0x067D - Avx512 Voltage Guardband Scaling Factor 2721 AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 2722 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. 2723 **/ 2724 UINT8 Avx512VoltageScaleFactor; 2725 2726 /** Offset 0x067E - Reserved 2727 **/ 2728 UINT8 Reserved37; 2729 2730 /** Offset 0x067F - GPIO Override 2731 Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings 2732 before moved to FSP. Available configurations 0: Disable;1: Level 1 2733 **/ 2734 UINT8 GpioOverride; 2735 2736 /** Offset 0x0680 - Reserved 2737 **/ 2738 UINT8 Reserved38[16]; 2739 } FSP_M_CONFIG; 2740 2741 /** Fsp M UPD Configuration 2742 **/ 2743 typedef struct { 2744 2745 /** Offset 0x0000 2746 **/ 2747 FSP_UPD_HEADER FspUpdHeader; 2748 2749 /** Offset 0x0020 2750 **/ 2751 FSPM_ARCH_UPD FspmArchUpd; 2752 2753 /** Offset 0x0040 2754 **/ 2755 FSP_M_CONFIG FspmConfig; 2756 2757 /** Offset 0x0690 2758 **/ 2759 UINT8 UnusedUpdSpace22[6]; 2760 2761 /** Offset 0x0696 2762 **/ 2763 UINT16 UpdTerminator; 2764 } FSPM_UPD; 2765 2766 #pragma pack() 2767 2768 #endif 2769