1 /** 2 ****************************************************************************** 3 * @file shci.h 4 * @author MCD Application Team 5 * @brief HCI command for the system channel 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef __SHCI_H 23 #define __SHCI_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "mbox_def.h" /* Requested to expose the MB_WirelessFwInfoTable_t structure */ 31 32 /* Exported types ------------------------------------------------------------*/ 33 34 /* SYSTEM EVENT */ 35 typedef enum 36 { 37 WIRELESS_FW_RUNNING = 0x00, 38 RSS_FW_RUNNING = 0x01, 39 } SHCI_SysEvt_Ready_Rsp_t; 40 41 /* ERROR CODES 42 * 43 * These error codes are detected on M0 side and are send back to the M4 via a system 44 * notification message. It is up to the application running on M4 to manage these errors 45 * 46 * These errors can be generated by all layers (low level driver, stack, framework infrastructure, etc..) 47 */ 48 typedef enum 49 { 50 ERR_BLE_INIT = 0, 51 ERR_THREAD_LLD_FATAL_ERROR = 125, /* The LLD driver used on 802_15_4 detected a fatal error */ 52 ERR_THREAD_UNKNOWN_CMD = 126, /* The command send by the M4 to control the Thread stack is unknown */ 53 } SCHI_SystemErrCode_t; 54 55 #define SHCI_EVTCODE ( 0xFF ) 56 #define SHCI_SUB_EVT_CODE_BASE ( 0x9200 ) 57 58 /** 59 * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION 60 */ 61 typedef enum 62 { 63 SHCI_SUB_EVT_CODE_READY = SHCI_SUB_EVT_CODE_BASE, 64 SHCI_SUB_EVT_ERROR_NOTIF, 65 } SHCI_SUB_EVT_CODE_t; 66 67 typedef PACKED_STRUCT{ 68 SHCI_SysEvt_Ready_Rsp_t sysevt_ready_rsp; 69 } SHCI_C2_Ready_Evt_t; 70 71 typedef PACKED_STRUCT{ 72 SCHI_SystemErrCode_t errorCode; 73 } SHCI_C2_ErrorNotif_Evt_t; 74 75 /* SYSTEM COMMAND */ 76 typedef PACKED_STRUCT 77 { 78 uint32_t MetaData[3]; 79 } SHCI_Header_t; 80 81 typedef enum 82 { 83 SHCI_Success = 0x00, 84 SHCI_UNKNOWN_CMD = 0x01, 85 SHCI_ERR_UNSUPPORTED_FEATURE = 0x11, 86 SHCI_ERR_INVALID_HCI_CMD_PARAMS = 0x12, 87 SHCI_FUS_CMD_NOT_SUPPORTED = 0xFF, 88 } SHCI_CmdStatus_t; 89 90 typedef enum 91 { 92 SHCI_8BITS = 0x01, 93 SHCI_16BITS = 0x02, 94 SHCI_32BITS = 0x04, 95 } SHCI_Busw_t; 96 97 #define SHCI_OGF ( 0x3F ) 98 #define SHCI_OCF_BASE ( 0x50 ) 99 100 /** 101 * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION 102 */ 103 typedef enum 104 { 105 SHCI_OCF_C2_RESERVED1 = SHCI_OCF_BASE, 106 SHCI_OCF_C2_RESERVED2, 107 SHCI_OCF_C2_FUS_GET_STATE, 108 SHCI_OCF_C2_FUS_RESERVED1, 109 SHCI_OCF_C2_FUS_FW_UPGRADE, 110 SHCI_OCF_C2_FUS_FW_DELETE, 111 SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY, 112 SHCI_OCF_C2_FUS_LOCK_AUTH_KEY, 113 SHCI_OCF_C2_FUS_STORE_USR_KEY, 114 SHCI_OCF_C2_FUS_LOAD_USR_KEY, 115 SHCI_OCF_C2_FUS_START_WS, 116 SHCI_OCF_C2_FUS_RESERVED2, 117 SHCI_OCF_C2_FUS_RESERVED3, 118 SHCI_OCF_C2_FUS_LOCK_USR_KEY, 119 SHCI_OCF_C2_FUS_RESERVED5, 120 SHCI_OCF_C2_FUS_RESERVED6, 121 SHCI_OCF_C2_FUS_RESERVED7, 122 SHCI_OCF_C2_FUS_RESERVED8, 123 SHCI_OCF_C2_FUS_RESERVED9, 124 SHCI_OCF_C2_FUS_RESERVED10, 125 SHCI_OCF_C2_FUS_RESERVED11, 126 SHCI_OCF_C2_FUS_RESERVED12, 127 SHCI_OCF_C2_BLE_INIT, 128 SHCI_OCF_C2_THREAD_INIT, 129 SHCI_OCF_C2_DEBUG_INIT, 130 SHCI_OCF_C2_FLASH_ERASE_ACTIVITY, 131 SHCI_OCF_C2_CONCURRENT_SET_MODE, 132 SHCI_OCF_C2_FLASH_STORE_DATA, 133 SHCI_OCF_C2_FLASH_ERASE_DATA, 134 SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER, 135 SHCI_OCF_C2_MAC_802_15_4_INIT, 136 SHCI_OCF_C2_REINIT, 137 SHCI_OCF_C2_ZIGBEE_INIT, 138 SHCI_OCF_C2_LLD_TESTS_INIT 139 } SHCI_OCF_t; 140 141 #define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE) 142 /** No command parameters */ 143 /** Response parameters*/ 144 typedef enum 145 { 146 FUS_STATE_NO_ERROR = 0x00, 147 FUS_STATE_IMG_NOT_FOUND = 0x01, 148 FUS_STATE_IMG_CORRUPT = 0x02, 149 FUS_STATE_IMG_NOT_AUTHENTIC = 0x03, 150 FUS_STATE_IMG_NOT_ENOUGH_SPACE = 0x04, 151 FUS_STATE_ERR_UNKNOWN = 0xFF, 152 } SHCI_FUS_GetState_ErrorCode_t; 153 154 #define SHCI_OPCODE_C2_FUS_RESERVED1 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED1) 155 /** No command parameters */ 156 /** No response parameters*/ 157 158 #define SHCI_OPCODE_C2_FUS_FW_UPGRADE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_UPGRADE) 159 /** No structure for command parameters */ 160 /** No response parameters*/ 161 162 #define SHCI_OPCODE_C2_FUS_FW_DELETE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_DELETE) 163 /** No command parameters */ 164 /** No response parameters*/ 165 166 #define SHCI_OPCODE_C2_FUS_UPDATE_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY) 167 typedef PACKED_STRUCT{ 168 uint8_t KeySize; 169 uint8_t KeyData[64]; 170 } SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t; 171 172 /** No response parameters*/ 173 174 #define SHCI_OPCODE_C2_FUS_LOCK_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_AUTH_KEY) 175 /** No command parameters */ 176 /** No response parameters*/ 177 178 #define SHCI_OPCODE_C2_FUS_STORE_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_STORE_USR_KEY) 179 /** Command parameters */ 180 /* List of supported key type */ 181 enum 182 { 183 KEYTYPE_NONE = 0x00, 184 KEYTYPE_SIMPLE = 0x01, 185 KEYTYPE_MASTER = 0x02, 186 KEYTYPE_ENCRYPTED = 0x03, 187 }; 188 189 /* List of supported key size */ 190 enum 191 { 192 KEYSIZE_16 = 16, 193 KEYSIZE_32 = 32, 194 }; 195 196 typedef PACKED_STRUCT{ 197 uint8_t KeyType; 198 uint8_t KeySize; 199 uint8_t KeyData[32 + 12]; 200 } SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t; 201 202 /** Response parameters*/ 203 /** It responds a 1 byte value holding the index given for the stored key */ 204 205 #define SHCI_OPCODE_C2_FUS_LOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOAD_USR_KEY) 206 /** Command parameters */ 207 /** 1 byte holding the key index value */ 208 209 /** No response parameters*/ 210 211 #define SHCI_OPCODE_C2_FUS_START_WS (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_START_WS) 212 /** No command parameters */ 213 /** No response parameters*/ 214 215 #define SHCI_OPCODE_C2_FUS_RESERVED2 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED2) 216 /** No command parameters */ 217 /** No response parameters*/ 218 219 #define SHCI_OPCODE_C2_FUS_RESERVED3 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED3) 220 /** No command parameters */ 221 /** No response parameters*/ 222 223 #define SHCI_OPCODE_C2_FUS_LOCK_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_USR_KEY) 224 /** Command parameters */ 225 /** 1 byte holding the key index value */ 226 227 /** No response parameters*/ 228 229 #define SHCI_OPCODE_C2_FUS_RESERVED5 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED5) 230 /** No command parameters */ 231 /** No response parameters*/ 232 233 #define SHCI_OPCODE_C2_FUS_RESERVED6 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED6) 234 /** No command parameters */ 235 /** No response parameters*/ 236 237 #define SHCI_OPCODE_C2_FUS_RESERVED7 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED7) 238 /** No command parameters */ 239 /** No response parameters*/ 240 241 #define SHCI_OPCODE_C2_FUS_RESERVED8 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED8) 242 /** No command parameters */ 243 /** No response parameters*/ 244 245 #define SHCI_OPCODE_C2_FUS_RESERVED9 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED9) 246 /** No command parameters */ 247 /** No response parameters*/ 248 249 #define SHCI_OPCODE_C2_FUS_RESERVED10 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED10) 250 /** No command parameters */ 251 /** No response parameters*/ 252 253 #define SHCI_OPCODE_C2_FUS_RESERVED11 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED11) 254 /** No command parameters */ 255 /** No response parameters*/ 256 257 #define SHCI_OPCODE_C2_FUS_RESERVED12 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED12) 258 /** No command parameters */ 259 /** No response parameters*/ 260 261 #define SHCI_OPCODE_C2_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_INIT) 262 /** THE ORDER SHALL NOT BE CHANGED */ 263 typedef PACKED_STRUCT{ 264 uint8_t* pBleBufferAddress; /**< NOT USED CURRENTLY */ 265 uint32_t BleBufferSize; /**< Size of the Buffer allocated in pBleBufferAddress */ 266 uint16_t NumAttrRecord; 267 uint16_t NumAttrServ; 268 uint16_t AttrValueArrSize; 269 uint8_t NumOfLinks; 270 uint8_t ExtendedPacketLengthEnable; 271 uint8_t PrWriteListSize; 272 uint8_t MblockCount; 273 uint16_t AttMtu; 274 uint16_t SlaveSca; 275 uint8_t MasterSca; 276 uint8_t LsSource; 277 uint32_t MaxConnEventLength; 278 uint16_t HsStartupTime; 279 uint8_t ViterbiEnable; 280 uint8_t LlOnly; 281 uint8_t HwVersion; 282 } SHCI_C2_Ble_Init_Cmd_Param_t; 283 284 typedef PACKED_STRUCT{ 285 SHCI_Header_t Header; /** Does not need to be initialized by the user */ 286 SHCI_C2_Ble_Init_Cmd_Param_t Param; 287 } SHCI_C2_Ble_Init_Cmd_Packet_t; 288 289 /** No response parameters*/ 290 291 #define SHCI_OPCODE_C2_THREAD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT) 292 /** No command parameters */ 293 /** No response parameters*/ 294 295 #define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT) 296 /** Command parameters */ 297 typedef PACKED_STRUCT{ 298 uint8_t *pGpioConfig; 299 uint8_t *pTracesConfig; 300 uint8_t *pGeneralConfig; 301 uint8_t GpioConfigSize; 302 uint8_t TracesConfigSize; 303 uint8_t GeneralConfigSize; 304 } SHCI_C2_DEBUG_init_Cmd_Param_t; 305 306 typedef PACKED_STRUCT{ 307 SHCI_Header_t Header; /** Does not need to be initialized by the user */ 308 SHCI_C2_DEBUG_init_Cmd_Param_t Param; 309 } SHCI_C2_DEBUG_Init_Cmd_Packet_t; 310 /** No response parameters*/ 311 312 #define SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_ACTIVITY) 313 /** Command parameters */ 314 typedef enum 315 { 316 ERASE_ACTIVITY_OFF = 0x00, 317 ERASE_ACTIVITY_ON = 0x01, 318 } SHCI_EraseActivity_t; 319 320 /** No response parameters*/ 321 322 #define SHCI_OPCODE_C2_CONCURRENT_SET_MODE (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_SET_MODE) 323 /** command parameters */ 324 typedef enum 325 { 326 BLE_ENABLE, 327 THREAD_ENABLE, 328 } SHCI_C2_CONCURRENT_Mode_Param_t; 329 /** No response parameters*/ 330 331 #define SHCI_OPCODE_C2_FLASH_STORE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_STORE_DATA) 332 #define SHCI_OPCODE_C2_FLASH_ERASE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_DATA) 333 /** command parameters */ 334 typedef enum 335 { 336 BLE_IP, 337 THREAD_IP, 338 } SHCI_C2_FLASH_Ip_t; 339 /** No response parameters*/ 340 341 #define SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER (( SHCI_OGF << 10) + SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER) 342 343 #define SHCI_OPCODE_C2_MAC_802_15_4_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_MAC_802_15_4_INIT) 344 345 #define SHCI_OPCODE_C2_REINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_REINIT) 346 347 #define SHCI_OPCODE_C2_ZIGBEE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_ZIGBEE_INIT) 348 349 #define SHCI_OPCODE_C2_LLD_TESTS_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_TESTS_INIT) 350 351 /* Exported type --------------------------------------------------------*/ 352 353 typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t; 354 355 /* 356 * At startup, the informations relative to the wireless binary are stored in RAM trough a structure defined by 357 * SHCI_WirelessFwInfoTable_t.This structure contains 4 fields (Version,MemorySize, Stack_info and a reserved part) 358 * each of those coded on 32 bits as shown on the table below: 359 * 360 * 361 * |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 | 362 * ------------------------------------------------------------------------------------------------- 363 * Version | Major version | Minor version | Sub version | Branch |Releas Type| 364 * ------------------------------------------------------------------------------------------------- 365 * MemorySize | SRAM2B (kB) | SRAM2A (kB) | SRAM1 (kB) | FLASH (4kb) | 366 * ------------------------------------------------------------------------------------------------- 367 * Info stack | Reserved | Reserved | Reserved | Type (MAC,Thread,BLE) | 368 * ------------------------------------------------------------------------------------------------- 369 * Reserved | Reserved | Reserved | Reserved | Reserved | 370 * ------------------------------------------------------------------------------------------------- 371 * 372 */ 373 374 /* Field Version */ 375 #define INFO_VERSION_MAJOR_OFFSET 24 376 #define INFO_VERSION_MAJOR_MASK 0xff000000 377 #define INFO_VERSION_MINOR_OFFSET 16 378 #define INFO_VERSION_MINOR_MASK 0x00ff0000 379 #define INFO_VERSION_SUB_OFFSET 8 380 #define INFO_VERSION_SUB_MASK 0x0000ff00 381 #define INFO_VERSION_BRANCH_OFFSET 4 382 #define INFO_VERSION_BRANCH_MASK 0x0000000f0 383 #define INFO_VERSION_TYPE_OFFSET 0 384 #define INFO_VERSION_TYPE_MASK 0x00000000f 385 386 #define INFO_VERSION_TYPE_RELEASE 1 387 388 /* Field Memory */ 389 #define INFO_SIZE_SRAM2B_OFFSET 24 390 #define INFO_SIZE_SRAM2B_MASK 0xff000000 391 #define INFO_SIZE_SRAM2A_OFFSET 16 392 #define INFO_SIZE_SRAM2A_MASK 0x00ff0000 393 #define INFO_SIZE_SRAM1_OFFSET 8 394 #define INFO_SIZE_SRAM1_MASK 0x0000ff00 395 #define INFO_SIZE_FLASH_OFFSET 0 396 #define INFO_SIZE_FLASH_MASK 0x000000ff 397 398 /* Field stack information */ 399 #define INFO_STACK_TYPE_OFFSET 0 400 #define INFO_STACK_TYPE_MASK 0x000000ff 401 #define INFO_STACK_TYPE_NONE 0 402 403 #define INFO_STACK_TYPE_BLE_STANDARD 0x1 404 #define INFO_STACK_TYPE_BLE_HCI 0x2 405 #define INFO_STACK_TYPE_THREAD_FTD 0x10 406 #define INFO_STACK_TYPE_THREAD_MTD 0x11 407 #define INFO_STACK_TYPE_ZIGBEE 0x30 408 #define INFO_STACK_TYPE_MAC 0x40 409 #define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC 0x50 410 #define INFO_STACK_TYPE_802154_LLD_TESTS 0x60 411 412 typedef struct { 413 /** 414 * Wireless Info 415 */ 416 uint8_t VersionMajor; 417 uint8_t VersionMinor; 418 uint8_t VersionSub; 419 uint8_t VersionBranch; 420 uint8_t VersionReleaseType; 421 uint8_t MemorySizeSram2B; /*< Multiple of 1K */ 422 uint8_t MemorySizeSram2A; /*< Multiple of 1K */ 423 uint8_t MemorySizeSram1; /*< Multiple of 1K */ 424 uint8_t MemorySizeFlash; /*< Multiple of 4K */ 425 uint8_t StackType; 426 /** 427 * Fus Info 428 */ 429 uint8_t FusVersionMajor; 430 uint8_t FusVersionMinor; 431 uint8_t FusVersionSub; 432 uint8_t FusMemorySizeSram2B; /*< Multiple of 1K */ 433 uint8_t FusMemorySizeSram2A; /*< Multiple of 1K */ 434 uint8_t FusMemorySizeFlash; /*< Multiple of 4K */ 435 }WirelessFwInfo_t; 436 437 438 /* Exported functions ------------------------------------------------------- */ 439 440 /** 441 * For all SHCI_C2_FUS_xxx() command: 442 * When the wireless FW is running on the CPU2, the command returns SHCI_FUS_CMD_NOT_SUPPORTED 443 * When any FUS command is sent after the SHCI_FUS_CMD_NOT_SUPPORTED has been received, 444 * the CPU2 switches on the RSS ( This reboots automatically the device ) 445 */ 446 /** 447 * SHCI_C2_FUS_GetState 448 * @brief Read the FUS State 449 * If the user is not interested by the Error code response, a null value may 450 * be passed as parameter 451 * 452 * @param p_rsp : return the error code when the FUS State Value = 0xFF 453 * @retval FUS State Values 454 */ 455 uint8_t SHCI_C2_FUS_GetState( SHCI_FUS_GetState_ErrorCode_t *p_rsp ); 456 457 /** 458 * SHCI_C2_FUS_FwUpgrade 459 * @brief Request the FUS to install the CPU2 firmware update 460 * 461 * @param fw_src_add: Address of the firmware image location 462 * @param fw_dest_add: Address of the firmware destination 463 * @retval Status 464 */ 465 SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade( uint32_t fw_src_add, uint32_t fw_dest_add ); 466 467 /** 468 * SHCI_C2_FUS_FwDelete 469 * @brief Delete the wireless stack on CPU2 470 * 471 * @param None 472 * @retval Status 473 */ 474 SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete( void ); 475 476 /** 477 * SHCI_C2_FUS_UpdateAuthKey 478 * @brief Request the FUS to update the authentication key 479 * 480 * @param pCmdPacket 481 * @retval Status 482 */ 483 SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey( SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *pParam ); 484 485 /** 486 * SHCI_C2_FUS_LockAuthKey 487 * @brief Request the FUS to prevent any future update of the authentication key 488 * 489 * @param None 490 * @retval Status 491 */ 492 SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey( void ); 493 494 /** 495 * SHCI_C2_FUS_StoreUsrKey 496 * @brief Request the FUS to store the user key 497 * 498 * @param pParam : command parameter 499 * @param p_key_index : Index allocated by the FUS to the stored key 500 * 501 * @retval Status 502 */ 503 SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey( SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *pParam, uint8_t *p_key_index ); 504 505 /** 506 * SHCI_C2_FUS_LoadUsrKey 507 * @brief Request the FUS to load the user key into the AES 508 * 509 * @param key_index : index of the user key to load in AES1 510 * @retval Status 511 */ 512 SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey( uint8_t key_index ); 513 514 /** 515 * SHCI_C2_FUS_StartWs 516 * @brief Request the FUS to reboot on the wireless stack 517 * 518 * @param None 519 * @retval Status 520 */ 521 SHCI_CmdStatus_t SHCI_C2_FUS_StartWs( void ); 522 523 /** 524 * SHCI_C2_FUS_LockUsrKey 525 * @brief Request the FUS to lock the user key so that it cannot be updated later on 526 * 527 * @param key_index : index of the user key to lock 528 * @retval Status 529 */ 530 SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey( uint8_t key_index ); 531 532 /** 533 * SHCI_C2_BLE_Init 534 * @brief Provides parameters and starts the BLE Stack 535 * 536 * @param pCmdPacket : Parameters to be provided to the BLE Stack 537 * @retval Status 538 */ 539 SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket ); 540 541 /** 542 * SHCI_C2_THREAD_Init 543 * @brief Starts the THREAD Stack 544 * 545 * @param None 546 * @retval Status 547 */ 548 SHCI_CmdStatus_t SHCI_C2_THREAD_Init( void ); 549 550 /** 551 * SHCI_C2_LLDTESTS_Init 552 * @brief Starts the LLD tests CLI 553 * 554 * @param param_size : Nb of bytes 555 * @param p_param : pointeur with data to give from M4 to M0 556 * @retval Status 557 */ 558 SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param ); 559 560 /** 561 * SHCI_C2_ZIGBEE_Init 562 * @brief Starts the Zigbee Stack 563 * 564 * @param None 565 * @retval Status 566 */ 567 SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init( void ); 568 569 /** 570 * SHCI_C2_DEBUG_Init 571 * @brief Starts the Traces 572 * 573 * @param None 574 * @retval Status 575 */ 576 SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket ); 577 578 /** 579 * SHCI_C2_FLASH_EraseActivity 580 * @brief Provides the information of the start and the end of a flash erase window on the CPU1 581 * 582 * @param erase_activity: Start/End of erase activity 583 * @retval Status 584 */ 585 SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity( SHCI_EraseActivity_t erase_activity ); 586 587 /** 588 * SHCI_C2_CONCURRENT_SetMode 589 * @brief Enable/Disable Thread on CPU2 (M0+) 590 * 591 * @param Mode: BLE or Thread enable flag 592 * @retval Status 593 */ 594 SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mode ); 595 596 /** 597 * SHCI_C2_FLASH_StoreData 598 * @brief Store Data in Flash 599 * 600 * @param Ip: BLE or THREAD 601 * @retval Status 602 */ 603 SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData( SHCI_C2_FLASH_Ip_t Ip ); 604 605 /** 606 * SHCI_C2_FLASH_EraseData 607 * @brief Erase Data in Flash 608 * 609 * @param Ip: BLE or THREAD 610 * @retval Status 611 */ 612 SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData( SHCI_C2_FLASH_Ip_t Ip ); 613 614 /** 615 * SHCI_C2_RADIO_AllowLowPower 616 * @brief Allow or forbid IP_radio (802_15_4 or BLE) to enter in low power mode. 617 * 618 * @param Ip: BLE or 802_15_5 619 * @param FlagRadioLowPowerOn: True or false 620 * @retval Status 621 */ 622 SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower( SHCI_C2_FLASH_Ip_t Ip,uint8_t FlagRadioLowPowerOn); 623 624 625 /** 626 * SHCI_C2_MAC_802_15_4_Init 627 * @brief Starts the MAC 802.15.4 on M0 628 * 629 * @param None 630 * @retval Status 631 */ 632 SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init( void ); 633 634 /** 635 * SHCI_GetWirelessFwInfo 636 * @brief This function read back the informations relative to the wireless binary loaded. 637 * Refer yourself to SHCI_WirelessFwInfoTable_t structure to get the significance 638 * of the different parameters returned. 639 * @param pWirelessInfo : Pointer to WirelessFwInfo_t. 640 * 641 * @retval SHCI_Success 642 */ 643 SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo ); 644 645 /** 646 * SHCI_C2_Reinit 647 * @brief This is required to allow the CPU1 to fake a set C2BOOT when it has already been set. 648 * In order to fake a C2BOOT, the CPU1 shall : 649 * - Send SHCI_C2_Reinit() 650 * - call SEV instruction 651 * WARNING: 652 * This function is intended to be used by the SBSFU 653 * 654 * @param None 655 * @retval Status 656 */ 657 SHCI_CmdStatus_t SHCI_C2_Reinit( void ); 658 659 #ifdef __cplusplus 660 } 661 #endif 662 663 #endif /*__SHCI_H */ 664 665 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 666