1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_LL_FMC_H 22 #define STM32L4xx_LL_FMC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FMC_LL 36 * @{ 37 */ 38 39 /** @addtogroup FMC_LL_Private_Macros 40 * @{ 41 */ 42 #if defined FMC_BANK1 43 44 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 46 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 47 ((__BANK__) == FMC_NORSRAM_BANK4)) 48 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 49 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 50 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 51 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 52 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 53 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 55 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 56 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 59 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 60 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 61 #if defined(FMC_BCR1_WFDIS) 62 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 63 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 64 #endif /* FMC_BCR1_WFDIS */ 65 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 66 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 67 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 68 ((__MODE__) == FMC_ACCESS_MODE_D)) 69 #if defined(FMC_BCRx_NBLSET) 70 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 71 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 72 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 73 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 74 #endif /* FMC_BCRx_NBLSET */ 75 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 76 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 77 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 78 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 79 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 80 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 81 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 82 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 83 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 84 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 85 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 86 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 87 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 88 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 89 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 90 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 91 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 92 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 93 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 94 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 95 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 96 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 97 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 98 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 99 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 100 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 101 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 102 #if defined(FMC_PCSCNTR_CSCOUNT) 103 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 104 #endif /* FMC_PCSCNTR_CSCOUNT */ 105 106 #endif /* FMC_BANK1 */ 107 #if defined(FMC_BANK3) 108 109 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 110 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 111 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 112 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 113 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 114 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 115 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 116 117 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 118 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 119 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 120 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 121 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 122 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 123 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 124 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 125 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 126 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 127 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 128 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 129 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 130 131 #endif /* FMC_BANK3 */ 132 133 /** 134 * @} 135 */ 136 137 /* Exported typedef ----------------------------------------------------------*/ 138 139 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 140 * @{ 141 */ 142 143 #if defined FMC_BANK1 144 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 145 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 146 #endif /* FMC_BANK1 */ 147 #if defined(FMC_BANK3) 148 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 149 #endif /* FMC_BANK3 */ 150 151 #if defined FMC_BANK1 152 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 153 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 154 #endif /* FMC_BANK1 */ 155 #if defined(FMC_BANK3) 156 #define FMC_NAND_DEVICE FMC_Bank3_R 157 #endif /* FMC_BANK3 */ 158 159 #if defined FMC_BANK1 160 /** 161 * @brief FMC NORSRAM Configuration Structure definition 162 */ 163 typedef struct 164 { 165 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 166 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 167 168 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 169 multiplexed on the data bus or not. 170 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 171 172 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 173 the corresponding memory device. 174 This parameter can be a value of @ref FMC_Memory_Type */ 175 176 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 177 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 178 179 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 180 valid only with synchronous burst Flash memories. 181 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 182 183 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 184 the Flash memory in burst mode. 185 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 186 187 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 188 clock cycle before the wait state or during the wait state, 189 valid only when accessing memories in burst mode. 190 This parameter can be a value of @ref FMC_Wait_Timing */ 191 192 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 193 This parameter can be a value of @ref FMC_Write_Operation */ 194 195 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 196 signal, valid for Flash memory access in burst mode. 197 This parameter can be a value of @ref FMC_Wait_Signal */ 198 199 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 200 This parameter can be a value of @ref FMC_Extended_Mode */ 201 202 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 203 valid only with asynchronous Flash memories. 204 This parameter can be a value of @ref FMC_AsynchronousWait */ 205 206 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 207 This parameter can be a value of @ref FMC_Write_Burst */ 208 209 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 210 This parameter is only enabled through the FMC_BCR1 register, and don't care 211 through FMC_BCR2..4 registers. 212 This parameter can be a value of @ref FMC_Continous_Clock */ 213 214 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 215 This parameter is only enabled through the FMC_BCR1 register, and don't care 216 through FMC_BCR2..4 registers. 217 This parameter can be a value of @ref FMC_Write_FIFO */ 218 219 uint32_t PageSize; /*!< Specifies the memory page size. 220 This parameter can be a value of @ref FMC_Page_Size */ 221 222 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 223 This parameter can be a value of @ref FMC_Byte_Lane */ 224 #if defined(FMC_PCSCNTR_CSCOUNT) 225 226 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank 227 for PSRAM refresh. 228 This parameter can be set to ENABLE or DISABLE */ 229 230 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous 231 accesses and in HCLK cycles for asynchronous accesses, 232 valid only if MaxChipSelectPulse is ENABLE. 233 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 234 @note: This parameter is common to all NSBank. */ 235 #endif 236 }FMC_NORSRAM_InitTypeDef; 237 238 /** 239 * @brief FMC NORSRAM Timing parameters structure definition 240 */ 241 typedef struct 242 { 243 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 244 the duration of the address setup time. 245 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 246 @note This parameter is not used with synchronous NOR Flash memories. */ 247 248 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 249 the duration of the address hold time. 250 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 251 @note This parameter is not used with synchronous NOR Flash memories. */ 252 253 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 254 the duration of the data setup time. 255 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 256 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 257 NOR Flash memories. */ 258 259 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 260 the duration of the data hold time. 261 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 262 @note This parameter is used for used in asynchronous accesses. */ 263 264 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 265 the duration of the bus turnaround. 266 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 267 @note This parameter is only used for multiplexed NOR Flash memories. */ 268 269 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 270 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. 271 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 272 accesses. */ 273 274 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 275 to the memory before getting the first data. 276 The parameter value depends on the memory type as shown below: 277 - It must be set to 0 in case of a CRAM 278 - It is don't care in asynchronous NOR, SRAM or ROM accesses 279 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories 280 with synchronous burst mode enable */ 281 282 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 283 This parameter can be a value of @ref FMC_Access_Mode */ 284 }FMC_NORSRAM_TimingTypeDef; 285 #endif /* FMC_BANK1 */ 286 287 #if defined(FMC_BANK3) 288 /** 289 * @brief FMC NAND Configuration Structure definition 290 */ 291 typedef struct 292 { 293 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 294 This parameter can be a value of @ref FMC_NAND_Bank */ 295 296 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 297 This parameter can be any value of @ref FMC_Wait_feature */ 298 299 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 300 This parameter can be any value of @ref FMC_NAND_Data_Width */ 301 302 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 303 This parameter can be any value of @ref FMC_ECC */ 304 305 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 306 This parameter can be any value of @ref FMC_ECC_Page_Size */ 307 308 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 309 delay between CLE low and RE low. 310 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 311 312 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 313 delay between ALE low and RE low. 314 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 315 }FMC_NAND_InitTypeDef; 316 #endif 317 318 #if defined(FMC_BANK3) 319 /** 320 * @brief FMC NAND Timing parameters structure definition 321 */ 322 typedef struct 323 { 324 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 325 the command assertion for NAND-Flash read or write access 326 to common/Attribute or I/O memory space (depending on 327 the memory space timing to be configured). 328 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 329 330 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 331 command for NAND-Flash read or write access to 332 common/Attribute or I/O memory space (depending on the 333 memory space timing to be configured). 334 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 335 336 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 337 (and data for write access) after the command de-assertion 338 for NAND-Flash read or write access to common/Attribute 339 or I/O memory space (depending on the memory space timing 340 to be configured). 341 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 342 343 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 344 data bus is kept in HiZ after the start of a NAND-Flash 345 write access to common/Attribute or I/O memory space (depending 346 on the memory space timing to be configured). 347 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 348 }FMC_NAND_PCC_TimingTypeDef; 349 #endif /* FMC_BANK3 */ 350 351 352 /** 353 * @} 354 */ 355 356 /* Exported constants --------------------------------------------------------*/ 357 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 358 * @{ 359 */ 360 #if defined FMC_BANK1 361 362 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 363 * @{ 364 */ 365 366 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 367 * @{ 368 */ 369 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) 370 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) 371 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) 372 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) 373 /** 374 * @} 375 */ 376 377 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 378 * @{ 379 */ 380 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) 381 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) 382 /** 383 * @} 384 */ 385 386 /** @defgroup FMC_Memory_Type FMC Memory Type 387 * @{ 388 */ 389 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) 390 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) 391 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) 392 /** 393 * @} 394 */ 395 396 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 397 * @{ 398 */ 399 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 400 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) 401 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) 402 /** 403 * @} 404 */ 405 406 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 407 * @{ 408 */ 409 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) 410 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) 411 /** 412 * @} 413 */ 414 415 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 416 * @{ 417 */ 418 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) 419 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) 420 /** 421 * @} 422 */ 423 424 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 425 * @{ 426 */ 427 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) 428 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) 429 /** 430 * @} 431 */ 432 433 /** @defgroup FMC_Wait_Timing FMC Wait Timing 434 * @{ 435 */ 436 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) 437 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) 438 /** 439 * @} 440 */ 441 442 /** @defgroup FMC_Write_Operation FMC Write Operation 443 * @{ 444 */ 445 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) 446 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) 447 /** 448 * @} 449 */ 450 451 /** @defgroup FMC_Wait_Signal FMC Wait Signal 452 * @{ 453 */ 454 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) 455 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) 456 /** 457 * @} 458 */ 459 460 /** @defgroup FMC_Extended_Mode FMC Extended Mode 461 * @{ 462 */ 463 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) 464 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) 465 /** 466 * @} 467 */ 468 469 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 470 * @{ 471 */ 472 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) 473 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) 474 /** 475 * @} 476 */ 477 478 /** @defgroup FMC_Page_Size FMC Page Size 479 * @{ 480 */ 481 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) 482 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) 483 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) 484 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) 485 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) 486 /** 487 * @} 488 */ 489 490 /** @defgroup FMC_Write_Burst FMC Write Burst 491 * @{ 492 */ 493 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) 494 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) 495 /** 496 * @} 497 */ 498 499 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 500 * @{ 501 */ 502 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) 503 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) 504 /** 505 * @} 506 */ 507 508 /** @defgroup FMC_Write_FIFO FMC Write FIFO 509 * @{ 510 */ 511 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) 512 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) 513 /** 514 * @} 515 */ 516 517 /** @defgroup FMC_Access_Mode FMC Access Mode 518 * @{ 519 */ 520 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) 521 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) 522 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) 523 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U) 524 /** 525 * @} 526 */ 527 528 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 529 * @{ 530 */ 531 #define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U) 532 #define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000U) 533 #define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000U) 534 #define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000U) 535 /** 536 * @} 537 */ 538 539 /** 540 * @} 541 */ 542 #endif /* FMC_BANK1 */ 543 544 #if defined(FMC_BANK3) 545 546 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 547 * @{ 548 */ 549 /** @defgroup FMC_NAND_Bank FMC NAND Bank 550 * @{ 551 */ 552 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U) 553 /** 554 * @} 555 */ 556 557 /** @defgroup FMC_Wait_feature FMC Wait feature 558 * @{ 559 */ 560 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) 561 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) 562 /** 563 * @} 564 */ 565 566 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 567 * @{ 568 */ 569 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) 570 /** 571 * @} 572 */ 573 574 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 575 * @{ 576 */ 577 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 578 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) 579 /** 580 * @} 581 */ 582 583 /** @defgroup FMC_ECC FMC ECC 584 * @{ 585 */ 586 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) 587 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) 588 /** 589 * @} 590 */ 591 592 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 593 * @{ 594 */ 595 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) 596 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) 597 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) 598 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) 599 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) 600 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) 601 /** 602 * @} 603 */ 604 605 /** 606 * @} 607 */ 608 #endif /* FMC_BANK3 */ 609 610 611 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 612 * @{ 613 */ 614 #if defined(FMC_BANK3) 615 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U) 616 #define FMC_IT_LEVEL ((uint32_t)0x00000010U) 617 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) 618 #endif /* FMC_BANK3 */ 619 /** 620 * @} 621 */ 622 623 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 624 * @{ 625 */ 626 #if defined(FMC_BANK3) 627 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) 628 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002U) 629 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) 630 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040U) 631 #endif /* FMC_BANK3 */ 632 /** 633 * @} 634 */ 635 636 /** 637 * @} 638 */ 639 640 /** 641 * @} 642 */ 643 644 /* Private macro -------------------------------------------------------------*/ 645 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 646 * @{ 647 */ 648 #if defined FMC_BANK1 649 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 650 * @brief macros to handle NOR device enable/disable and read/write operations 651 * @{ 652 */ 653 654 /** 655 * @brief Enable the NORSRAM device access. 656 * @param __INSTANCE__ FMC_NORSRAM Instance 657 * @param __BANK__ FMC_NORSRAM Bank 658 * @retval None 659 */ 660 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN) 661 662 /** 663 * @brief Disable the NORSRAM device access. 664 * @param __INSTANCE__ FMC_NORSRAM Instance 665 * @param __BANK__ FMC_NORSRAM Bank 666 * @retval None 667 */ 668 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN) 669 670 /** 671 * @} 672 */ 673 #endif /* FMC_BANK1 */ 674 675 #if defined(FMC_BANK3) 676 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 677 * @brief macros to handle NAND device enable/disable 678 * @{ 679 */ 680 681 /** 682 * @brief Enable the NAND device access. 683 * @param __INSTANCE__ FMC_NAND Instance 684 * @retval None 685 */ 686 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 687 688 /** 689 * @brief Disable the NAND device access. 690 * @param __INSTANCE__ FMC_NAND Instance 691 * @param __BANK__ FMC_NAND Bank 692 * @retval None 693 */ 694 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 695 696 /** 697 * @} 698 */ 699 #endif 700 701 #if defined(FMC_BANK3) 702 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 703 * @brief macros to handle NAND interrupts 704 * @{ 705 */ 706 707 /** 708 * @brief Enable the NAND device interrupt. 709 * @param __INSTANCE__ FMC_NAND instance 710 * @param __INTERRUPT__ FMC_NAND interrupt 711 * This parameter can be any combination of the following values: 712 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 713 * @arg FMC_IT_LEVEL: Interrupt level. 714 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 715 * @retval None 716 */ 717 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 718 719 /** 720 * @brief Disable the NAND device interrupt. 721 * @param __INSTANCE__ FMC_NAND Instance 722 * @param __INTERRUPT__ FMC_NAND interrupt 723 * This parameter can be any combination of the following values: 724 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 725 * @arg FMC_IT_LEVEL: Interrupt level. 726 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 727 * @retval None 728 */ 729 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 730 731 /** 732 * @brief Get flag status of the NAND device. 733 * @param __INSTANCE__ FMC_NAND Instance 734 * @param __BANK__ FMC_NAND Bank 735 * @param __FLAG__ FMC_NAND flag 736 * This parameter can be any combination of the following values: 737 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 738 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 739 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 740 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 741 * @retval The state of FLAG (SET or RESET). 742 */ 743 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 744 745 /** 746 * @brief Clear flag status of the NAND device. 747 * @param __INSTANCE__ FMC_NAND Instance 748 * @param __FLAG__ FMC_NAND flag 749 * This parameter can be any combination of the following values: 750 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 751 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 752 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 753 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 754 * @retval None 755 */ 756 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 757 758 /** 759 * @} 760 */ 761 #endif /* FMC_BANK3 */ 762 763 764 /** 765 * @} 766 */ 767 768 /** 769 * @} 770 */ 771 772 /* Private functions ---------------------------------------------------------*/ 773 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 774 * @{ 775 */ 776 777 #if defined FMC_BANK1 778 /** @defgroup FMC_LL_NORSRAM NOR SRAM 779 * @{ 780 */ 781 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 782 * @{ 783 */ 784 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); 785 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 786 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); 787 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 788 /** 789 * @} 790 */ 791 792 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 793 * @{ 794 */ 795 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 796 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 797 /** 798 * @} 799 */ 800 /** 801 * @} 802 */ 803 #endif /* FMC_BANK1 */ 804 805 #if defined(FMC_BANK3) 806 /** @defgroup FMC_LL_NAND NAND 807 * @{ 808 */ 809 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 810 * @{ 811 */ 812 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 813 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 814 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 815 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 816 /** 817 * @} 818 */ 819 820 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 821 * @{ 822 */ 823 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 824 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 825 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); 826 /** 827 * @} 828 */ 829 /** 830 * @} 831 */ 832 #endif /* FMC_BANK3 */ 833 834 835 836 /** 837 * @} 838 */ 839 840 /** 841 * @} 842 */ 843 844 /** 845 * @} 846 */ 847 848 #ifdef __cplusplus 849 } 850 #endif 851 852 #endif /* STM32L4xx_LL_FMC_H */ 853 854 /************************ (C) COPYRIGHT STMicroelectronics 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