| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 259 Register MaskReg, Register ScratchReg) { in insertMaskedMerge()
287 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
427 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
525 Register MaskReg, in tryToFoldBNEOnCmpXchgResult()
583 Register MaskReg = IsMasked ? MI.getOperand(5).getReg() : Register(); in expandAtomicCmpXchg() local
631 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 227 Register MaskReg, Register ScratchReg) { in insertMaskedMerge()
253 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
401 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
562 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandPseudoInsts.cpp | 276 Register MaskReg, Register ScratchReg) { in insertMaskedMerge()
304 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
444 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
585 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask()
|
| /aosp_15_r20/external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 93 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 221 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
|
| H A D | LegalizerHelper.cpp | 7476 Register MaskReg = MI.getOperand(1).getReg(); in lowerSelect() local
|
| /aosp_15_r20/external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8545 unsigned MaskReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
9263 unsigned MaskReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4171 Register MaskReg = MIB->getOperand(1).getReg(); in expandPostRAPseudo() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1299 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 5018 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2789 Register MaskReg = I.getOperand(2).getReg(); in selectG_PTRMASK() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3096 Register MaskReg = I.getOperand(2).getReg(); in select() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 10787 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
11601 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11774 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
12769 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
|