1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef _SOC_MSR_H_ 4 #define _SOC_MSR_H_ 5 6 #include <intelblocks/msr.h> 7 8 #define MSR_FEATURE_CONFIG 0x13c 9 #define FEATURE_CONFIG_LOCK BIT(0) 10 11 #define IA32_MCG_CAP 0x179 12 #define IA32_MCG_CAP_COUNT_MASK 0xff 13 #define IA32_MCG_CAP_CTL_P_BIT 8 14 #define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) 15 16 #define IA32_MCG_CTL 0x17b /* IA32_MCG_CAP[MCG_CTL_P] == 1 */ 17 18 /* IA32_MISC_ENABLE bits */ 19 #define FAST_STRINGS_ENABLE_BIT (1 << 0) 20 #define SPEED_STEP_ENABLE_BIT (1 << 16) 21 #define MONIOR_ENABLE_BIT (1 << 18) 22 23 #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0 24 25 /* MSR_PKG_CST_CONFIG_CONTROL bits */ 26 #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 27 #define PKG_CSTATE_LIMIT_SHIFT 0 /* 0:3 */ 28 /* No package C-state limit. All C-States supported by the processor are available. */ 29 #define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT) 30 #define CFG_LOCK_SHIFT 15 31 #define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT) 32 33 /* MSR_POWER_CTL bits */ 34 #define MSR_POWER_CTL 0x1fc 35 #define BIDIR_PROCHOT_ENABLE_SHIFT 0 36 #define BIDIR_PROCHOT_ENABLE (1 << BIDIR_PROCHOT_ENABLE_SHIFT) 37 #define C1E_ENABLE_SHIFT 1 38 #define C1E_ENABLE (1 << C1E_ENABLE_SHIFT) 39 40 /* MSR_IA32_PERF_CTRL (0x199) bits */ 41 #define MSR_IA32_PERF_CTRL 0x199 42 #define PSTATE_REQ_SHIFT 8 /* 8:14 bits */ 43 #define PSTATE_REQ_MASK (0x7f << PSTATE_REQ_SHIFT) 44 #define PSTATE_REQ_RATIO (0xa << PSTATE_REQ_SHIFT) 45 46 /* MSR_MISC_PWR_MGMT bits */ 47 #define MSR_MISC_PWR_MGMT 0x1aa 48 #define HWP_ENUM_SHIFT 6 49 #define HWP_ENUM_ENABLE (1 << HWP_ENUM_SHIFT) 50 #define HWP_EPP_SHIFT 12 51 #define HWP_EPP_ENUM_ENABLE (1 << HWP_EPP_SHIFT) 52 #define LOCK_MISC_PWR_MGMT_MSR_SHIFT 13 53 #define LOCK_MISC_PWR_MGMT_MSR (1 << LOCK_MISC_PWR_MGMT_MSR_SHIFT) 54 #define LOCK_THERM_INT_SHIFT 22 55 #define LOCK_THERM_INT (1 << LOCK_THERM_INT_SHIFT) 56 57 /* MSR_TURBO_RATIO_LIMIT bits */ 58 #define MSR_TURBO_RATIO_LIMIT 0x1ad 59 60 /* MSR_TURBO_RATIO_LIMIT_CORES (0x1ae) */ 61 #define MSR_TURBO_RATIO_LIMIT_CORES 0x1ae 62 63 /* MSR_VR_CURRENT_CONFIG bits */ 64 #define MSR_VR_CURRENT_CONFIG 0x601 65 #define CURRENT_LIMIT_LOCK_SHIFT 31 66 #define CURRENT_LIMIT_LOCK (0x1 << CURRENT_LIMIT_LOCK_SHIFT) 67 68 #define MSR_VR_MISC_CONFIG 0x603 69 70 /* MSR_TURBO_ACTIVATION_RATIO bits */ 71 #define MSR_TURBO_ACTIVATION_RATIO 0x64c 72 #define MAX_NON_TURBO_RATIO_SHIFT 0 73 #define MAX_NON_TURBO_RATIO (0xff << MAX_NON_TURBO_RATIO_SHIFT) 74 75 #define IA32_PM_ENABLE 0x770 76 #define IA32_HWP_CAPABILITIES 0x771 77 78 /* MSR_ENERGY_PERF_BIAS_CONFIG bits */ 79 #define MSR_ENERGY_PERF_BIAS_CONFIG 0xa01 80 #define EPB_ENERGY_POLICY_SHIFT 3 81 #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) 82 83 /* MSR Protected Processor Inventory Number */ 84 #define MSR_PPIN_CTL 0x04e 85 #define MSR_PPIN_CTL_LOCK 0x1 86 #define MSR_PPIN_CTL_ENABLE_SHIFT 1 87 #define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT) 88 #define MSR_PPIN 0x04f 89 #define MSR_PPIN_CAP_SHIFT 23 90 #define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) 91 92 /* SOC-specific #defines may use the above definitions */ 93 #include <soc/soc_msr.h> 94 95 #endif /* _SOC_MSR_H_ */ 96