1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_INTEL_COMMON_MSR_H 4 #define SOC_INTEL_COMMON_MSR_H 5 6 #define MSR_CORE_THREAD_COUNT 0x35 7 #define MSR_PLATFORM_INFO 0xce 8 #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 9 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ 10 #define PKG_C_STATE_LIMIT_C2_MASK 0x2 11 /* Set MSR_PKG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ 12 #define CORE_C_STATE_LIMIT_C10_MASK 0x70 13 /* Set MSR_PKG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ 14 #define IO_MWAIT_REDIRECT_MASK 0x400 15 /* Set MSR_PKG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ 16 #define CST_CFG_LOCK_MASK 0x8000 17 #define MSR_BIOS_UPGD_TRIG 0x7a 18 #define SGX_ACTIVATE_BIT (1) 19 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 20 #define MSR_EMULATE_PM_TIMER 0x121 21 #define EMULATE_DELAY_OFFSET_VALUE 20 22 #define EMULATE_PM_TMR_EN (1 << 16) 23 #define EMULATE_DELAY_VALUE 0x13 24 #define SMM_MCA_CAP_MSR 0x17d 25 #define SMM_CPU_SVRSTR_BIT 57 26 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) 27 #define MSR_FLEX_RATIO 0x194 28 #define FLEX_RATIO_LOCK (1 << 20) 29 #define FLEX_RATIO_EN (1 << 16) 30 /* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ 31 #define BURST_MODE_DISABLE (1 << 6) 32 #define MSR_TEMPERATURE_TARGET 0x1a2 33 #define TEMPERATURE_TCC_MASK 0xf 34 #define TEMPERATURE_TCC_SHIFT 24 35 #define MSR_PREFETCH_CTL 0x1a4 36 #define PREFETCH_L1_DISABLE (1 << 0) 37 #define PREFETCH_L2_DISABLE (1 << 2) 38 #define DISABLE_CPU_ERROR (1 << 11) 39 #define MSR_MISC_PWR_MGMT 0x1aa 40 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 41 #define MISC_PWR_MGMT_ISST_EN (1 << 6) 42 #define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) 43 #define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) 44 #define MSR_DISABLE_SIGNALING_THREE_STRIKE_EVENT 0x1ab 45 #define THREE_STRIKE_COUNT (1 << 0) 46 #define MSR_TURBO_RATIO_LIMIT 0x1ad 47 #define MSR_PRMRR_PHYS_BASE 0x1f4 48 #define MSR_PRMRR_PHYS_MASK 0x1f5 49 #define PRMRR_PHYS_MASK_LOCK (1 << 10) 50 #define PRMRR_PHYS_MASK_VALID (1 << 11) 51 #define MSR_PRMRR_VALID_CONFIG 0x1fb 52 #define MSR_POWER_CTL 0x1fc 53 #define POWER_CTL_C1E_MASK (1 << 1) 54 #define MSR_PRMRR_BASE_0 0x2a0 55 #define MSR_EVICT_CTL 0x2e0 56 #define MSR_LT_CONTROL 0x2e7 57 #define LT_CONTROL_LOCK (1 << 0) 58 #define MSR_SGX_OWNEREPOCH0 0x300 59 #define MSR_SGX_OWNEREPOCH1 0x301 60 #define SMM_FEATURE_CONTROL_MSR 0x4e0 61 #define SMM_CPU_SAVE_EN (1 << 1) 62 #define MSR_PKG_POWER_SKU_UNIT 0x606 63 #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a 64 #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b 65 #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c 66 #define MSR_PKG_POWER_LIMIT 0x610 67 /* 68 * For Mobile, RAPL default PL1 time window value set to 28 seconds. 69 * RAPL time window calculation defined as follows: 70 * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], 71 * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. 72 */ 73 #define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e 74 #define MSR_PKG_POWER_SKU 0x614 75 #define MSR_DDR_RAPL_LIMIT 0x618 76 #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 77 #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 78 #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 79 #define IRTL_VALID (1 << 15) 80 #define IRTL_1_NS (0 << 10) 81 #define IRTL_32_NS (1 << 10) 82 #define IRTL_1024_NS (2 << 10) 83 #define IRTL_32768_NS (3 << 10) 84 #define IRTL_1048576_NS (4 << 10) 85 #define IRTL_33554432_NS (5 << 10) 86 #define IRTL_RESPONSE_MASK (0x3ff) 87 #define MSR_COUNTER_24_MHZ 0x637 88 #define MSR_CONFIG_TDP_NOMINAL 0x648 89 #define MSR_CONFIG_TDP_LEVEL1 0x649 90 #define MSR_CONFIG_TDP_LEVEL2 0x64a 91 #define MSR_CONFIG_TDP_CONTROL 0x64b 92 #define MSR_TURBO_ACTIVATION_RATIO 0x64c 93 #define PKG_POWER_LIMIT_MASK (0x7fff) 94 #define PKG_POWER_LIMIT_EN (1 << 15) 95 #define PKG_POWER_LIMIT_CLAMP (1 << 16) 96 #define PKG_POWER_LIMIT_TIME_SHIFT 17 97 #define PKG_POWER_LIMIT_TIME_MASK (0x7f) 98 #define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24 99 #define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f) 100 101 #define MSR_CORE_MKTME_ACTIVATION 0x9ff 102 /* SMM save state MSRs */ 103 #define SMBASE_MSR 0xc20 104 #define IEDBASE_MSR 0xc22 105 106 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) 107 108 /* MTRR_CAP_MSR bits */ 109 #define SMRR_SUPPORTED (1<<11) 110 #define PRMRR_SUPPORTED (1<<12) 111 #define SMRR_LOCK_SUPPORTED (1<<14) 112 113 #define SGX_SUPPORTED (1<<2) 114 #define TME_SUPPORTED (1<<13) 115 116 #define KEYLOCKER_SUPPORTED (1<<23) 117 #define KEYLOCKER_AESKL (1) 118 119 #endif /* SOC_INTEL_COMMON_MSR_H */ 120