1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ 4 #define __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ 5 6 #define EPBAR 0x40 7 #define MCHBAR 0x48 8 9 #define GGC 0x50 /* GMCH Graphics Control */ 10 #define DEVEN 0x54 /* Device Enable */ 11 #define DEVEN_D7EN (1 << 14) 12 #define DEVEN_PEG60 (1 << 13) 13 #define DEVEN_D4EN (1 << 7) 14 #define DEVEN_IGD (1 << 4) 15 #define DEVEN_PEG10 (1 << 3) 16 #define DEVEN_PEG11 (1 << 2) 17 #define DEVEN_PEG12 (1 << 1) 18 #define DEVEN_HOST (1 << 0) 19 20 #define PAVPC 0x58 /* Protected Audio Video Path Control */ 21 #define DPR 0x5c /* DMA Protected Range */ 22 23 #define PCIEXBAR 0x60 24 #define DMIBAR 0x68 25 26 #define MESEG_BASE 0x70 27 #define MESEG_MASK 0x78 28 #define MELCK (1 << 10) /* ME Range Lock */ 29 #define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ 30 31 #define PAM0 0x80 32 #define PAM1 0x81 33 #define PAM2 0x82 34 #define PAM3 0x83 35 #define PAM4 0x84 36 #define PAM5 0x85 37 #define PAM6 0x86 38 39 #define LAC 0x87 /* Legacy Access Control */ 40 #define SMRAM 0x88 /* System Management RAM Control */ 41 42 #define REMAPBASE 0x90 43 #define REMAPLIMIT 0x98 44 #define TOM 0xa0 45 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ 46 #define BDSM 0xb0 /* Base Data of Stolen Memory */ 47 #define BGSM 0xb4 /* Base GTT Stolen Memory */ 48 #define TSEGMB 0xb8 /* TSEG Memory Base */ 49 #define TOLUD 0xbc /* Top of Low Used Memory */ 50 51 #define CAPID0_A 0xe4 /* Capabilities Register A */ 52 #define CAPID_ECCDIS (1 << 25) 53 #define CAPID_DDPCD (1 << 14) 54 #define CAPID_PDCD (1 << 12) 55 #define CAPID_WRTVREF (1 << 1) 56 #define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) 57 58 #define CAPID0_B 0xe8 /* Capabilities Register B */ 59 60 #define SKPAD 0xdc /* Scratchpad Data */ 61 62 #define DIDOR 0xf3 /* Device ID override, for debug and samples only */ 63 64 #endif /* __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ */ 65