1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_NVIDIA_TEGRA210_MC_H__ 4 #define __SOC_NVIDIA_TEGRA210_MC_H__ 5 6 #include <stddef.h> 7 #include <stdint.h> 8 9 // Memory Controller registers we need/care about 10 11 struct tegra_mc_regs { 12 uint32_t rsvd_0x0[4]; /* 0x00 */ 13 uint32_t smmu_config; /* 0x10 */ 14 uint32_t smmu_tlb_config; /* 0x14 */ 15 uint32_t smmu_ptc_config; /* 0x18 */ 16 uint32_t smmu_ptb_asid; /* 0x1c */ 17 uint32_t smmu_ptb_data; /* 0x20 */ 18 uint32_t rsvd_0x24[3]; /* 0x24 */ 19 uint32_t smmu_tlb_flush; /* 0x30 */ 20 uint32_t smmu_ptc_flush; /* 0x34 */ 21 uint32_t rsvd_0x38[6]; /* 0x38 */ 22 uint32_t emem_cfg; /* 0x50 */ 23 uint32_t emem_adr_cfg; /* 0x54 */ 24 uint32_t emem_adr_cfg_dev0; /* 0x58 */ 25 uint32_t emem_adr_cfg_dev1; /* 0x5c */ 26 uint32_t emem_adr_cfg_channel_mask; /* 0x60 */ 27 uint32_t emem_adr_cfg_bank_mask_0; /* 0x64 */ 28 uint32_t emem_adr_cfg_bank_mask_1; /* 0x68 */ 29 uint32_t emem_adr_cfg_bank_mask_2; /* 0x6c */ 30 uint32_t security_cfg0; /* 0x70 */ 31 uint32_t security_cfg1; /* 0x74 */ 32 uint32_t rsvd_0x78[6]; /* 0x78 */ 33 uint32_t emem_arb_cfg; /* 0x90 */ 34 uint32_t emem_arb_outstanding_req; /* 0x94 */ 35 uint32_t emem_arb_timing_rcd; /* 0x98 */ 36 uint32_t emem_arb_timing_rp; /* 0x9c */ 37 uint32_t emem_arb_timing_rc; /* 0xa0 */ 38 uint32_t emem_arb_timing_ras; /* 0xa4 */ 39 uint32_t emem_arb_timing_faw; /* 0xa8 */ 40 uint32_t emem_arb_timing_rrd; /* 0xac */ 41 uint32_t emem_arb_timing_rap2pre; /* 0xb0 */ 42 uint32_t emem_arb_timing_wap2pre; /* 0xb4 */ 43 uint32_t emem_arb_timing_r2r; /* 0xb8 */ 44 uint32_t emem_arb_timing_w2w; /* 0xbc */ 45 uint32_t emem_arb_timing_r2w; /* 0xc0 */ 46 uint32_t emem_arb_timing_w2r; /* 0xc4 */ 47 uint32_t emem_arb_misc2; /* 0xC8 */ 48 uint32_t rsvd_0xcc[1]; /* 0xCC */ 49 uint32_t emem_arb_da_turns; /* 0xd0 */ 50 uint32_t emem_arb_da_covers; /* 0xd4 */ 51 uint32_t emem_arb_misc0; /* 0xd8 */ 52 uint32_t emem_arb_misc1; /* 0xdc */ 53 uint32_t emem_arb_ring1_throttle; /* 0xe0 */ 54 uint32_t emem_arb_ring3_throttle; /* 0xe4 */ 55 uint32_t emem_arb_override; /* 0xe8 */ 56 uint32_t emem_arb_rsv; /* 0xec */ 57 uint32_t rsvd_0xf0[1]; /* 0xf0 */ 58 uint32_t clken_override; /* 0xf4 */ 59 uint32_t timing_control_dbg; /* 0xf8 */ 60 uint32_t timing_control; /* 0xfc */ 61 uint32_t stat_control; /* 0x100 */ 62 uint32_t rsvd_0x104[65]; /* 0x104 */ 63 uint32_t emem_arb_isochronous_0; /* 0x208 */ 64 uint32_t emem_arb_isochronous_1; /* 0x20c */ 65 uint32_t emem_arb_isochronous_2; /* 0x210 */ 66 uint32_t rsvd_0x214[38]; /* 0x214 */ 67 uint32_t dis_extra_snap_levels; /* 0x2ac */ 68 uint32_t rsvd_0x2b0[90]; /* 0x2b0 */ 69 uint32_t video_protect_vpr_override; /* 0x418 */ 70 uint32_t rsvd_0x41c[93]; /* 0x41c */ 71 uint32_t video_protect_vpr_override1; /* 0x590 */ 72 uint32_t rsvd_0x594[29]; /* 0x594 */ 73 uint32_t display_snap_ring; /* 0x608 */ 74 uint32_t rsvd_0x60c[15]; /* 0x60c */ 75 uint32_t video_protect_bom; /* 0x648 */ 76 uint32_t video_protect_size_mb; /* 0x64c */ 77 uint32_t video_protect_reg_ctrl; /* 0x650 */ 78 uint32_t rsvd_0x654[4]; /* 0x654 */ 79 uint32_t emem_cfg_access_ctrl; /* 0x664 */ 80 uint32_t rsvd_0x668[2]; /* 0x668 */ 81 uint32_t sec_carveout_bom; /* 0x670 */ 82 uint32_t sec_carveout_size_mb; /* 0x674 */ 83 uint32_t sec_carveout_reg_ctrl; /* 0x678 */ 84 uint32_t rsvd_0x67c[17]; /* 0x67C-0x6BC */ 85 86 uint32_t emem_arb_timing_rfcpb; /* 0x6C0 */ 87 uint32_t emem_arb_timing_ccdmw; /* 0x6C4 */ 88 uint32_t rsvd_0x6c8[10]; /* 0x6C8-0x6EC */ 89 90 uint32_t emem_arb_refpb_hp_ctrl; /* 0x6F0 */ 91 uint32_t emem_arb_refpb_bank_ctrl; /* 0x6F4 */ 92 uint32_t rsvd_0x6f8[156]; /* 0x6F8-0x964 */ 93 94 uint32_t emem_arb_override_1; /* 0x968 */ 95 uint32_t rsvd_0x96c[3]; /* 0x96c */ 96 uint32_t video_protect_bom_adr_hi; /* 0x978 */ 97 uint32_t rsvd_0x97c[2]; /* 0x97c */ 98 uint32_t video_protect_gpu_override_0; /* 0x984 */ 99 uint32_t video_protect_gpu_override_1; /* 0x988 */ 100 uint32_t rsvd_0x98c[5]; /* 0x98c */ 101 uint32_t mts_carveout_bom; /* 0x9a0 */ 102 uint32_t mts_carveout_size_mb; /* 0x9a4 */ 103 uint32_t mts_carveout_adr_hi; /* 0x9a8 */ 104 uint32_t mts_carveout_reg_ctrl; /* 0x9ac */ 105 uint32_t rsvd_0x9b0[4]; /* 0x9b0 */ 106 uint32_t emem_bank_swizzle_cfg0; /* 0x9c0 */ 107 uint32_t emem_bank_swizzle_cfg1; /* 0x9c4 */ 108 uint32_t emem_bank_swizzle_cfg2; /* 0x9c8 */ 109 uint32_t emem_bank_swizzle_cfg3; /* 0x9cc */ 110 uint32_t rsvd_0x9d0[1]; /* 0x9d0 */ 111 uint32_t sec_carveout_adr_hi; /* 0x9d4 */ 112 uint32_t rsvd_0x9d8; /* 0x9D8 */ 113 uint32_t da_config0; /* 0x9DC */ 114 uint32_t rsvd_0x9c0[138]; /* 0x9E0-0xc04 */ 115 116 uint32_t security_carveout1_cfg0; /* 0xc08 */ 117 uint32_t security_carveout1_bom; /* 0xc0c */ 118 uint32_t security_carveout1_bom_hi; /* 0xc10 */ 119 uint32_t security_carveout1_size_128kb; /* 0xc14 */ 120 uint32_t security_carveout1_ca0; /* 0xc18 */ 121 uint32_t security_carveout1_ca1; /* 0xc1c */ 122 uint32_t security_carveout1_ca2; /* 0xc20 */ 123 uint32_t security_carveout1_ca3; /* 0xc24 */ 124 uint32_t security_carveout1_ca4; /* 0xc28 */ 125 uint32_t security_carveout1_cfia0; /* 0xc2c */ 126 uint32_t security_carveout1_cfia1; /* 0xc30 */ 127 uint32_t security_carveout1_cfia2; /* 0xc34 */ 128 uint32_t security_carveout1_cfia3; /* 0xc38 */ 129 uint32_t security_carveout1_cfia4; /* 0xc3c */ 130 uint32_t rsvd_0xc40[6]; /* 0xc40-0xc54 */ 131 132 uint32_t security_carveout2_cfg0; /* 0xc58 */ 133 uint32_t security_carveout2_bom; /* 0xc5c */ 134 uint32_t security_carveout2_bom_hi; /* 0xc60 */ 135 uint32_t security_carveout2_size_128kb; /* 0xc64 */ 136 uint32_t security_carveout2_ca0; /* 0xc68 */ 137 uint32_t security_carveout2_ca1; /* 0xc6c */ 138 uint32_t security_carveout2_ca2; /* 0xc70 */ 139 uint32_t security_carveout2_ca3; /* 0xc74 */ 140 uint32_t security_carveout2_ca4; /* 0xc78 */ 141 uint32_t security_carveout2_cfia0; /* 0xc7c */ 142 uint32_t security_carveout2_cfia1; /* 0xc80 */ 143 uint32_t security_carveout2_cfia2; /* 0xc84 */ 144 uint32_t security_carveout2_cfia3; /* 0xc88 */ 145 uint32_t security_carveout2_cfia4; /* 0xc8c */ 146 uint32_t rsvd_0xc90[6]; /* 0xc90-0xca4 */ 147 148 uint32_t security_carveout3_cfg0; /* 0xca8 */ 149 uint32_t security_carveout3_bom; /* 0xcac */ 150 uint32_t security_carveout3_bom_hi; /* 0xcb0 */ 151 uint32_t security_carveout3_size_128kb; /* 0xcb4 */ 152 uint32_t security_carveout3_ca0; /* 0xcb8 */ 153 uint32_t security_carveout3_ca1; /* 0xcbc */ 154 uint32_t security_carveout3_ca2; /* 0xcc0 */ 155 uint32_t security_carveout3_ca3; /* 0xcc4 */ 156 uint32_t security_carveout3_ca4; /* 0xcc8 */ 157 uint32_t security_carveout3_cfia0; /* 0xccc */ 158 uint32_t security_carveout3_cfia1; /* 0xcd0 */ 159 uint32_t security_carveout3_cfia2; /* 0xcd4 */ 160 uint32_t security_carveout3_cfia3; /* 0xcd8 */ 161 uint32_t security_carveout3_cfia4; /* 0xcdc */ 162 uint32_t rsvd_0xce0[6]; /* 0xce0-0xcf4 */ 163 164 uint32_t security_carveout4_cfg0; /* 0xcf8 */ 165 uint32_t security_carveout4_bom; /* 0xcfc */ 166 uint32_t security_carveout4_bom_hi; /* 0xd00 */ 167 uint32_t security_carveout4_size_128kb; /* 0xd04 */ 168 uint32_t security_carveout4_ca0; /* 0xd08 */ 169 uint32_t security_carveout4_ca1; /* 0xd0c */ 170 uint32_t security_carveout4_ca2; /* 0xd10 */ 171 uint32_t security_carveout4_ca3; /* 0xd14 */ 172 uint32_t security_carveout4_ca4; /* 0xd18 */ 173 uint32_t security_carveout4_cfia0; /* 0xd1c */ 174 uint32_t security_carveout4_cfia1; /* 0xd20 */ 175 uint32_t security_carveout4_cfia2; /* 0xd24 */ 176 uint32_t security_carveout4_cfia3; /* 0xd28 */ 177 uint32_t security_carveout4_cfia4; /* 0xd2c */ 178 uint32_t rsvd_0xd30[6]; /* 0xd30-0xd44 */ 179 180 uint32_t security_carveout5_cfg0; /* 0xd48 */ 181 uint32_t security_carveout5_bom; /* 0xd4c */ 182 uint32_t security_carveout5_bom_hi; /* 0xd50 */ 183 uint32_t security_carveout5_size_128kb; /* 0xd54 */ 184 uint32_t security_carveout5_ca0; /* 0xd58 */ 185 uint32_t security_carveout5_ca1; /* 0xd5c */ 186 uint32_t security_carveout5_ca2; /* 0xd60 */ 187 uint32_t security_carveout5_ca3; /* 0xd64 */ 188 uint32_t security_carveout5_ca4; /* 0xd68 */ 189 uint32_t security_carveout5_cfia0; /* 0xd6c */ 190 uint32_t security_carveout5_cfia1; /* 0xd70 */ 191 uint32_t security_carveout5_cfia2; /* 0xd74 */ 192 uint32_t security_carveout5_cfia3; /* 0xd78 */ 193 uint32_t security_carveout5_cfia4; /* 0xd7c */ 194 }; 195 196 enum { 197 MC_SMMU_CONFIG_ENABLE = 1, 198 199 MC_EMEM_CFG_SIZE_MB_SHIFT = 0, 200 MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff, 201 202 MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, 203 MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, 204 205 MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1, 206 207 MC_TIMING_CONTROL_TIMING_UPDATE = 1, 208 }; 209 210 #define MC_SECURITY_CARVEOUT_LOCKED (1 << 1) 211 #define MC_VPR_WR_ACCESS_DISABLE (1 << 0) 212 #define MC_VPR_ALLOW_TZ_WR_ACCESS_ENABLE (1 << 1) 213 214 check_member(tegra_mc_regs, security_carveout5_cfia4, 0xd7c); 215 216 #endif /* __SOC_NVIDIA_TEGRA210_MC_H__ */ 217