1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef _SOC_COMMON_BLOCK_LPC_LIB_H_ 4 #define _SOC_COMMON_BLOCK_LPC_LIB_H_ 5 6 #include <device/device.h> 7 #include <stddef.h> 8 #include <stdint.h> 9 10 /* 11 * IO decode enable macros are in the format IO_<peripheral>_<IO port>. 12 * For example, to open ports 0x60, 0x64 for the keyboard controller, 13 * use IOE_KBC_60_64 macro. For IOE_ macros that do not specify a port range, 14 * the port range is selectable via the IO decodes register. 15 */ 16 #define LPC_IOE_EC_4E_4F (1 << 13) 17 #define LPC_IOE_SUPERIO_2E_2F (1 << 12) 18 #define LPC_IOE_EC_62_66 (1 << 11) 19 #define LPC_IOE_KBC_60_64 (1 << 10) 20 #define LPC_IOE_HGE_208 (1 << 9) 21 #define LPC_IOE_LGE_200 (1 << 8) 22 #define LPC_IOE_FDD_EN (1 << 3) 23 #define LPC_IOE_LPT_EN (1 << 2) 24 #define LPC_IOE_COMB_EN (1 << 1) 25 #define LPC_IOE_COMA_EN (1 << 0) 26 #define LPC_NUM_GENERIC_IO_RANGES 4 27 28 /* LPC PCR configuration */ 29 #define PCR_LPC_PRC 0x341c 30 #define PCR_LPC_CCE_EN 0xf 31 #define PCR_LPC_PCE_EN (9 << 8) 32 33 /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ 34 enum serirq_mode { 35 SERIRQ_QUIET, 36 SERIRQ_CONTINUOUS, 37 SERIRQ_OFF, 38 }; 39 40 /* 41 * Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together. 42 * Output:I/O Enable Bits 43 */ 44 uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables); 45 /* Return the current decode settings */ 46 uint16_t lpc_get_fixed_io_decode(void); 47 /* Set the current decode ranges */ 48 uint16_t lpc_set_fixed_io_ranges(uint16_t io_ranges, uint16_t mask); 49 /* Open a generic IO window to the LPC bus. Four windows are available. */ 50 void lpc_open_pmio_window(uint16_t base, uint16_t size); 51 /* Open a generic MMIO window to the LPC bus. One window is available. */ 52 void lpc_open_mmio_window(uintptr_t base, size_t size); 53 /* Init SoC Specific LPC features. Common definition will be weak and 54 each soc will need to define the init. */ 55 void lpc_soc_init(struct device *dev); 56 /* Fill up LPC IO resource structure inside SoC directory */ 57 void pch_lpc_soc_fill_io_resources(struct device *dev); 58 /* Set LPC BIOS Control BILD bit. */ 59 void lpc_set_bios_interface_lock_down(void); 60 /* Set LPC BIOS Control LE bit. */ 61 void lpc_set_lock_enable(void); 62 /* Set LPC BIOS Control EISS bit. */ 63 void lpc_set_eiss(void); 64 /* Set LPC BIOS Decode LE bit */ 65 void lpc_set_bde(void); 66 /* Set LPC Serial IRQ mode. */ 67 void lpc_set_serirq_mode(enum serirq_mode mode); 68 /* Enable CLKRUN_EN for power gating LPC. */ 69 void lpc_enable_pci_clk_cntl(void); 70 /* LPC Clock Run is a feature to stop LPC clock unless a peripheral objects. */ 71 void lpc_disable_clkrun(void); 72 /* 73 * Setup I/O Decode Range Register for LPC 74 * ComA Range 3F8h-3FFh [2:0] 75 * ComB Range 2F8h-2FFh [6:4] 76 * Enable ComA and ComB Port 77 */ 78 void lpc_io_setup_comm_a_b(void); 79 /* Enable PCH LPC by setting up generic decode range registers. */ 80 void pch_enable_lpc(void); 81 /* Get SoC's generic IO decoder range register settings. */ 82 void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); 83 /* Add resource into LPC PCI device space */ 84 void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, 85 uintptr_t base, size_t size, unsigned long flags); 86 /* Enable PCH IOAPIC */ 87 void pch_enable_ioapic(void); 88 /* Retrieve and setup PCH LPC interrupt routing. */ 89 void pch_pirq_init(void); 90 /* 91 * LPC MISC programming 92 * 1. Setup NMI on errors, disable SERR 93 * 2. Disable NMI sources 94 */ 95 void pch_misc_init(void); 96 /* 97 * Calls acpi_write_hpet which creates and fills HPET table and 98 * adds it to the RSDT (and XSDT) structure. 99 */ 100 unsigned long southbridge_write_acpi_tables(const struct device *device, 101 unsigned long current, 102 struct acpi_rsdp *rsdp); 103 const uint8_t *lpc_get_pic_pirq_routing(size_t *num); 104 /* Enable LPC Write Protect. */ 105 void lpc_enable_wp(void); 106 /* Disable LPC Write Protect. */ 107 void lpc_disable_wp(void); 108 #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ 109