1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_rng.h
4 * @author MCD Application Team
5 * @brief Header file of RNG LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_RNG_H
22 #define STM32L4xx_LL_RNG_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (RNG)
36
37 /** @defgroup RNG_LL RNG
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45
46 /* Exported types ------------------------------------------------------------*/
47 #if defined(RNG_CR_CED)
48 #if defined(USE_FULL_LL_DRIVER)
49 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
50 * @{
51 */
52
53
54 /**
55 * @brief LL RNG Init Structure Definition
56 */
57 typedef struct
58 {
59 uint32_t ClockErrorDetection; /*!< Clock error detection.
60 This parameter can be one value of @ref RNG_LL_CED.
61
62 This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */
63 } LL_RNG_InitTypeDef;
64
65 /**
66 * @}
67 */
68 #endif /* USE_FULL_LL_DRIVER */
69 #endif
70 /* Exported constants --------------------------------------------------------*/
71 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
72 * @{
73 */
74
75 #if defined(RNG_CR_CED)
76 /** @defgroup RNG_LL_CED Clock Error Detection
77 * @{
78 */
79 #define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
80 #define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
81 /**
82 * @}
83 */
84 #endif
85
86 #if defined(RNG_CR_CONDRST)
87 /** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
88 * programmable divider acting on the incoming RNG clock
89 * @{
90 */
91 #define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
92 #define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
93 /*!< 2 RNG clock cycles per internal RNG clock */
94 #define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
95 /*!< 4 RNG clock cycles per internal RNG clock */
96 #define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
97 /*!< 8 RNG clock cycles per internal RNG clock */
98 #define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
99 /*!< 16 RNG clock cycles per internal RNG clock */
100 #define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
101 /*!< 32 RNG clock cycles per internal RNG clock */
102 #define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
103 /*!< 64 RNG clock cycles per internal RNG clock */
104 #define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
105 /*!< 128 RNG clock cycles per internal RNG clock */
106 #define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
107 /*!< 256 RNG clock cycles per internal RNG clock */
108 #define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
109 /*!< 512 RNG clock cycles per internal RNG clock */
110 #define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
111 /*!< 1024 RNG clock cycles per internal RNG clock */
112 #define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
113 /*!< 2048 RNG clock cycles per internal RNG clock */
114 #define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
115 /*!< 4096 RNG clock cycles per internal RNG clock */
116 #define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
117 /*!< 8192 RNG clock cycles per internal RNG clock */
118 #define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
119 /*!< 16384 RNG clock cycles per internal RNG clock */
120 #define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
121 /*!< 32768 RNG clock cycles per internal RNG clock */
122 /**
123 * @}
124 */
125
126 /** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
127 * @{
128 */
129 #define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/
130 #define LL_RNG_NOTNIST_COMPLIANT (RNG_CR_NISTC) /*!< Non NIST compliant configuration */
131
132 /**
133 * @}
134 */
135 #endif/*RNG_CR_CONDRST*/
136 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
137 * @brief Flags defines which can be used with LL_RNG_ReadReg function
138 * @{
139 */
140 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
141 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
142 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
143 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
144 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
145 /**
146 * @}
147 */
148
149 /** @defgroup RNG_LL_EC_IT IT Defines
150 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
151 * @{
152 */
153 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
154 /**
155 * @}
156 */
157
158 /**
159 * @}
160 */
161
162 /* Exported macro ------------------------------------------------------------*/
163 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
164 * @{
165 */
166
167 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
168 * @{
169 */
170
171 /**
172 * @brief Write a value in RNG register
173 * @param __INSTANCE__ RNG Instance
174 * @param __REG__ Register to be written
175 * @param __VALUE__ Value to be written in the register
176 * @retval None
177 */
178 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
179
180 /**
181 * @brief Read a value in RNG register
182 * @param __INSTANCE__ RNG Instance
183 * @param __REG__ Register to be read
184 * @retval Register value
185 */
186 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
187 /**
188 * @}
189 */
190
191 /**
192 * @}
193 */
194
195
196 /* Exported functions --------------------------------------------------------*/
197 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
198 * @{
199 */
200 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
201 * @{
202 */
203
204 /**
205 * @brief Enable Random Number Generation
206 * @rmtoll CR RNGEN LL_RNG_Enable
207 * @param RNGx RNG Instance
208 * @retval None
209 */
LL_RNG_Enable(RNG_TypeDef * RNGx)210 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
211 {
212 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
213 }
214
215 /**
216 * @brief Disable Random Number Generation
217 * @rmtoll CR RNGEN LL_RNG_Disable
218 * @param RNGx RNG Instance
219 * @retval None
220 */
LL_RNG_Disable(RNG_TypeDef * RNGx)221 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
222 {
223 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
224 }
225
226 /**
227 * @brief Check if Random Number Generator is enabled
228 * @rmtoll CR RNGEN LL_RNG_IsEnabled
229 * @param RNGx RNG Instance
230 * @retval State of bit (1 or 0).
231 */
LL_RNG_IsEnabled(RNG_TypeDef * RNGx)232 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
233 {
234 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
235 }
236
237 #if defined(RNG_CR_CED)
238 /**
239 * @brief Enable Clock Error Detection
240 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
241 * @param RNGx RNG Instance
242 * @retval None
243 */
LL_RNG_EnableClkErrorDetect(RNG_TypeDef * RNGx)244 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
245 {
246 CLEAR_BIT(RNGx->CR, RNG_CR_CED);
247 }
248
249 /**
250 * @brief Disable RNG Clock Error Detection
251 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
252 * @param RNGx RNG Instance
253 * @retval None
254 */
LL_RNG_DisableClkErrorDetect(RNG_TypeDef * RNGx)255 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
256 {
257 SET_BIT(RNGx->CR, RNG_CR_CED);
258 }
259
260 /**
261 * @brief Check if RNG Clock Error Detection is enabled
262 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
263 * @param RNGx RNG Instance
264 * @retval State of bit (1 or 0).
265 */
LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef * RNGx)266 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
267 {
268 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
269 }
270
271 #if defined(RNG_CR_CONDRST)
272 /**
273 * @brief Set RNG Conditioning Soft Reset bit
274 * @rmtoll CR CONDRST LL_RNG_SetConditioningResetBit
275 * @param RNGx RNG Instance
276 * @retval None
277 */
LL_RNG_SetConditioningResetBit(RNG_TypeDef * RNGx)278 __STATIC_INLINE void LL_RNG_SetConditioningResetBit(RNG_TypeDef *RNGx)
279 {
280 SET_BIT(RNGx->CR, RNG_CR_CONDRST);
281 }
282
283 /**
284 * @brief Reset RNG Conditioning Soft Reset bit
285 * @rmtoll CR CONDRST LL_RNG_ResetConditioningResetBit
286 * @param RNGx RNG Instance
287 * @retval None
288 */
LL_RNG_ResetConditioningResetBit(RNG_TypeDef * RNGx)289 __STATIC_INLINE void LL_RNG_ResetConditioningResetBit(RNG_TypeDef *RNGx)
290 {
291 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
292 }
293
294 /**
295 * @brief Check if RNG Conditioning Soft Reset bit is set
296 * @rmtoll CR CONDRST LL_RNG_IsResetConditioningBitSet
297 * @param RNGx RNG Instance
298 * @retval State of bit (1 or 0).
299 */
LL_RNG_IsResetConditioningBitSet(RNG_TypeDef * RNGx)300 __STATIC_INLINE uint32_t LL_RNG_IsResetConditioningBitSet(RNG_TypeDef *RNGx)
301 {
302 return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
303 }
304
305 /**
306 * @brief Enable RNG Config Lock
307 * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
308 * @param RNGx RNG Instance
309 * @retval None
310 */
LL_RNG_ConfigLock(RNG_TypeDef * RNGx)311 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
312 {
313 SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
314 }
315
316 /**
317 * @brief Check if RNG Config Lock is enabled
318 * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
319 * @param RNGx RNG Instance
320 * @retval State of bit (1 or 0).
321 */
LL_RNG_IsConfigLocked(RNG_TypeDef * RNGx)322 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
323 {
324 return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
325 }
326
327 /**
328 * @brief Enable NIST Compliance
329 * @rmtoll CR NISTC LL_RNG_EnableNistCompliance
330 * @param RNGx RNG Instance
331 * @retval None
332 */
LL_RNG_EnableNistCompliance(RNG_TypeDef * RNGx)333 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
334 {
335 CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
336 }
337
338 /**
339 * @brief Disable NIST Compliance
340 * @rmtoll CR NISTC LL_RNG_DisableNistCompliance
341 * @param RNGx RNG Instance
342 * @retval None
343 */
LL_RNG_DisableNistCompliance(RNG_TypeDef * RNGx)344 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
345 {
346 SET_BIT(RNGx->CR, RNG_CR_NISTC);
347 }
348
349 /**
350 * @brief Check if NIST Compliance is enabled
351 * @rmtoll CR NISTC LL_RNG_IsNistComplianceEnabled
352 * @param RNGx RNG Instance
353 * @retval State of bit (1 or 0).
354 */
LL_RNG_IsNistComplianceEnabled(RNG_TypeDef * RNGx)355 __STATIC_INLINE uint32_t LL_RNG_IsNistComplianceEnabled(RNG_TypeDef *RNGx)
356 {
357 return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
358 }
359
360 /**
361 * @brief Set RNG Config1 Configuration field value
362 * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
363 * @param RNGx RNG Instance
364 * @param Config1 Value between 0 and 0x3F
365 * @retval None
366 */
LL_RNG_SetConfig1(RNG_TypeDef * RNGx,uint32_t Config1)367 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
368 {
369 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
370 }
371
372 /**
373 * @brief Get RNG Config1 Configuration field value
374 * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
375 * @param RNGx RNG Instance
376 * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
377 */
LL_RNG_GetConfig1(RNG_TypeDef * RNGx)378 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
379 {
380 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
381 }
382
383 /**
384 * @brief Set RNG Config2 Configuration field value
385 * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
386 * @param RNGx RNG Instance
387 * @param Config2 Value between 0 and 0x7
388 * @retval None
389 */
LL_RNG_SetConfig2(RNG_TypeDef * RNGx,uint32_t Config2)390 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
391 {
392 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
393 }
394
395 /**
396 * @brief Get RNG Config2 Configuration field value
397 * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
398 * @param RNGx RNG Instance
399 * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
400 */
LL_RNG_GetConfig2(RNG_TypeDef * RNGx)401 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
402 {
403 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
404 }
405
406 /**
407 * @brief Set RNG Config3 Configuration field value
408 * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
409 * @param RNGx RNG Instance
410 * @param Config3 Value between 0 and 0xF
411 * @retval None
412 */
LL_RNG_SetConfig3(RNG_TypeDef * RNGx,uint32_t Config3)413 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
414 {
415 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
416 }
417
418 /**
419 * @brief Get RNG Config3 Configuration field value
420 * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
421 * @param RNGx RNG Instance
422 * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
423 */
LL_RNG_GetConfig3(RNG_TypeDef * RNGx)424 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
425 {
426 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
427 }
428
429 /**
430 * @brief Set RNG Clock divider factor
431 * @rmtoll CR CLKDIV LL_RNG_SetClockDivider
432 * @param RNGx RNG Instance
433 * @param Divider can be one of the following values:
434 * @arg @ref LL_RNG_CLKDIV_BY_1
435 * @arg @ref LL_RNG_CLKDIV_BY_2
436 * @arg @ref LL_RNG_CLKDIV_BY_4
437 * @arg @ref LL_RNG_CLKDIV_BY_8
438 * @arg @ref LL_RNG_CLKDIV_BY_16
439 * @arg @ref LL_RNG_CLKDIV_BY_32
440 * @arg @ref LL_RNG_CLKDIV_BY_64
441 * @arg @ref LL_RNG_CLKDIV_BY_128
442 * @arg @ref LL_RNG_CLKDIV_BY_256
443 * @arg @ref LL_RNG_CLKDIV_BY_512
444 * @arg @ref LL_RNG_CLKDIV_BY_1024
445 * @arg @ref LL_RNG_CLKDIV_BY_2048
446 * @arg @ref LL_RNG_CLKDIV_BY_4096
447 * @arg @ref LL_RNG_CLKDIV_BY_8192
448 * @arg @ref LL_RNG_CLKDIV_BY_16384
449 * @arg @ref LL_RNG_CLKDIV_BY_32768
450 * @retval None
451 */
LL_RNG_SetClockDivider(RNG_TypeDef * RNGx,uint32_t Divider)452 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
453 {
454 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
455 }
456
457 /**
458 * @brief Get RNG Clock divider factor
459 * @rmtoll CR CLKDIV LL_RNG_GetClockDivider
460 * @param RNGx RNG Instance
461 * @retval Returned value can be one of the following values:
462 * @arg @ref LL_RNG_CLKDIV_BY_1
463 * @arg @ref LL_RNG_CLKDIV_BY_2
464 * @arg @ref LL_RNG_CLKDIV_BY_4
465 * @arg @ref LL_RNG_CLKDIV_BY_8
466 * @arg @ref LL_RNG_CLKDIV_BY_16
467 * @arg @ref LL_RNG_CLKDIV_BY_32
468 * @arg @ref LL_RNG_CLKDIV_BY_64
469 * @arg @ref LL_RNG_CLKDIV_BY_128
470 * @arg @ref LL_RNG_CLKDIV_BY_256
471 * @arg @ref LL_RNG_CLKDIV_BY_512
472 * @arg @ref LL_RNG_CLKDIV_BY_1024
473 * @arg @ref LL_RNG_CLKDIV_BY_2048
474 * @arg @ref LL_RNG_CLKDIV_BY_4096
475 * @arg @ref LL_RNG_CLKDIV_BY_8192
476 * @arg @ref LL_RNG_CLKDIV_BY_16384
477 * @arg @ref LL_RNG_CLKDIV_BY_32768
478 */
LL_RNG_GetClockDivider(RNG_TypeDef * RNGx)479 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
480 {
481 return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
482 }
483 #endif /*RNG_CR_CONDRST*/
484 #endif
485 /**
486 * @}
487 */
488
489 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
490 * @{
491 */
492
493 /**
494 * @brief Indicate if the RNG Data ready Flag is set or not
495 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
496 * @param RNGx RNG Instance
497 * @retval State of bit (1 or 0).
498 */
LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef * RNGx)499 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
500 {
501 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
502 }
503
504 /**
505 * @brief Indicate if the Clock Error Current Status Flag is set or not
506 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
507 * @param RNGx RNG Instance
508 * @retval State of bit (1 or 0).
509 */
LL_RNG_IsActiveFlag_CECS(RNG_TypeDef * RNGx)510 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
511 {
512 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
513 }
514
515 /**
516 * @brief Indicate if the Seed Error Current Status Flag is set or not
517 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
518 * @param RNGx RNG Instance
519 * @retval State of bit (1 or 0).
520 */
LL_RNG_IsActiveFlag_SECS(RNG_TypeDef * RNGx)521 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
522 {
523 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
524 }
525
526 /**
527 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
528 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
529 * @param RNGx RNG Instance
530 * @retval State of bit (1 or 0).
531 */
LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef * RNGx)532 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
533 {
534 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
535 }
536
537 /**
538 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
539 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
540 * @param RNGx RNG Instance
541 * @retval State of bit (1 or 0).
542 */
LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef * RNGx)543 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
544 {
545 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
546 }
547
548 /**
549 * @brief Clear Clock Error interrupt Status (CEIS) Flag
550 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
551 * @param RNGx RNG Instance
552 * @retval None
553 */
LL_RNG_ClearFlag_CEIS(RNG_TypeDef * RNGx)554 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
555 {
556 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
557 }
558
559 /**
560 * @brief Clear Seed Error interrupt Status (SEIS) Flag
561 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
562 * @param RNGx RNG Instance
563 * @retval None
564 */
LL_RNG_ClearFlag_SEIS(RNG_TypeDef * RNGx)565 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
566 {
567 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
568 }
569
570 /**
571 * @}
572 */
573
574 /** @defgroup RNG_LL_EF_IT_Management IT Management
575 * @{
576 */
577
578 /**
579 * @brief Enable Random Number Generator Interrupt
580 * (applies for either Seed error, Clock Error or Data ready interrupts)
581 * @rmtoll CR IE LL_RNG_EnableIT
582 * @param RNGx RNG Instance
583 * @retval None
584 */
LL_RNG_EnableIT(RNG_TypeDef * RNGx)585 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
586 {
587 SET_BIT(RNGx->CR, RNG_CR_IE);
588 }
589
590 /**
591 * @brief Disable Random Number Generator Interrupt
592 * (applies for either Seed error, Clock Error or Data ready interrupts)
593 * @rmtoll CR IE LL_RNG_DisableIT
594 * @param RNGx RNG Instance
595 * @retval None
596 */
LL_RNG_DisableIT(RNG_TypeDef * RNGx)597 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
598 {
599 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
600 }
601
602 /**
603 * @brief Check if Random Number Generator Interrupt is enabled
604 * (applies for either Seed error, Clock Error or Data ready interrupts)
605 * @rmtoll CR IE LL_RNG_IsEnabledIT
606 * @param RNGx RNG Instance
607 * @retval State of bit (1 or 0).
608 */
LL_RNG_IsEnabledIT(RNG_TypeDef * RNGx)609 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
610 {
611 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
612 }
613
614 /**
615 * @}
616 */
617
618 /** @defgroup RNG_LL_EF_Data_Management Data Management
619 * @{
620 */
621
622 /**
623 * @brief Return32-bit Random Number value
624 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
625 * @param RNGx RNG Instance
626 * @retval Generated 32-bit random value
627 */
LL_RNG_ReadRandData32(RNG_TypeDef * RNGx)628 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
629 {
630 return (uint32_t)(READ_REG(RNGx->DR));
631 }
632
633 /**
634 * @}
635 */
636 #if defined(RNG_VER_3_2) || defined (RNG_VER_3_1)
637 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
638 * @{
639 */
640
641 /**
642 * @brief Set RNG Health Test Control
643 * @rmtoll HTCR HTCFG LL_RNG_SetHealthconfiguration
644 * @param RNGx RNG Instance
645 * @param HTCFG can be values of 32 bits
646 * @retval None
647 */
LL_RNG_SetHealthconfiguration(RNG_TypeDef * RNGx,uint32_t HTCFG)648 __STATIC_INLINE void LL_RNG_SetHealthconfiguration(RNG_TypeDef *RNGx, uint32_t HTCFG)
649 {
650 WRITE_REG(RNGx->HTCR, HTCFG);
651 }
652
653 /**
654 * @brief Get RNG Health Test Control
655 * @rmtoll HTCR HTCFG LL_RNG_GetHealthconfiguration
656 * @param RNGx RNG Instance
657 * @retval Return 32-bit RNG Health Test configuration
658 */
LL_RNG_GetHealthconfiguration(RNG_TypeDef * RNGx)659 __STATIC_INLINE uint32_t LL_RNG_GetHealthconfiguration(RNG_TypeDef *RNGx)
660 {
661 return (uint32_t)READ_REG(RNGx->HTCR);
662 }
663
664 /**
665 * @}
666 */
667 #endif /* RNG_VER_3_2 || RNG_VER_3_1 */
668
669 #if defined(USE_FULL_LL_DRIVER)
670 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
671 * @{
672 */
673 #if defined(RNG_CR_CED)
674 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
675 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
676 #endif
677 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
678
679 /**
680 * @}
681 */
682 #endif /* USE_FULL_LL_DRIVER */
683
684 /**
685 * @}
686 */
687
688 /**
689 * @}
690 */
691
692 #endif /* RNG */
693
694 /**
695 * @}
696 */
697
698 #ifdef __cplusplus
699 }
700 #endif
701
702 #endif /* __STM32L4xx_LL_RNG_H */
703
704 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
705