1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_LPUART_H
22 #define STM32L4xx_LL_LPUART_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (LPUART1)
36
37 /** @defgroup LPUART_LL LPUART
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 #if defined(USART_PRESC_PRESCALER)
44 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
45 * @{
46 */
47 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
48 static const uint16_t LPUART_PRESCALER_TAB[] =
49 {
50 (uint16_t)1,
51 (uint16_t)2,
52 (uint16_t)4,
53 (uint16_t)6,
54 (uint16_t)8,
55 (uint16_t)10,
56 (uint16_t)12,
57 (uint16_t)16,
58 (uint16_t)32,
59 (uint16_t)64,
60 (uint16_t)128,
61 (uint16_t)256
62 };
63 /**
64 * @}
65 */
66 #endif /* USART_PRESC_PRESCALER */
67
68 /* Private constants ---------------------------------------------------------*/
69 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
70 * @{
71 */
72 /* Defines used in Baud Rate related macros and corresponding register setting computation */
73 #define LPUART_LPUARTDIV_FREQ_MUL 256U
74 #define LPUART_BRR_MASK 0x000FFFFFU
75 #define LPUART_BRR_MIN_VALUE 0x00000300U
76 /**
77 * @}
78 */
79
80
81 /* Private macros ------------------------------------------------------------*/
82 #if defined(USE_FULL_LL_DRIVER)
83 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
84 * @{
85 */
86 /**
87 * @}
88 */
89 #endif /*USE_FULL_LL_DRIVER*/
90
91 /* Exported types ------------------------------------------------------------*/
92 #if defined(USE_FULL_LL_DRIVER)
93 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
94 * @{
95 */
96
97 /**
98 * @brief LL LPUART Init Structure definition
99 */
100 typedef struct
101 {
102 #if defined(USART_PRESC_PRESCALER)
103 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
104 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
105
106 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/
107
108 #endif /* USART_PRESC_PRESCALER */
109 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
110
111 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
112
113 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
114 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
115
116 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
117
118 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
119 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
120
121 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
122
123 uint32_t Parity; /*!< Specifies the parity mode.
124 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
125
126 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
127
128 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
129 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
130
131 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
132
133 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
134 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
135
136 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
137
138 } LL_LPUART_InitTypeDef;
139
140 /**
141 * @}
142 */
143 #endif /* USE_FULL_LL_DRIVER */
144
145 /* Exported constants --------------------------------------------------------*/
146 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
147 * @{
148 */
149
150 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
151 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
152 * @{
153 */
154 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
155 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
156 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */
157 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
158 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
159 #if defined(USART_CR1_FIFOEN)
160 #define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
161 #endif /* USART_CR1_FIFOEN */
162 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
163 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
164 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
165 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
166 /**
167 * @}
168 */
169
170 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
171 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
172 * @{
173 */
174 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
175 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
176 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
177 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
178 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
179 #if defined(USART_CR1_FIFOEN)
180 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
181 #else
182 #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
183 #endif /* USART_CR1_FIFOEN */
184 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
185 #if defined(USART_CR1_FIFOEN)
186 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
187 #else
188 #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
189 #endif /* USART_CR1_FIFOEN */
190 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
191 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
192 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
193 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
194 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
195 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
196 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
197 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
198 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
199 #if defined(USART_CR1_FIFOEN)
200 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
201 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
202 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
203 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
204 #endif /* USART_CR1_FIFOEN */
205 /**
206 * @}
207 */
208
209 /** @defgroup LPUART_LL_EC_IT IT Defines
210 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
211 * @{
212 */
213 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
214 #if defined(USART_CR1_FIFOEN)
215 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
216 #else
217 #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
218 #endif /* USART_CR1_FIFOEN */
219 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
220 #if defined(USART_CR1_FIFOEN)
221 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
222 #else
223 #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
224 #endif /* USART_CR1_FIFOEN */
225 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
226 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
227 #if defined(USART_CR1_FIFOEN)
228 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
229 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
230 #endif /* USART_CR1_FIFOEN */
231 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
232 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
233 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
234 #if defined(USART_CR1_FIFOEN)
235 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
236 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
237 #endif /* USART_CR1_FIFOEN */
238 /**
239 * @}
240 */
241 #if defined(USART_CR1_FIFOEN)
242
243 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
244 * @{
245 */
246 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
247 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
248 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
249 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
250 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
251 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
252 /**
253 * @}
254 */
255 #endif /* USART_CR1_FIFOEN */
256
257 /** @defgroup LPUART_LL_EC_DIRECTION Direction
258 * @{
259 */
260 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
261 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
262 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
263 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
264 /**
265 * @}
266 */
267
268 /** @defgroup LPUART_LL_EC_PARITY Parity Control
269 * @{
270 */
271 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
272 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
273 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
274 /**
275 * @}
276 */
277
278 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
279 * @{
280 */
281 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
282 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
283 /**
284 * @}
285 */
286
287 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
288 * @{
289 */
290 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
291 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
292 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
293 /**
294 * @}
295 */
296 #if defined(USART_PRESC_PRESCALER)
297
298 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
299 * @{
300 */
301 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
302 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
303 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
304 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
305 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
306 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
307 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
308 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
309 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
310 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
311 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
312 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
313 /**
314 * @}
315 */
316 #endif /* USART_PRESC_PRESCALER */
317
318 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
319 * @{
320 */
321 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
322 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
323 /**
324 * @}
325 */
326
327 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
328 * @{
329 */
330 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
331 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
332 /**
333 * @}
334 */
335
336 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
337 * @{
338 */
339 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
340 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
341 /**
342 * @}
343 */
344
345 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
346 * @{
347 */
348 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
349 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
350 /**
351 * @}
352 */
353
354 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
355 * @{
356 */
357 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
358 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
359 /**
360 * @}
361 */
362
363 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
364 * @{
365 */
366 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
367 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
368 /**
369 * @}
370 */
371
372 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
373 * @{
374 */
375 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
376 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
377 /**
378 * @}
379 */
380
381 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
382 * @{
383 */
384 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
385 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
386 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
387 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
388 /**
389 * @}
390 */
391
392 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
393 * @{
394 */
395 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
396 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
397 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
398 /**
399 * @}
400 */
401
402 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
403 * @{
404 */
405 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
406 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
407 /**
408 * @}
409 */
410
411 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
412 * @{
413 */
414 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
415 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
416 /**
417 * @}
418 */
419
420 /**
421 * @}
422 */
423
424 /* Exported macro ------------------------------------------------------------*/
425 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
426 * @{
427 */
428
429 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
430 * @{
431 */
432
433 /**
434 * @brief Write a value in LPUART register
435 * @param __INSTANCE__ LPUART Instance
436 * @param __REG__ Register to be written
437 * @param __VALUE__ Value to be written in the register
438 * @retval None
439 */
440 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
441
442 /**
443 * @brief Read a value in LPUART register
444 * @param __INSTANCE__ LPUART Instance
445 * @param __REG__ Register to be read
446 * @retval Register value
447 */
448 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
449 /**
450 * @}
451 */
452
453 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
454 * @{
455 */
456
457 /**
458 * @brief Compute LPUARTDIV value according to Peripheral Clock and
459 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
460 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
461 @if USART_PRESC_PRESCALER
462 * @param __PRESCALER__ This parameter can be one of the following values:
463 * @arg @ref LL_LPUART_PRESCALER_DIV1
464 * @arg @ref LL_LPUART_PRESCALER_DIV2
465 * @arg @ref LL_LPUART_PRESCALER_DIV4
466 * @arg @ref LL_LPUART_PRESCALER_DIV6
467 * @arg @ref LL_LPUART_PRESCALER_DIV8
468 * @arg @ref LL_LPUART_PRESCALER_DIV10
469 * @arg @ref LL_LPUART_PRESCALER_DIV12
470 * @arg @ref LL_LPUART_PRESCALER_DIV16
471 * @arg @ref LL_LPUART_PRESCALER_DIV32
472 * @arg @ref LL_LPUART_PRESCALER_DIV64
473 * @arg @ref LL_LPUART_PRESCALER_DIV128
474 * @arg @ref LL_LPUART_PRESCALER_DIV256
475 @endif
476 * @param __BAUDRATE__ Baud Rate value to achieve
477 * @retval LPUARTDIV value to be used for BRR register filling
478 */
479 #if defined(USART_PRESC_PRESCALER)
480 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
481 + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
482 #else
483 #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)(((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__))\
484 & LPUART_BRR_MASK)
485 #endif /* USART_PRESC_PRESCALER */
486
487 /**
488 * @}
489 */
490
491 /**
492 * @}
493 */
494
495 /* Exported functions --------------------------------------------------------*/
496 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
497 * @{
498 */
499
500 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
501 * @{
502 */
503
504 /**
505 * @brief LPUART Enable
506 * @rmtoll CR1 UE LL_LPUART_Enable
507 * @param LPUARTx LPUART Instance
508 * @retval None
509 */
LL_LPUART_Enable(USART_TypeDef * LPUARTx)510 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
511 {
512 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
513 }
514
515 /**
516 * @brief LPUART Disable
517 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
518 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
519 * flags, in the LPUARTx_ISR are set to their default values.
520 * @note In order to go into low-power mode without generating errors on the line,
521 * the TE bit must be reset before and the software must wait
522 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
523 * The DMA requests are also reset when UE = 0 so the DMA channel must
524 * be disabled before resetting the UE bit.
525 * @rmtoll CR1 UE LL_LPUART_Disable
526 * @param LPUARTx LPUART Instance
527 * @retval None
528 */
LL_LPUART_Disable(USART_TypeDef * LPUARTx)529 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
530 {
531 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
532 }
533
534 /**
535 * @brief Indicate if LPUART is enabled
536 * @rmtoll CR1 UE LL_LPUART_IsEnabled
537 * @param LPUARTx LPUART Instance
538 * @retval State of bit (1 or 0).
539 */
LL_LPUART_IsEnabled(USART_TypeDef * LPUARTx)540 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
541 {
542 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
543 }
544
545 #if defined(USART_CR1_FIFOEN)
546 /**
547 * @brief FIFO Mode Enable
548 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
549 * @param LPUARTx LPUART Instance
550 * @retval None
551 */
LL_LPUART_EnableFIFO(USART_TypeDef * LPUARTx)552 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
553 {
554 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
555 }
556
557 /**
558 * @brief FIFO Mode Disable
559 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
560 * @param LPUARTx LPUART Instance
561 * @retval None
562 */
LL_LPUART_DisableFIFO(USART_TypeDef * LPUARTx)563 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
564 {
565 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
566 }
567
568 /**
569 * @brief Indicate if FIFO Mode is enabled
570 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
571 * @param LPUARTx LPUART Instance
572 * @retval State of bit (1 or 0).
573 */
LL_LPUART_IsEnabledFIFO(USART_TypeDef * LPUARTx)574 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
575 {
576 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
577 }
578
579 /**
580 * @brief Configure TX FIFO Threshold
581 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
582 * @param LPUARTx LPUART Instance
583 * @param Threshold This parameter can be one of the following values:
584 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
585 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
586 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
587 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
588 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
589 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
590 * @retval None
591 */
LL_LPUART_SetTXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)592 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
593 {
594 MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
595 }
596
597 /**
598 * @brief Return TX FIFO Threshold Configuration
599 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
600 * @param LPUARTx LPUART Instance
601 * @retval Returned value can be one of the following values:
602 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
603 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
604 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
605 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
606 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
607 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
608 */
LL_LPUART_GetTXFIFOThreshold(USART_TypeDef * LPUARTx)609 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
610 {
611 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
612 }
613
614 /**
615 * @brief Configure RX FIFO Threshold
616 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
617 * @param LPUARTx LPUART Instance
618 * @param Threshold This parameter can be one of the following values:
619 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
620 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
621 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
622 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
623 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
624 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
625 * @retval None
626 */
LL_LPUART_SetRXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)627 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
628 {
629 MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
630 }
631
632 /**
633 * @brief Return RX FIFO Threshold Configuration
634 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
635 * @param LPUARTx LPUART Instance
636 * @retval Returned value can be one of the following values:
637 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
638 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
639 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
640 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
641 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
642 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
643 */
LL_LPUART_GetRXFIFOThreshold(USART_TypeDef * LPUARTx)644 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
645 {
646 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
647 }
648
649 /**
650 * @brief Configure TX and RX FIFOs Threshold
651 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
652 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
653 * @param LPUARTx LPUART Instance
654 * @param TXThreshold This parameter can be one of the following values:
655 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
656 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
657 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
658 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
659 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
660 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
661 * @param RXThreshold This parameter can be one of the following values:
662 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
663 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
664 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
665 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
666 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
667 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
668 * @retval None
669 */
LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef * LPUARTx,uint32_t TXThreshold,uint32_t RXThreshold)670 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
671 {
672 MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
673 }
674 #endif /* USART_CR1_FIFOEN */
675
676 /**
677 * @brief LPUART enabled in STOP Mode
678 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
679 * LPUART clock selection is HSI or LSE in RCC.
680 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
681 * @param LPUARTx LPUART Instance
682 * @retval None
683 */
LL_LPUART_EnableInStopMode(USART_TypeDef * LPUARTx)684 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
685 {
686 SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
687 }
688
689 /**
690 * @brief LPUART disabled in STOP Mode
691 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
692 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
693 * @param LPUARTx LPUART Instance
694 * @retval None
695 */
LL_LPUART_DisableInStopMode(USART_TypeDef * LPUARTx)696 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
697 {
698 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
699 }
700
701 /**
702 * @brief Indicate if LPUART is enabled in STOP Mode
703 * (able to wake up MCU from Stop mode or not)
704 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
705 * @param LPUARTx LPUART Instance
706 * @retval State of bit (1 or 0).
707 */
LL_LPUART_IsEnabledInStopMode(USART_TypeDef * LPUARTx)708 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
709 {
710 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
711 }
712
713 #if defined(USART_CR3_UCESM)
714 /**
715 * @brief LPUART Clock enabled in STOP Mode
716 * @note When this function is called, LPUART Clock is enabled while in STOP mode
717 * @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode
718 * @param LPUARTx LPUART Instance
719 * @retval None
720 */
LL_LPUART_EnableClockInStopMode(USART_TypeDef * LPUARTx)721 __STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx)
722 {
723 SET_BIT(LPUARTx->CR3, USART_CR3_UCESM);
724 }
725
726 /**
727 * @brief LPUART clock disabled in STOP Mode
728 * @note When this function is called, LPUART Clock is disabled while in STOP mode
729 * @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode
730 * @param LPUARTx LPUART Instance
731 * @retval None
732 */
LL_LPUART_DisableClockInStopMode(USART_TypeDef * LPUARTx)733 __STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx)
734 {
735 CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM);
736 }
737
738 /**
739 * @brief Indicate if LPUART clock is enabled in STOP Mode
740 * @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode
741 * @param LPUARTx LPUART Instance
742 * @retval State of bit (1 or 0).
743 */
LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef * LPUARTx)744 __STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef *LPUARTx)
745 {
746 return ((READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)) ? 1UL : 0UL);
747 }
748
749 #endif /* USART_CR3_UCESM */
750 /**
751 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
752 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
753 * @param LPUARTx LPUART Instance
754 * @retval None
755 */
LL_LPUART_EnableDirectionRx(USART_TypeDef * LPUARTx)756 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
757 {
758 SET_BIT(LPUARTx->CR1, USART_CR1_RE);
759 }
760
761 /**
762 * @brief Receiver Disable
763 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
764 * @param LPUARTx LPUART Instance
765 * @retval None
766 */
LL_LPUART_DisableDirectionRx(USART_TypeDef * LPUARTx)767 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
768 {
769 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
770 }
771
772 /**
773 * @brief Transmitter Enable
774 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
775 * @param LPUARTx LPUART Instance
776 * @retval None
777 */
LL_LPUART_EnableDirectionTx(USART_TypeDef * LPUARTx)778 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
779 {
780 SET_BIT(LPUARTx->CR1, USART_CR1_TE);
781 }
782
783 /**
784 * @brief Transmitter Disable
785 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
786 * @param LPUARTx LPUART Instance
787 * @retval None
788 */
LL_LPUART_DisableDirectionTx(USART_TypeDef * LPUARTx)789 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
790 {
791 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
792 }
793
794 /**
795 * @brief Configure simultaneously enabled/disabled states
796 * of Transmitter and Receiver
797 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
798 * CR1 TE LL_LPUART_SetTransferDirection
799 * @param LPUARTx LPUART Instance
800 * @param TransferDirection This parameter can be one of the following values:
801 * @arg @ref LL_LPUART_DIRECTION_NONE
802 * @arg @ref LL_LPUART_DIRECTION_RX
803 * @arg @ref LL_LPUART_DIRECTION_TX
804 * @arg @ref LL_LPUART_DIRECTION_TX_RX
805 * @retval None
806 */
LL_LPUART_SetTransferDirection(USART_TypeDef * LPUARTx,uint32_t TransferDirection)807 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
808 {
809 MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
810 }
811
812 /**
813 * @brief Return enabled/disabled states of Transmitter and Receiver
814 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
815 * CR1 TE LL_LPUART_GetTransferDirection
816 * @param LPUARTx LPUART Instance
817 * @retval Returned value can be one of the following values:
818 * @arg @ref LL_LPUART_DIRECTION_NONE
819 * @arg @ref LL_LPUART_DIRECTION_RX
820 * @arg @ref LL_LPUART_DIRECTION_TX
821 * @arg @ref LL_LPUART_DIRECTION_TX_RX
822 */
LL_LPUART_GetTransferDirection(USART_TypeDef * LPUARTx)823 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
824 {
825 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
826 }
827
828 /**
829 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
830 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
831 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
832 * (depending on data width) and parity is checked on the received data.
833 * @rmtoll CR1 PS LL_LPUART_SetParity\n
834 * CR1 PCE LL_LPUART_SetParity
835 * @param LPUARTx LPUART Instance
836 * @param Parity This parameter can be one of the following values:
837 * @arg @ref LL_LPUART_PARITY_NONE
838 * @arg @ref LL_LPUART_PARITY_EVEN
839 * @arg @ref LL_LPUART_PARITY_ODD
840 * @retval None
841 */
LL_LPUART_SetParity(USART_TypeDef * LPUARTx,uint32_t Parity)842 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
843 {
844 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
845 }
846
847 /**
848 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
849 * @rmtoll CR1 PS LL_LPUART_GetParity\n
850 * CR1 PCE LL_LPUART_GetParity
851 * @param LPUARTx LPUART Instance
852 * @retval Returned value can be one of the following values:
853 * @arg @ref LL_LPUART_PARITY_NONE
854 * @arg @ref LL_LPUART_PARITY_EVEN
855 * @arg @ref LL_LPUART_PARITY_ODD
856 */
LL_LPUART_GetParity(USART_TypeDef * LPUARTx)857 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
858 {
859 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
860 }
861
862 /**
863 * @brief Set Receiver Wake Up method from Mute mode.
864 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
865 * @param LPUARTx LPUART Instance
866 * @param Method This parameter can be one of the following values:
867 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
868 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
869 * @retval None
870 */
LL_LPUART_SetWakeUpMethod(USART_TypeDef * LPUARTx,uint32_t Method)871 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
872 {
873 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
874 }
875
876 /**
877 * @brief Return Receiver Wake Up method from Mute mode
878 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
879 * @param LPUARTx LPUART Instance
880 * @retval Returned value can be one of the following values:
881 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
882 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
883 */
LL_LPUART_GetWakeUpMethod(USART_TypeDef * LPUARTx)884 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
885 {
886 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
887 }
888
889 /**
890 * @brief Set Word length (nb of data bits, excluding start and stop bits)
891 * @rmtoll CR1 M LL_LPUART_SetDataWidth
892 * @param LPUARTx LPUART Instance
893 * @param DataWidth This parameter can be one of the following values:
894 * @arg @ref LL_LPUART_DATAWIDTH_7B
895 * @arg @ref LL_LPUART_DATAWIDTH_8B
896 * @arg @ref LL_LPUART_DATAWIDTH_9B
897 * @retval None
898 */
LL_LPUART_SetDataWidth(USART_TypeDef * LPUARTx,uint32_t DataWidth)899 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
900 {
901 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
902 }
903
904 /**
905 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
906 * @rmtoll CR1 M LL_LPUART_GetDataWidth
907 * @param LPUARTx LPUART Instance
908 * @retval Returned value can be one of the following values:
909 * @arg @ref LL_LPUART_DATAWIDTH_7B
910 * @arg @ref LL_LPUART_DATAWIDTH_8B
911 * @arg @ref LL_LPUART_DATAWIDTH_9B
912 */
LL_LPUART_GetDataWidth(USART_TypeDef * LPUARTx)913 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
914 {
915 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
916 }
917
918 /**
919 * @brief Allow switch between Mute Mode and Active mode
920 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
921 * @param LPUARTx LPUART Instance
922 * @retval None
923 */
LL_LPUART_EnableMuteMode(USART_TypeDef * LPUARTx)924 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
925 {
926 SET_BIT(LPUARTx->CR1, USART_CR1_MME);
927 }
928
929 /**
930 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
931 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
932 * @param LPUARTx LPUART Instance
933 * @retval None
934 */
LL_LPUART_DisableMuteMode(USART_TypeDef * LPUARTx)935 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
936 {
937 CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
938 }
939
940 /**
941 * @brief Indicate if switch between Mute Mode and Active mode is allowed
942 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
943 * @param LPUARTx LPUART Instance
944 * @retval State of bit (1 or 0).
945 */
LL_LPUART_IsEnabledMuteMode(USART_TypeDef * LPUARTx)946 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
947 {
948 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
949 }
950
951 #if defined(USART_PRESC_PRESCALER)
952 /**
953 * @brief Configure Clock source prescaler for baudrate generator and oversampling
954 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
955 * @param LPUARTx LPUART Instance
956 * @param PrescalerValue This parameter can be one of the following values:
957 * @arg @ref LL_LPUART_PRESCALER_DIV1
958 * @arg @ref LL_LPUART_PRESCALER_DIV2
959 * @arg @ref LL_LPUART_PRESCALER_DIV4
960 * @arg @ref LL_LPUART_PRESCALER_DIV6
961 * @arg @ref LL_LPUART_PRESCALER_DIV8
962 * @arg @ref LL_LPUART_PRESCALER_DIV10
963 * @arg @ref LL_LPUART_PRESCALER_DIV12
964 * @arg @ref LL_LPUART_PRESCALER_DIV16
965 * @arg @ref LL_LPUART_PRESCALER_DIV32
966 * @arg @ref LL_LPUART_PRESCALER_DIV64
967 * @arg @ref LL_LPUART_PRESCALER_DIV128
968 * @arg @ref LL_LPUART_PRESCALER_DIV256
969 * @retval None
970 */
LL_LPUART_SetPrescaler(USART_TypeDef * LPUARTx,uint32_t PrescalerValue)971 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
972 {
973 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
974 }
975
976 /**
977 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
978 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
979 * @param LPUARTx LPUART Instance
980 * @retval Returned value can be one of the following values:
981 * @arg @ref LL_LPUART_PRESCALER_DIV1
982 * @arg @ref LL_LPUART_PRESCALER_DIV2
983 * @arg @ref LL_LPUART_PRESCALER_DIV4
984 * @arg @ref LL_LPUART_PRESCALER_DIV6
985 * @arg @ref LL_LPUART_PRESCALER_DIV8
986 * @arg @ref LL_LPUART_PRESCALER_DIV10
987 * @arg @ref LL_LPUART_PRESCALER_DIV12
988 * @arg @ref LL_LPUART_PRESCALER_DIV16
989 * @arg @ref LL_LPUART_PRESCALER_DIV32
990 * @arg @ref LL_LPUART_PRESCALER_DIV64
991 * @arg @ref LL_LPUART_PRESCALER_DIV128
992 * @arg @ref LL_LPUART_PRESCALER_DIV256
993 */
LL_LPUART_GetPrescaler(USART_TypeDef * LPUARTx)994 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
995 {
996 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
997 }
998 #endif /* USART_PRESC_PRESCALER */
999
1000 /**
1001 * @brief Set the length of the stop bits
1002 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
1003 * @param LPUARTx LPUART Instance
1004 * @param StopBits This parameter can be one of the following values:
1005 * @arg @ref LL_LPUART_STOPBITS_1
1006 * @arg @ref LL_LPUART_STOPBITS_2
1007 * @retval None
1008 */
LL_LPUART_SetStopBitsLength(USART_TypeDef * LPUARTx,uint32_t StopBits)1009 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
1010 {
1011 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1012 }
1013
1014 /**
1015 * @brief Retrieve the length of the stop bits
1016 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
1017 * @param LPUARTx LPUART Instance
1018 * @retval Returned value can be one of the following values:
1019 * @arg @ref LL_LPUART_STOPBITS_1
1020 * @arg @ref LL_LPUART_STOPBITS_2
1021 */
LL_LPUART_GetStopBitsLength(USART_TypeDef * LPUARTx)1022 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
1023 {
1024 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
1025 }
1026
1027 /**
1028 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
1029 * @note Call of this function is equivalent to following function call sequence :
1030 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
1031 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
1032 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
1033 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
1034 * CR1 PCE LL_LPUART_ConfigCharacter\n
1035 * CR1 M LL_LPUART_ConfigCharacter\n
1036 * CR2 STOP LL_LPUART_ConfigCharacter
1037 * @param LPUARTx LPUART Instance
1038 * @param DataWidth This parameter can be one of the following values:
1039 * @arg @ref LL_LPUART_DATAWIDTH_7B
1040 * @arg @ref LL_LPUART_DATAWIDTH_8B
1041 * @arg @ref LL_LPUART_DATAWIDTH_9B
1042 * @param Parity This parameter can be one of the following values:
1043 * @arg @ref LL_LPUART_PARITY_NONE
1044 * @arg @ref LL_LPUART_PARITY_EVEN
1045 * @arg @ref LL_LPUART_PARITY_ODD
1046 * @param StopBits This parameter can be one of the following values:
1047 * @arg @ref LL_LPUART_STOPBITS_1
1048 * @arg @ref LL_LPUART_STOPBITS_2
1049 * @retval None
1050 */
LL_LPUART_ConfigCharacter(USART_TypeDef * LPUARTx,uint32_t DataWidth,uint32_t Parity,uint32_t StopBits)1051 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
1052 uint32_t StopBits)
1053 {
1054 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1055 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1056 }
1057
1058 /**
1059 * @brief Configure TX/RX pins swapping setting.
1060 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
1061 * @param LPUARTx LPUART Instance
1062 * @param SwapConfig This parameter can be one of the following values:
1063 * @arg @ref LL_LPUART_TXRX_STANDARD
1064 * @arg @ref LL_LPUART_TXRX_SWAPPED
1065 * @retval None
1066 */
LL_LPUART_SetTXRXSwap(USART_TypeDef * LPUARTx,uint32_t SwapConfig)1067 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1068 {
1069 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1070 }
1071
1072 /**
1073 * @brief Retrieve TX/RX pins swapping configuration.
1074 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
1075 * @param LPUARTx LPUART Instance
1076 * @retval Returned value can be one of the following values:
1077 * @arg @ref LL_LPUART_TXRX_STANDARD
1078 * @arg @ref LL_LPUART_TXRX_SWAPPED
1079 */
LL_LPUART_GetTXRXSwap(USART_TypeDef * LPUARTx)1080 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
1081 {
1082 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1083 }
1084
1085 /**
1086 * @brief Configure RX pin active level logic
1087 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1088 * @param LPUARTx LPUART Instance
1089 * @param PinInvMethod This parameter can be one of the following values:
1090 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1091 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1092 * @retval None
1093 */
LL_LPUART_SetRXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1094 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1095 {
1096 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1097 }
1098
1099 /**
1100 * @brief Retrieve RX pin active level logic configuration
1101 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1102 * @param LPUARTx LPUART Instance
1103 * @retval Returned value can be one of the following values:
1104 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1105 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1106 */
LL_LPUART_GetRXPinLevel(USART_TypeDef * LPUARTx)1107 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
1108 {
1109 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1110 }
1111
1112 /**
1113 * @brief Configure TX pin active level logic
1114 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1115 * @param LPUARTx LPUART Instance
1116 * @param PinInvMethod This parameter can be one of the following values:
1117 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1118 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1119 * @retval None
1120 */
LL_LPUART_SetTXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1121 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1122 {
1123 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1124 }
1125
1126 /**
1127 * @brief Retrieve TX pin active level logic configuration
1128 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1129 * @param LPUARTx LPUART Instance
1130 * @retval Returned value can be one of the following values:
1131 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1132 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1133 */
LL_LPUART_GetTXPinLevel(USART_TypeDef * LPUARTx)1134 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
1135 {
1136 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1137 }
1138
1139 /**
1140 * @brief Configure Binary data logic.
1141 *
1142 * @note Allow to define how Logical data from the data register are send/received :
1143 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1144 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1145 * @param LPUARTx LPUART Instance
1146 * @param DataLogic This parameter can be one of the following values:
1147 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1148 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1149 * @retval None
1150 */
LL_LPUART_SetBinaryDataLogic(USART_TypeDef * LPUARTx,uint32_t DataLogic)1151 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1152 {
1153 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1154 }
1155
1156 /**
1157 * @brief Retrieve Binary data configuration
1158 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1159 * @param LPUARTx LPUART Instance
1160 * @retval Returned value can be one of the following values:
1161 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1162 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1163 */
LL_LPUART_GetBinaryDataLogic(USART_TypeDef * LPUARTx)1164 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
1165 {
1166 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1167 }
1168
1169 /**
1170 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1171 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1172 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1173 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1174 * @param LPUARTx LPUART Instance
1175 * @param BitOrder This parameter can be one of the following values:
1176 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1177 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1178 * @retval None
1179 */
LL_LPUART_SetTransferBitOrder(USART_TypeDef * LPUARTx,uint32_t BitOrder)1180 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1181 {
1182 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1183 }
1184
1185 /**
1186 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1187 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1188 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1189 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1190 * @param LPUARTx LPUART Instance
1191 * @retval Returned value can be one of the following values:
1192 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1193 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1194 */
LL_LPUART_GetTransferBitOrder(USART_TypeDef * LPUARTx)1195 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
1196 {
1197 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1198 }
1199
1200 /**
1201 * @brief Set Address of the LPUART node.
1202 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1203 * for wake up with address mark detection.
1204 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1205 * (b7-b4 should be set to 0)
1206 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1207 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1208 * for wake up with 7-bit address mark detection.
1209 * The MSB of the character sent by the transmitter should be equal to 1.
1210 * It may also be used for character detection during normal reception,
1211 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1212 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1213 * value and CMF flag is set on match)
1214 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1215 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1216 * @param LPUARTx LPUART Instance
1217 * @param AddressLen This parameter can be one of the following values:
1218 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1219 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1220 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1221 * @retval None
1222 */
LL_LPUART_ConfigNodeAddress(USART_TypeDef * LPUARTx,uint32_t AddressLen,uint32_t NodeAddress)1223 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1224 {
1225 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1226 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1227 }
1228
1229 /**
1230 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1231 * @note If 4-bit Address Detection is selected in ADDM7,
1232 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1233 * If 7-bit Address Detection is selected in ADDM7,
1234 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1235 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1236 * @param LPUARTx LPUART Instance
1237 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1238 */
LL_LPUART_GetNodeAddress(USART_TypeDef * LPUARTx)1239 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
1240 {
1241 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1242 }
1243
1244 /**
1245 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1246 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1247 * @param LPUARTx LPUART Instance
1248 * @retval Returned value can be one of the following values:
1249 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1250 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1251 */
LL_LPUART_GetNodeAddressLen(USART_TypeDef * LPUARTx)1252 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
1253 {
1254 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1255 }
1256
1257 /**
1258 * @brief Enable RTS HW Flow Control
1259 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1260 * @param LPUARTx LPUART Instance
1261 * @retval None
1262 */
LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1263 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1264 {
1265 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1266 }
1267
1268 /**
1269 * @brief Disable RTS HW Flow Control
1270 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1271 * @param LPUARTx LPUART Instance
1272 * @retval None
1273 */
LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1274 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1275 {
1276 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1277 }
1278
1279 /**
1280 * @brief Enable CTS HW Flow Control
1281 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1282 * @param LPUARTx LPUART Instance
1283 * @retval None
1284 */
LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1285 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1286 {
1287 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1288 }
1289
1290 /**
1291 * @brief Disable CTS HW Flow Control
1292 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1293 * @param LPUARTx LPUART Instance
1294 * @retval None
1295 */
LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1296 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1297 {
1298 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1299 }
1300
1301 /**
1302 * @brief Configure HW Flow Control mode (both CTS and RTS)
1303 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1304 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1305 * @param LPUARTx LPUART Instance
1306 * @param HardwareFlowControl This parameter can be one of the following values:
1307 * @arg @ref LL_LPUART_HWCONTROL_NONE
1308 * @arg @ref LL_LPUART_HWCONTROL_RTS
1309 * @arg @ref LL_LPUART_HWCONTROL_CTS
1310 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1311 * @retval None
1312 */
LL_LPUART_SetHWFlowCtrl(USART_TypeDef * LPUARTx,uint32_t HardwareFlowControl)1313 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1314 {
1315 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1316 }
1317
1318 /**
1319 * @brief Return HW Flow Control configuration (both CTS and RTS)
1320 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1321 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1322 * @param LPUARTx LPUART Instance
1323 * @retval Returned value can be one of the following values:
1324 * @arg @ref LL_LPUART_HWCONTROL_NONE
1325 * @arg @ref LL_LPUART_HWCONTROL_RTS
1326 * @arg @ref LL_LPUART_HWCONTROL_CTS
1327 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1328 */
LL_LPUART_GetHWFlowCtrl(USART_TypeDef * LPUARTx)1329 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
1330 {
1331 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1332 }
1333
1334 /**
1335 * @brief Enable Overrun detection
1336 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1337 * @param LPUARTx LPUART Instance
1338 * @retval None
1339 */
LL_LPUART_EnableOverrunDetect(USART_TypeDef * LPUARTx)1340 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1341 {
1342 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1343 }
1344
1345 /**
1346 * @brief Disable Overrun detection
1347 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1348 * @param LPUARTx LPUART Instance
1349 * @retval None
1350 */
LL_LPUART_DisableOverrunDetect(USART_TypeDef * LPUARTx)1351 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1352 {
1353 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1354 }
1355
1356 /**
1357 * @brief Indicate if Overrun detection is enabled
1358 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1359 * @param LPUARTx LPUART Instance
1360 * @retval State of bit (1 or 0).
1361 */
LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef * LPUARTx)1362 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
1363 {
1364 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1365 }
1366
1367 /**
1368 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1369 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1370 * @param LPUARTx LPUART Instance
1371 * @param Type This parameter can be one of the following values:
1372 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1373 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1374 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1375 * @retval None
1376 */
LL_LPUART_SetWKUPType(USART_TypeDef * LPUARTx,uint32_t Type)1377 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1378 {
1379 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1380 }
1381
1382 /**
1383 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1384 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1385 * @param LPUARTx LPUART Instance
1386 * @retval Returned value can be one of the following values:
1387 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1388 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1389 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1390 */
LL_LPUART_GetWKUPType(USART_TypeDef * LPUARTx)1391 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
1392 {
1393 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1394 }
1395
1396 /**
1397 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1398 *
1399 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1400 * according to used Peripheral Clock and expected Baud Rate values
1401 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1402 * (Baud rate value != 0).
1403 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1404 * a care should be taken when generating high baud rates using high PeriphClk
1405 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1406 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1407 * @param LPUARTx LPUART Instance
1408 * @param PeriphClk Peripheral Clock
1409 @if USART_PRESC_PRESCALER
1410 * @param PrescalerValue This parameter can be one of the following values:
1411 * @arg @ref LL_LPUART_PRESCALER_DIV1
1412 * @arg @ref LL_LPUART_PRESCALER_DIV2
1413 * @arg @ref LL_LPUART_PRESCALER_DIV4
1414 * @arg @ref LL_LPUART_PRESCALER_DIV6
1415 * @arg @ref LL_LPUART_PRESCALER_DIV8
1416 * @arg @ref LL_LPUART_PRESCALER_DIV10
1417 * @arg @ref LL_LPUART_PRESCALER_DIV12
1418 * @arg @ref LL_LPUART_PRESCALER_DIV16
1419 * @arg @ref LL_LPUART_PRESCALER_DIV32
1420 * @arg @ref LL_LPUART_PRESCALER_DIV64
1421 * @arg @ref LL_LPUART_PRESCALER_DIV128
1422 * @arg @ref LL_LPUART_PRESCALER_DIV256
1423 @endif
1424 * @param BaudRate Baud Rate
1425 * @retval None
1426 */
1427 #if defined(USART_PRESC_PRESCALER)
LL_LPUART_SetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue,uint32_t BaudRate)1428 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1429 uint32_t BaudRate)
1430 #else
1431 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
1432 #endif /* USART_PRESC_PRESCALER */
1433 {
1434 #if defined(USART_PRESC_PRESCALER)
1435 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1436 #else
1437 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
1438 #endif /* USART_PRESC_PRESCALER */
1439 }
1440
1441 /**
1442 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1443 * (full BRR content), and to used Peripheral Clock values
1444 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1445 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1446 * @param LPUARTx LPUART Instance
1447 * @param PeriphClk Peripheral Clock
1448 @if USART_PRESC_PRESCALER
1449 * @param PrescalerValue This parameter can be one of the following values:
1450 * @arg @ref LL_LPUART_PRESCALER_DIV1
1451 * @arg @ref LL_LPUART_PRESCALER_DIV2
1452 * @arg @ref LL_LPUART_PRESCALER_DIV4
1453 * @arg @ref LL_LPUART_PRESCALER_DIV6
1454 * @arg @ref LL_LPUART_PRESCALER_DIV8
1455 * @arg @ref LL_LPUART_PRESCALER_DIV10
1456 * @arg @ref LL_LPUART_PRESCALER_DIV12
1457 * @arg @ref LL_LPUART_PRESCALER_DIV16
1458 * @arg @ref LL_LPUART_PRESCALER_DIV32
1459 * @arg @ref LL_LPUART_PRESCALER_DIV64
1460 * @arg @ref LL_LPUART_PRESCALER_DIV128
1461 * @arg @ref LL_LPUART_PRESCALER_DIV256
1462 @endif
1463 * @retval Baud Rate
1464 */
1465 #if defined(USART_PRESC_PRESCALER)
LL_LPUART_GetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue)1466 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
1467 #else
1468 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
1469 #endif /* USART_PRESC_PRESCALER */
1470 {
1471 register uint32_t lpuartdiv;
1472 register uint32_t brrresult;
1473 #if defined(USART_PRESC_PRESCALER)
1474 register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1475 #endif /* USART_PRESC_PRESCALER */
1476
1477 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1478
1479 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1480 {
1481 #if defined(USART_PRESC_PRESCALER)
1482 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1483 #else
1484 brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1485 #endif /* USART_PRESC_PRESCALER */
1486 }
1487 else
1488 {
1489 brrresult = 0x0UL;
1490 }
1491
1492 return (brrresult);
1493 }
1494
1495 /**
1496 * @}
1497 */
1498
1499 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1500 * @{
1501 */
1502
1503 /**
1504 * @brief Enable Single Wire Half-Duplex mode
1505 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1506 * @param LPUARTx LPUART Instance
1507 * @retval None
1508 */
LL_LPUART_EnableHalfDuplex(USART_TypeDef * LPUARTx)1509 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1510 {
1511 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1512 }
1513
1514 /**
1515 * @brief Disable Single Wire Half-Duplex mode
1516 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1517 * @param LPUARTx LPUART Instance
1518 * @retval None
1519 */
LL_LPUART_DisableHalfDuplex(USART_TypeDef * LPUARTx)1520 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1521 {
1522 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1523 }
1524
1525 /**
1526 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1527 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1528 * @param LPUARTx LPUART Instance
1529 * @retval State of bit (1 or 0).
1530 */
LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef * LPUARTx)1531 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
1532 {
1533 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1534 }
1535
1536 /**
1537 * @}
1538 */
1539
1540 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1541 * @{
1542 */
1543
1544 /**
1545 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1546 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1547 * @param LPUARTx LPUART Instance
1548 * @param Time Value between Min_Data=0 and Max_Data=31
1549 * @retval None
1550 */
LL_LPUART_SetDEDeassertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1551 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1552 {
1553 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1554 }
1555
1556 /**
1557 * @brief Return DEDT (Driver Enable De-Assertion Time)
1558 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1559 * @param LPUARTx LPUART Instance
1560 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1561 */
LL_LPUART_GetDEDeassertionTime(USART_TypeDef * LPUARTx)1562 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
1563 {
1564 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1565 }
1566
1567 /**
1568 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1569 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1570 * @param LPUARTx LPUART Instance
1571 * @param Time Value between Min_Data=0 and Max_Data=31
1572 * @retval None
1573 */
LL_LPUART_SetDEAssertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1574 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1575 {
1576 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1577 }
1578
1579 /**
1580 * @brief Return DEAT (Driver Enable Assertion Time)
1581 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1582 * @param LPUARTx LPUART Instance
1583 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1584 */
LL_LPUART_GetDEAssertionTime(USART_TypeDef * LPUARTx)1585 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
1586 {
1587 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1588 }
1589
1590 /**
1591 * @brief Enable Driver Enable (DE) Mode
1592 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1593 * @param LPUARTx LPUART Instance
1594 * @retval None
1595 */
LL_LPUART_EnableDEMode(USART_TypeDef * LPUARTx)1596 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1597 {
1598 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1599 }
1600
1601 /**
1602 * @brief Disable Driver Enable (DE) Mode
1603 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1604 * @param LPUARTx LPUART Instance
1605 * @retval None
1606 */
LL_LPUART_DisableDEMode(USART_TypeDef * LPUARTx)1607 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1608 {
1609 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1610 }
1611
1612 /**
1613 * @brief Indicate if Driver Enable (DE) Mode is enabled
1614 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1615 * @param LPUARTx LPUART Instance
1616 * @retval State of bit (1 or 0).
1617 */
LL_LPUART_IsEnabledDEMode(USART_TypeDef * LPUARTx)1618 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
1619 {
1620 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1621 }
1622
1623 /**
1624 * @brief Select Driver Enable Polarity
1625 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1626 * @param LPUARTx LPUART Instance
1627 * @param Polarity This parameter can be one of the following values:
1628 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1629 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1630 * @retval None
1631 */
LL_LPUART_SetDESignalPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)1632 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1633 {
1634 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1635 }
1636
1637 /**
1638 * @brief Return Driver Enable Polarity
1639 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1640 * @param LPUARTx LPUART Instance
1641 * @retval Returned value can be one of the following values:
1642 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1643 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1644 */
LL_LPUART_GetDESignalPolarity(USART_TypeDef * LPUARTx)1645 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
1646 {
1647 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1648 }
1649
1650 /**
1651 * @}
1652 */
1653
1654 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1655 * @{
1656 */
1657
1658 /**
1659 * @brief Check if the LPUART Parity Error Flag is set or not
1660 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1661 * @param LPUARTx LPUART Instance
1662 * @retval State of bit (1 or 0).
1663 */
LL_LPUART_IsActiveFlag_PE(USART_TypeDef * LPUARTx)1664 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
1665 {
1666 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1667 }
1668
1669 /**
1670 * @brief Check if the LPUART Framing Error Flag is set or not
1671 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1672 * @param LPUARTx LPUART Instance
1673 * @retval State of bit (1 or 0).
1674 */
LL_LPUART_IsActiveFlag_FE(USART_TypeDef * LPUARTx)1675 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
1676 {
1677 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1678 }
1679
1680 /**
1681 * @brief Check if the LPUART Noise error detected Flag is set or not
1682 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1683 * @param LPUARTx LPUART Instance
1684 * @retval State of bit (1 or 0).
1685 */
LL_LPUART_IsActiveFlag_NE(USART_TypeDef * LPUARTx)1686 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
1687 {
1688 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1689 }
1690
1691 /**
1692 * @brief Check if the LPUART OverRun Error Flag is set or not
1693 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1694 * @param LPUARTx LPUART Instance
1695 * @retval State of bit (1 or 0).
1696 */
LL_LPUART_IsActiveFlag_ORE(USART_TypeDef * LPUARTx)1697 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
1698 {
1699 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1700 }
1701
1702 /**
1703 * @brief Check if the LPUART IDLE line detected Flag is set or not
1704 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1705 * @param LPUARTx LPUART Instance
1706 * @retval State of bit (1 or 0).
1707 */
LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef * LPUARTx)1708 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
1709 {
1710 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1711 }
1712
1713 #if defined(USART_CR1_FIFOEN)
1714 /* Legacy define */
1715 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1716
1717 /**
1718 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1719 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1720 * @param LPUARTx LPUART Instance
1721 * @retval State of bit (1 or 0).
1722 */
LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef * LPUARTx)1723 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1724 {
1725 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1726 }
1727 #else
1728 /**
1729 * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not
1730 * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE
1731 * @param LPUARTx LPUART Instance
1732 * @retval State of bit (1 or 0).
1733 */
LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef * LPUARTx)1734 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
1735 {
1736 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
1737 }
1738 #endif /* USART_CR1_FIFOEN */
1739
1740 /**
1741 * @brief Check if the LPUART Transmission Complete Flag is set or not
1742 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1743 * @param LPUARTx LPUART Instance
1744 * @retval State of bit (1 or 0).
1745 */
LL_LPUART_IsActiveFlag_TC(USART_TypeDef * LPUARTx)1746 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
1747 {
1748 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1749 }
1750
1751 #if defined(USART_CR1_FIFOEN)
1752 /* Legacy define */
1753 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
1754
1755 /**
1756 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1757 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1758 * @param LPUARTx LPUART Instance
1759 * @retval State of bit (1 or 0).
1760 */
LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef * LPUARTx)1761 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
1762 {
1763 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1764 }
1765 #else
1766 /**
1767 * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not
1768 * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE
1769 * @param LPUARTx LPUART Instance
1770 * @retval State of bit (1 or 0).
1771 */
LL_LPUART_IsActiveFlag_TXE(USART_TypeDef * LPUARTx)1772 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
1773 {
1774 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
1775 }
1776 #endif /* USART_CR1_FIFOEN */
1777
1778 /**
1779 * @brief Check if the LPUART CTS interrupt Flag is set or not
1780 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1781 * @param LPUARTx LPUART Instance
1782 * @retval State of bit (1 or 0).
1783 */
LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef * LPUARTx)1784 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
1785 {
1786 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1787 }
1788
1789 /**
1790 * @brief Check if the LPUART CTS Flag is set or not
1791 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1792 * @param LPUARTx LPUART Instance
1793 * @retval State of bit (1 or 0).
1794 */
LL_LPUART_IsActiveFlag_CTS(USART_TypeDef * LPUARTx)1795 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
1796 {
1797 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1798 }
1799
1800 /**
1801 * @brief Check if the LPUART Busy Flag is set or not
1802 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1803 * @param LPUARTx LPUART Instance
1804 * @retval State of bit (1 or 0).
1805 */
LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef * LPUARTx)1806 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
1807 {
1808 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1809 }
1810
1811 /**
1812 * @brief Check if the LPUART Character Match Flag is set or not
1813 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1814 * @param LPUARTx LPUART Instance
1815 * @retval State of bit (1 or 0).
1816 */
LL_LPUART_IsActiveFlag_CM(USART_TypeDef * LPUARTx)1817 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
1818 {
1819 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1820 }
1821
1822 /**
1823 * @brief Check if the LPUART Send Break Flag is set or not
1824 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1825 * @param LPUARTx LPUART Instance
1826 * @retval State of bit (1 or 0).
1827 */
LL_LPUART_IsActiveFlag_SBK(USART_TypeDef * LPUARTx)1828 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
1829 {
1830 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1831 }
1832
1833 /**
1834 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1835 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1836 * @param LPUARTx LPUART Instance
1837 * @retval State of bit (1 or 0).
1838 */
LL_LPUART_IsActiveFlag_RWU(USART_TypeDef * LPUARTx)1839 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
1840 {
1841 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1842 }
1843
1844 /**
1845 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1846 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1847 * @param LPUARTx LPUART Instance
1848 * @retval State of bit (1 or 0).
1849 */
LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef * LPUARTx)1850 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
1851 {
1852 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1853 }
1854
1855 /**
1856 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1857 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1858 * @param LPUARTx LPUART Instance
1859 * @retval State of bit (1 or 0).
1860 */
LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef * LPUARTx)1861 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
1862 {
1863 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1864 }
1865
1866 /**
1867 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1868 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1869 * @param LPUARTx LPUART Instance
1870 * @retval State of bit (1 or 0).
1871 */
LL_LPUART_IsActiveFlag_REACK(USART_TypeDef * LPUARTx)1872 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
1873 {
1874 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1875 }
1876
1877 #if defined(USART_CR1_FIFOEN)
1878 /**
1879 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1880 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1881 * @param LPUARTx LPUART Instance
1882 * @retval State of bit (1 or 0).
1883 */
LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef * LPUARTx)1884 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
1885 {
1886 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1887 }
1888
1889 /**
1890 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1891 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1892 * @param LPUARTx LPUART Instance
1893 * @retval State of bit (1 or 0).
1894 */
LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef * LPUARTx)1895 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
1896 {
1897 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1898 }
1899
1900 /**
1901 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1902 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1903 * @param LPUARTx LPUART Instance
1904 * @retval State of bit (1 or 0).
1905 */
LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef * LPUARTx)1906 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
1907 {
1908 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1909 }
1910
1911 /**
1912 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1913 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1914 * @param LPUARTx LPUART Instance
1915 * @retval State of bit (1 or 0).
1916 */
LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef * LPUARTx)1917 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
1918 {
1919 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1920 }
1921 #endif /* USART_CR1_FIFOEN */
1922
1923 /**
1924 * @brief Clear Parity Error Flag
1925 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1926 * @param LPUARTx LPUART Instance
1927 * @retval None
1928 */
LL_LPUART_ClearFlag_PE(USART_TypeDef * LPUARTx)1929 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1930 {
1931 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1932 }
1933
1934 /**
1935 * @brief Clear Framing Error Flag
1936 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1937 * @param LPUARTx LPUART Instance
1938 * @retval None
1939 */
LL_LPUART_ClearFlag_FE(USART_TypeDef * LPUARTx)1940 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1941 {
1942 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1943 }
1944
1945 /**
1946 * @brief Clear Noise detected Flag
1947 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1948 * @param LPUARTx LPUART Instance
1949 * @retval None
1950 */
LL_LPUART_ClearFlag_NE(USART_TypeDef * LPUARTx)1951 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1952 {
1953 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1954 }
1955
1956 /**
1957 * @brief Clear OverRun Error Flag
1958 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1959 * @param LPUARTx LPUART Instance
1960 * @retval None
1961 */
LL_LPUART_ClearFlag_ORE(USART_TypeDef * LPUARTx)1962 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1963 {
1964 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1965 }
1966
1967 /**
1968 * @brief Clear IDLE line detected Flag
1969 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1970 * @param LPUARTx LPUART Instance
1971 * @retval None
1972 */
LL_LPUART_ClearFlag_IDLE(USART_TypeDef * LPUARTx)1973 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1974 {
1975 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1976 }
1977
1978 #if defined(USART_CR1_FIFOEN)
1979 /**
1980 * @brief Clear TX FIFO Empty Flag
1981 * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE
1982 * @param LPUARTx LPUART Instance
1983 * @retval None
1984 */
LL_LPUART_ClearFlag_TXFE(USART_TypeDef * LPUARTx)1985 __STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
1986 {
1987 WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
1988 }
1989 #endif /* USART_CR1_FIFOEN */
1990
1991 /**
1992 * @brief Clear Transmission Complete Flag
1993 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1994 * @param LPUARTx LPUART Instance
1995 * @retval None
1996 */
LL_LPUART_ClearFlag_TC(USART_TypeDef * LPUARTx)1997 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1998 {
1999 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
2000 }
2001
2002 /**
2003 * @brief Clear CTS Interrupt Flag
2004 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
2005 * @param LPUARTx LPUART Instance
2006 * @retval None
2007 */
LL_LPUART_ClearFlag_nCTS(USART_TypeDef * LPUARTx)2008 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
2009 {
2010 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
2011 }
2012
2013 /**
2014 * @brief Clear Character Match Flag
2015 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
2016 * @param LPUARTx LPUART Instance
2017 * @retval None
2018 */
LL_LPUART_ClearFlag_CM(USART_TypeDef * LPUARTx)2019 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
2020 {
2021 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
2022 }
2023
2024 /**
2025 * @brief Clear Wake Up from stop mode Flag
2026 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
2027 * @param LPUARTx LPUART Instance
2028 * @retval None
2029 */
LL_LPUART_ClearFlag_WKUP(USART_TypeDef * LPUARTx)2030 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
2031 {
2032 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
2033 }
2034
2035 /**
2036 * @}
2037 */
2038
2039 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
2040 * @{
2041 */
2042
2043 /**
2044 * @brief Enable IDLE Interrupt
2045 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
2046 * @param LPUARTx LPUART Instance
2047 * @retval None
2048 */
LL_LPUART_EnableIT_IDLE(USART_TypeDef * LPUARTx)2049 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
2050 {
2051 SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2052 }
2053
2054 #if defined(USART_CR1_FIFOEN)
2055 /* Legacy define */
2056 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
2057
2058 /**
2059 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
2060 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
2061 * @param LPUARTx LPUART Instance
2062 * @retval None
2063 */
LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2064 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2065 {
2066 SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2067 }
2068 #else
2069
2070 /**
2071 * @brief Enable RX Not Empty Interrupt
2072 * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE
2073 * @param LPUARTx LPUART Instance
2074 * @retval None
2075 */
LL_LPUART_EnableIT_RXNE(USART_TypeDef * LPUARTx)2076 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
2077 {
2078 SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
2079 }
2080 #endif /* USART_CR1_FIFOEN */
2081
2082 /**
2083 * @brief Enable Transmission Complete Interrupt
2084 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
2085 * @param LPUARTx LPUART Instance
2086 * @retval None
2087 */
LL_LPUART_EnableIT_TC(USART_TypeDef * LPUARTx)2088 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
2089 {
2090 SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2091 }
2092
2093 #if defined(USART_CR1_FIFOEN)
2094 /* Legacy define */
2095 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
2096
2097 /**
2098 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
2099 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
2100 * @param LPUARTx LPUART Instance
2101 * @retval None
2102 */
LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2103 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2104 {
2105 SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2106 }
2107 #else
2108
2109 /**
2110 * @brief Enable TX Empty Interrupt
2111 * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE
2112 * @param LPUARTx LPUART Instance
2113 * @retval None
2114 */
LL_LPUART_EnableIT_TXE(USART_TypeDef * LPUARTx)2115 __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
2116 {
2117 SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
2118 }
2119 #endif /* USART_CR1_FIFOEN */
2120
2121 /**
2122 * @brief Enable Parity Error Interrupt
2123 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
2124 * @param LPUARTx LPUART Instance
2125 * @retval None
2126 */
LL_LPUART_EnableIT_PE(USART_TypeDef * LPUARTx)2127 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
2128 {
2129 SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2130 }
2131
2132 /**
2133 * @brief Enable Character Match Interrupt
2134 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
2135 * @param LPUARTx LPUART Instance
2136 * @retval None
2137 */
LL_LPUART_EnableIT_CM(USART_TypeDef * LPUARTx)2138 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
2139 {
2140 SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2141 }
2142
2143 #if defined(USART_CR1_FIFOEN)
2144 /**
2145 * @brief Enable TX FIFO Empty Interrupt
2146 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
2147 * @param LPUARTx LPUART Instance
2148 * @retval None
2149 */
LL_LPUART_EnableIT_TXFE(USART_TypeDef * LPUARTx)2150 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
2151 {
2152 SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2153 }
2154
2155 /**
2156 * @brief Enable RX FIFO Full Interrupt
2157 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
2158 * @param LPUARTx LPUART Instance
2159 * @retval None
2160 */
LL_LPUART_EnableIT_RXFF(USART_TypeDef * LPUARTx)2161 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
2162 {
2163 SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2164 }
2165 #endif /* USART_CR1_FIFOEN */
2166
2167 /**
2168 * @brief Enable Error Interrupt
2169 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2170 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2171 * - 0: Interrupt is inhibited
2172 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2173 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
2174 * @param LPUARTx LPUART Instance
2175 * @retval None
2176 */
LL_LPUART_EnableIT_ERROR(USART_TypeDef * LPUARTx)2177 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2178 {
2179 SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2180 }
2181
2182 /**
2183 * @brief Enable CTS Interrupt
2184 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2185 * @param LPUARTx LPUART Instance
2186 * @retval None
2187 */
LL_LPUART_EnableIT_CTS(USART_TypeDef * LPUARTx)2188 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2189 {
2190 SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2191 }
2192
2193 /**
2194 * @brief Enable Wake Up from Stop Mode Interrupt
2195 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
2196 * @param LPUARTx LPUART Instance
2197 * @retval None
2198 */
LL_LPUART_EnableIT_WKUP(USART_TypeDef * LPUARTx)2199 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2200 {
2201 SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2202 }
2203
2204 #if defined(USART_CR1_FIFOEN)
2205 /**
2206 * @brief Enable TX FIFO Threshold Interrupt
2207 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2208 * @param LPUARTx LPUART Instance
2209 * @retval None
2210 */
LL_LPUART_EnableIT_TXFT(USART_TypeDef * LPUARTx)2211 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2212 {
2213 SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2214 }
2215
2216 /**
2217 * @brief Enable RX FIFO Threshold Interrupt
2218 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2219 * @param LPUARTx LPUART Instance
2220 * @retval None
2221 */
LL_LPUART_EnableIT_RXFT(USART_TypeDef * LPUARTx)2222 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2223 {
2224 SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2225 }
2226 #endif /* USART_CR1_FIFOEN */
2227
2228 /**
2229 * @brief Disable IDLE Interrupt
2230 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2231 * @param LPUARTx LPUART Instance
2232 * @retval None
2233 */
LL_LPUART_DisableIT_IDLE(USART_TypeDef * LPUARTx)2234 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2235 {
2236 CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2237 }
2238
2239 #if defined(USART_CR1_FIFOEN)
2240 /* Legacy define */
2241 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
2242
2243 /**
2244 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2245 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2246 * @param LPUARTx LPUART Instance
2247 * @retval None
2248 */
LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2249 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2250 {
2251 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2252 }
2253 #else
2254
2255 /**
2256 * @brief Disable RX Not Empty Interrupt
2257 * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE
2258 * @param LPUARTx LPUART Instance
2259 * @retval None
2260 */
LL_LPUART_DisableIT_RXNE(USART_TypeDef * LPUARTx)2261 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
2262 {
2263 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
2264 }
2265 #endif /* USART_CR1_FIFOEN */
2266
2267 /**
2268 * @brief Disable Transmission Complete Interrupt
2269 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2270 * @param LPUARTx LPUART Instance
2271 * @retval None
2272 */
LL_LPUART_DisableIT_TC(USART_TypeDef * LPUARTx)2273 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2274 {
2275 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2276 }
2277
2278 #if defined(USART_CR1_FIFOEN)
2279 /* Legacy define */
2280 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
2281
2282 /**
2283 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2284 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2285 * @param LPUARTx LPUART Instance
2286 * @retval None
2287 */
LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2288 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2289 {
2290 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2291 }
2292 #else
2293
2294 /**
2295 * @brief Disable TX Empty Interrupt
2296 * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE
2297 * @param LPUARTx LPUART Instance
2298 * @retval None
2299 */
LL_LPUART_DisableIT_TXE(USART_TypeDef * LPUARTx)2300 __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
2301 {
2302 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
2303 }
2304 #endif /* USART_CR1_FIFOEN */
2305
2306 /**
2307 * @brief Disable Parity Error Interrupt
2308 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2309 * @param LPUARTx LPUART Instance
2310 * @retval None
2311 */
LL_LPUART_DisableIT_PE(USART_TypeDef * LPUARTx)2312 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2313 {
2314 CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2315 }
2316
2317 /**
2318 * @brief Disable Character Match Interrupt
2319 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2320 * @param LPUARTx LPUART Instance
2321 * @retval None
2322 */
LL_LPUART_DisableIT_CM(USART_TypeDef * LPUARTx)2323 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2324 {
2325 CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2326 }
2327
2328 #if defined(USART_CR1_FIFOEN)
2329 /**
2330 * @brief Disable TX FIFO Empty Interrupt
2331 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2332 * @param LPUARTx LPUART Instance
2333 * @retval None
2334 */
LL_LPUART_DisableIT_TXFE(USART_TypeDef * LPUARTx)2335 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2336 {
2337 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2338 }
2339
2340 /**
2341 * @brief Disable RX FIFO Full Interrupt
2342 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2343 * @param LPUARTx LPUART Instance
2344 * @retval None
2345 */
LL_LPUART_DisableIT_RXFF(USART_TypeDef * LPUARTx)2346 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2347 {
2348 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2349 }
2350 #endif /* USART_CR1_FIFOEN */
2351
2352 /**
2353 * @brief Disable Error Interrupt
2354 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2355 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2356 * - 0: Interrupt is inhibited
2357 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2358 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2359 * @param LPUARTx LPUART Instance
2360 * @retval None
2361 */
LL_LPUART_DisableIT_ERROR(USART_TypeDef * LPUARTx)2362 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2363 {
2364 CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2365 }
2366
2367 /**
2368 * @brief Disable CTS Interrupt
2369 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2370 * @param LPUARTx LPUART Instance
2371 * @retval None
2372 */
LL_LPUART_DisableIT_CTS(USART_TypeDef * LPUARTx)2373 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2374 {
2375 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2376 }
2377
2378 /**
2379 * @brief Disable Wake Up from Stop Mode Interrupt
2380 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
2381 * @param LPUARTx LPUART Instance
2382 * @retval None
2383 */
LL_LPUART_DisableIT_WKUP(USART_TypeDef * LPUARTx)2384 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2385 {
2386 CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2387 }
2388
2389 #if defined(USART_CR1_FIFOEN)
2390 /**
2391 * @brief Disable TX FIFO Threshold Interrupt
2392 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2393 * @param LPUARTx LPUART Instance
2394 * @retval None
2395 */
LL_LPUART_DisableIT_TXFT(USART_TypeDef * LPUARTx)2396 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2397 {
2398 CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2399 }
2400
2401 /**
2402 * @brief Disable RX FIFO Threshold Interrupt
2403 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2404 * @param LPUARTx LPUART Instance
2405 * @retval None
2406 */
LL_LPUART_DisableIT_RXFT(USART_TypeDef * LPUARTx)2407 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2408 {
2409 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2410 }
2411 #endif /* USART_CR1_FIFOEN */
2412
2413 /**
2414 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2415 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2416 * @param LPUARTx LPUART Instance
2417 * @retval State of bit (1 or 0).
2418 */
LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef * LPUARTx)2419 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
2420 {
2421 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2422 }
2423
2424 #if defined(USART_CR1_FIFOEN)
2425 /* Legacy define */
2426 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2427
2428 /**
2429 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2430 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2431 * @param LPUARTx LPUART Instance
2432 * @retval State of bit (1 or 0).
2433 */
LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2434 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2435 {
2436 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2437 }
2438 #else
2439
2440 /**
2441 * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
2442 * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE
2443 * @param LPUARTx LPUART Instance
2444 * @retval State of bit (1 or 0).
2445 */
LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef * LPUARTx)2446 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
2447 {
2448 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1UL : 0UL);
2449 }
2450 #endif /* USART_CR1_FIFOEN */
2451
2452 /**
2453 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2454 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2455 * @param LPUARTx LPUART Instance
2456 * @retval State of bit (1 or 0).
2457 */
LL_LPUART_IsEnabledIT_TC(USART_TypeDef * LPUARTx)2458 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
2459 {
2460 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2461 }
2462
2463 #if defined(USART_CR1_FIFOEN)
2464 /* Legacy define */
2465 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
2466
2467 /**
2468 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2469 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2470 * @param LPUARTx LPUART Instance
2471 * @retval State of bit (1 or 0).
2472 */
LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2473 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2474 {
2475 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2476 }
2477 #else
2478
2479 /**
2480 * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled.
2481 * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE
2482 * @param LPUARTx LPUART Instance
2483 * @retval State of bit (1 or 0).
2484 */
LL_LPUART_IsEnabledIT_TXE(USART_TypeDef * LPUARTx)2485 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
2486 {
2487 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1UL : 0UL);
2488 }
2489 #endif /* USART_CR1_FIFOEN */
2490
2491 /**
2492 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2493 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2494 * @param LPUARTx LPUART Instance
2495 * @retval State of bit (1 or 0).
2496 */
LL_LPUART_IsEnabledIT_PE(USART_TypeDef * LPUARTx)2497 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
2498 {
2499 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2500 }
2501
2502 /**
2503 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2504 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2505 * @param LPUARTx LPUART Instance
2506 * @retval State of bit (1 or 0).
2507 */
LL_LPUART_IsEnabledIT_CM(USART_TypeDef * LPUARTx)2508 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
2509 {
2510 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2511 }
2512
2513 #if defined(USART_CR1_FIFOEN)
2514 /**
2515 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2516 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2517 * @param LPUARTx LPUART Instance
2518 * @retval State of bit (1 or 0).
2519 */
LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef * LPUARTx)2520 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
2521 {
2522 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2523 }
2524
2525 /**
2526 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2527 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2528 * @param LPUARTx LPUART Instance
2529 * @retval State of bit (1 or 0).
2530 */
LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef * LPUARTx)2531 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
2532 {
2533 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2534 }
2535 #endif /* USART_CR1_FIFOEN */
2536
2537 /**
2538 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2539 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2540 * @param LPUARTx LPUART Instance
2541 * @retval State of bit (1 or 0).
2542 */
LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef * LPUARTx)2543 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
2544 {
2545 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2546 }
2547
2548 /**
2549 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2550 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2551 * @param LPUARTx LPUART Instance
2552 * @retval State of bit (1 or 0).
2553 */
LL_LPUART_IsEnabledIT_CTS(USART_TypeDef * LPUARTx)2554 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
2555 {
2556 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2557 }
2558
2559 /**
2560 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
2561 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
2562 * @param LPUARTx LPUART Instance
2563 * @retval State of bit (1 or 0).
2564 */
LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef * LPUARTx)2565 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
2566 {
2567 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2568 }
2569
2570 #if defined(USART_CR1_FIFOEN)
2571 /**
2572 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2573 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2574 * @param LPUARTx LPUART Instance
2575 * @retval State of bit (1 or 0).
2576 */
LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef * LPUARTx)2577 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
2578 {
2579 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2580 }
2581
2582 /**
2583 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2584 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2585 * @param LPUARTx LPUART Instance
2586 * @retval State of bit (1 or 0).
2587 */
LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef * LPUARTx)2588 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
2589 {
2590 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2591 }
2592 #endif /* USART_CR1_FIFOEN */
2593
2594 /**
2595 * @}
2596 */
2597
2598 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2599 * @{
2600 */
2601
2602 /**
2603 * @brief Enable DMA Mode for reception
2604 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2605 * @param LPUARTx LPUART Instance
2606 * @retval None
2607 */
LL_LPUART_EnableDMAReq_RX(USART_TypeDef * LPUARTx)2608 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2609 {
2610 SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2611 }
2612
2613 /**
2614 * @brief Disable DMA Mode for reception
2615 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2616 * @param LPUARTx LPUART Instance
2617 * @retval None
2618 */
LL_LPUART_DisableDMAReq_RX(USART_TypeDef * LPUARTx)2619 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2620 {
2621 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2622 }
2623
2624 /**
2625 * @brief Check if DMA Mode is enabled for reception
2626 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2627 * @param LPUARTx LPUART Instance
2628 * @retval State of bit (1 or 0).
2629 */
LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef * LPUARTx)2630 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
2631 {
2632 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2633 }
2634
2635 /**
2636 * @brief Enable DMA Mode for transmission
2637 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2638 * @param LPUARTx LPUART Instance
2639 * @retval None
2640 */
LL_LPUART_EnableDMAReq_TX(USART_TypeDef * LPUARTx)2641 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2642 {
2643 SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2644 }
2645
2646 /**
2647 * @brief Disable DMA Mode for transmission
2648 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2649 * @param LPUARTx LPUART Instance
2650 * @retval None
2651 */
LL_LPUART_DisableDMAReq_TX(USART_TypeDef * LPUARTx)2652 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2653 {
2654 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2655 }
2656
2657 /**
2658 * @brief Check if DMA Mode is enabled for transmission
2659 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2660 * @param LPUARTx LPUART Instance
2661 * @retval State of bit (1 or 0).
2662 */
LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef * LPUARTx)2663 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
2664 {
2665 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2666 }
2667
2668 /**
2669 * @brief Enable DMA Disabling on Reception Error
2670 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2671 * @param LPUARTx LPUART Instance
2672 * @retval None
2673 */
LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2674 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2675 {
2676 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2677 }
2678
2679 /**
2680 * @brief Disable DMA Disabling on Reception Error
2681 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2682 * @param LPUARTx LPUART Instance
2683 * @retval None
2684 */
LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2685 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2686 {
2687 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2688 }
2689
2690 /**
2691 * @brief Indicate if DMA Disabling on Reception Error is disabled
2692 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2693 * @param LPUARTx LPUART Instance
2694 * @retval State of bit (1 or 0).
2695 */
LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef * LPUARTx)2696 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2697 {
2698 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2699 }
2700
2701 /**
2702 * @brief Get the LPUART data register address used for DMA transfer
2703 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2704 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2705 * @param LPUARTx LPUART Instance
2706 * @param Direction This parameter can be one of the following values:
2707 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2708 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2709 * @retval Address of data register
2710 */
LL_LPUART_DMA_GetRegAddr(USART_TypeDef * LPUARTx,uint32_t Direction)2711 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
2712 {
2713 register uint32_t data_reg_addr;
2714
2715 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2716 {
2717 /* return address of TDR register */
2718 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2719 }
2720 else
2721 {
2722 /* return address of RDR register */
2723 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2724 }
2725
2726 return data_reg_addr;
2727 }
2728
2729 /**
2730 * @}
2731 */
2732
2733 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2734 * @{
2735 */
2736
2737 /**
2738 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2739 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2740 * @param LPUARTx LPUART Instance
2741 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2742 */
LL_LPUART_ReceiveData8(USART_TypeDef * LPUARTx)2743 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
2744 {
2745 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2746 }
2747
2748 /**
2749 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2750 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2751 * @param LPUARTx LPUART Instance
2752 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2753 */
LL_LPUART_ReceiveData9(USART_TypeDef * LPUARTx)2754 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
2755 {
2756 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2757 }
2758
2759 /**
2760 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2761 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2762 * @param LPUARTx LPUART Instance
2763 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2764 * @retval None
2765 */
LL_LPUART_TransmitData8(USART_TypeDef * LPUARTx,uint8_t Value)2766 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2767 {
2768 LPUARTx->TDR = Value;
2769 }
2770
2771 /**
2772 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2773 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2774 * @param LPUARTx LPUART Instance
2775 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2776 * @retval None
2777 */
LL_LPUART_TransmitData9(USART_TypeDef * LPUARTx,uint16_t Value)2778 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2779 {
2780 LPUARTx->TDR = Value & 0x1FFUL;
2781 }
2782
2783 /**
2784 * @}
2785 */
2786
2787 /** @defgroup LPUART_LL_EF_Execution Execution
2788 * @{
2789 */
2790
2791 /**
2792 * @brief Request Break sending
2793 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2794 * @param LPUARTx LPUART Instance
2795 * @retval None
2796 */
LL_LPUART_RequestBreakSending(USART_TypeDef * LPUARTx)2797 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2798 {
2799 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2800 }
2801
2802 /**
2803 * @brief Put LPUART in mute mode and set the RWU flag
2804 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2805 * @param LPUARTx LPUART Instance
2806 * @retval None
2807 */
LL_LPUART_RequestEnterMuteMode(USART_TypeDef * LPUARTx)2808 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2809 {
2810 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2811 }
2812
2813 /**
2814 @if USART_CR1_FIFOEN
2815 * @brief Request a Receive Data and FIFO flush
2816 * @note Allows to discard the received data without reading them, and avoid an overrun
2817 * condition.
2818 @else
2819 * @brief Request a Receive Data flush
2820 @endif
2821 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2822 * @param LPUARTx LPUART Instance
2823 * @retval None
2824 */
LL_LPUART_RequestRxDataFlush(USART_TypeDef * LPUARTx)2825 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2826 {
2827 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2828 }
2829
2830 /**
2831 * @}
2832 */
2833
2834 #if defined(USE_FULL_LL_DRIVER)
2835 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2836 * @{
2837 */
2838 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
2839 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
2840 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2841 /**
2842 * @}
2843 */
2844 #endif /* USE_FULL_LL_DRIVER */
2845
2846 /**
2847 * @}
2848 */
2849
2850 /**
2851 * @}
2852 */
2853
2854 #endif /* LPUART1 */
2855
2856 /**
2857 * @}
2858 */
2859
2860 #ifdef __cplusplus
2861 }
2862 #endif
2863
2864 #endif /* STM32L4xx_LL_LPUART_H */
2865
2866 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2867