1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F4xx_LL_SPI_H
22 #define STM32F4xx_LL_SPI_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx.h"
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
36
37 /** @defgroup SPI_LL SPI
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
48 * @{
49 */
50
51 /**
52 * @brief SPI Init structures definition
53 */
54 typedef struct
55 {
56 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
57 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
58
59 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
60
61 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
62 This parameter can be a value of @ref SPI_LL_EC_MODE.
63
64 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
65
66 uint32_t DataWidth; /*!< Specifies the SPI data width.
67 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
68
69 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
70
71 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
72 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
73
74 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
75
76 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
77 This parameter can be a value of @ref SPI_LL_EC_PHASE.
78
79 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
80
81 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
82 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
83
84 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
85
86 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
87 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
88 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
89
90 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
91
92 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
93 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
94
95 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
96
97 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
98 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
99
100 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
101
102 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
103 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
104
105 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
106
107 } LL_SPI_InitTypeDef;
108
109 /**
110 * @}
111 */
112 #endif /* USE_FULL_LL_DRIVER */
113
114 /* Exported constants --------------------------------------------------------*/
115 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
116 * @{
117 */
118
119 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
120 * @brief Flags defines which can be used with LL_SPI_ReadReg function
121 * @{
122 */
123 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
124 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
125 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
126 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
127 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
128 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
129 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
130 /**
131 * @}
132 */
133
134 /** @defgroup SPI_LL_EC_IT IT Defines
135 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
136 * @{
137 */
138 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
139 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
140 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
141 /**
142 * @}
143 */
144
145 /** @defgroup SPI_LL_EC_MODE Operation Mode
146 * @{
147 */
148 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
149 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
150 /**
151 * @}
152 */
153
154 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
155 * @{
156 */
157 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
158 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
159 /**
160 * @}
161 */
162
163 /** @defgroup SPI_LL_EC_PHASE Clock Phase
164 * @{
165 */
166 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
167 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
168 /**
169 * @}
170 */
171
172 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
173 * @{
174 */
175 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
176 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
177 /**
178 * @}
179 */
180
181 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
182 * @{
183 */
184 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
185 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
186 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
187 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
188 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
189 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
190 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
191 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
192 /**
193 * @}
194 */
195
196 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
197 * @{
198 */
199 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
200 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
201 /**
202 * @}
203 */
204
205 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
206 * @{
207 */
208 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
209 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
210 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
211 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
212 /**
213 * @}
214 */
215
216 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
217 * @{
218 */
219 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
220 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
221 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
222 /**
223 * @}
224 */
225
226 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
227 * @{
228 */
229 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
230 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
231 /**
232 * @}
233 */
234 #if defined(USE_FULL_LL_DRIVER)
235
236 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
237 * @{
238 */
239 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
240 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
241 /**
242 * @}
243 */
244 #endif /* USE_FULL_LL_DRIVER */
245
246 /**
247 * @}
248 */
249
250 /* Exported macro ------------------------------------------------------------*/
251 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
252 * @{
253 */
254
255 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
256 * @{
257 */
258
259 /**
260 * @brief Write a value in SPI register
261 * @param __INSTANCE__ SPI Instance
262 * @param __REG__ Register to be written
263 * @param __VALUE__ Value to be written in the register
264 * @retval None
265 */
266 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
267
268 /**
269 * @brief Read a value in SPI register
270 * @param __INSTANCE__ SPI Instance
271 * @param __REG__ Register to be read
272 * @retval Register value
273 */
274 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
275 /**
276 * @}
277 */
278
279 /**
280 * @}
281 */
282
283 /* Exported functions --------------------------------------------------------*/
284 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
285 * @{
286 */
287
288 /** @defgroup SPI_LL_EF_Configuration Configuration
289 * @{
290 */
291
292 /**
293 * @brief Enable SPI peripheral
294 * @rmtoll CR1 SPE LL_SPI_Enable
295 * @param SPIx SPI Instance
296 * @retval None
297 */
LL_SPI_Enable(SPI_TypeDef * SPIx)298 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
299 {
300 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
301 }
302
303 /**
304 * @brief Disable SPI peripheral
305 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
306 * @rmtoll CR1 SPE LL_SPI_Disable
307 * @param SPIx SPI Instance
308 * @retval None
309 */
LL_SPI_Disable(SPI_TypeDef * SPIx)310 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
311 {
312 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
313 }
314
315 /**
316 * @brief Check if SPI peripheral is enabled
317 * @rmtoll CR1 SPE LL_SPI_IsEnabled
318 * @param SPIx SPI Instance
319 * @retval State of bit (1 or 0).
320 */
LL_SPI_IsEnabled(SPI_TypeDef * SPIx)321 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
322 {
323 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
324 }
325
326 /**
327 * @brief Set SPI operation mode to Master or Slave
328 * @note This bit should not be changed when communication is ongoing.
329 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
330 * CR1 SSI LL_SPI_SetMode
331 * @param SPIx SPI Instance
332 * @param Mode This parameter can be one of the following values:
333 * @arg @ref LL_SPI_MODE_MASTER
334 * @arg @ref LL_SPI_MODE_SLAVE
335 * @retval None
336 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)337 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
338 {
339 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
340 }
341
342 /**
343 * @brief Get SPI operation mode (Master or Slave)
344 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
345 * CR1 SSI LL_SPI_GetMode
346 * @param SPIx SPI Instance
347 * @retval Returned value can be one of the following values:
348 * @arg @ref LL_SPI_MODE_MASTER
349 * @arg @ref LL_SPI_MODE_SLAVE
350 */
LL_SPI_GetMode(SPI_TypeDef * SPIx)351 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
352 {
353 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
354 }
355
356 /**
357 * @brief Set serial protocol used
358 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
359 * @rmtoll CR2 FRF LL_SPI_SetStandard
360 * @param SPIx SPI Instance
361 * @param Standard This parameter can be one of the following values:
362 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
363 * @arg @ref LL_SPI_PROTOCOL_TI
364 * @retval None
365 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)366 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
367 {
368 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
369 }
370
371 /**
372 * @brief Get serial protocol used
373 * @rmtoll CR2 FRF LL_SPI_GetStandard
374 * @param SPIx SPI Instance
375 * @retval Returned value can be one of the following values:
376 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
377 * @arg @ref LL_SPI_PROTOCOL_TI
378 */
LL_SPI_GetStandard(SPI_TypeDef * SPIx)379 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
380 {
381 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
382 }
383
384 /**
385 * @brief Set clock phase
386 * @note This bit should not be changed when communication is ongoing.
387 * This bit is not used in SPI TI mode.
388 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
389 * @param SPIx SPI Instance
390 * @param ClockPhase This parameter can be one of the following values:
391 * @arg @ref LL_SPI_PHASE_1EDGE
392 * @arg @ref LL_SPI_PHASE_2EDGE
393 * @retval None
394 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)395 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
396 {
397 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
398 }
399
400 /**
401 * @brief Get clock phase
402 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
403 * @param SPIx SPI Instance
404 * @retval Returned value can be one of the following values:
405 * @arg @ref LL_SPI_PHASE_1EDGE
406 * @arg @ref LL_SPI_PHASE_2EDGE
407 */
LL_SPI_GetClockPhase(SPI_TypeDef * SPIx)408 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
409 {
410 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
411 }
412
413 /**
414 * @brief Set clock polarity
415 * @note This bit should not be changed when communication is ongoing.
416 * This bit is not used in SPI TI mode.
417 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
418 * @param SPIx SPI Instance
419 * @param ClockPolarity This parameter can be one of the following values:
420 * @arg @ref LL_SPI_POLARITY_LOW
421 * @arg @ref LL_SPI_POLARITY_HIGH
422 * @retval None
423 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)424 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
425 {
426 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
427 }
428
429 /**
430 * @brief Get clock polarity
431 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
432 * @param SPIx SPI Instance
433 * @retval Returned value can be one of the following values:
434 * @arg @ref LL_SPI_POLARITY_LOW
435 * @arg @ref LL_SPI_POLARITY_HIGH
436 */
LL_SPI_GetClockPolarity(SPI_TypeDef * SPIx)437 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
438 {
439 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
440 }
441
442 /**
443 * @brief Set baud rate prescaler
444 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
445 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
446 * @param SPIx SPI Instance
447 * @param BaudRate This parameter can be one of the following values:
448 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
449 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
450 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
451 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
452 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
453 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
454 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
455 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
456 * @retval None
457 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t BaudRate)458 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
459 {
460 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
461 }
462
463 /**
464 * @brief Get baud rate prescaler
465 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
466 * @param SPIx SPI Instance
467 * @retval Returned value can be one of the following values:
468 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
469 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
470 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
472 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
473 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
474 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
475 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
476 */
LL_SPI_GetBaudRatePrescaler(SPI_TypeDef * SPIx)477 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
478 {
479 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
480 }
481
482 /**
483 * @brief Set transfer bit order
484 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
485 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
486 * @param SPIx SPI Instance
487 * @param BitOrder This parameter can be one of the following values:
488 * @arg @ref LL_SPI_LSB_FIRST
489 * @arg @ref LL_SPI_MSB_FIRST
490 * @retval None
491 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)492 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
493 {
494 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
495 }
496
497 /**
498 * @brief Get transfer bit order
499 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
500 * @param SPIx SPI Instance
501 * @retval Returned value can be one of the following values:
502 * @arg @ref LL_SPI_LSB_FIRST
503 * @arg @ref LL_SPI_MSB_FIRST
504 */
LL_SPI_GetTransferBitOrder(SPI_TypeDef * SPIx)505 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
506 {
507 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
508 }
509
510 /**
511 * @brief Set transfer direction mode
512 * @note For Half-Duplex mode, Rx Direction is set by default.
513 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
514 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
515 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
516 * CR1 BIDIOE LL_SPI_SetTransferDirection
517 * @param SPIx SPI Instance
518 * @param TransferDirection This parameter can be one of the following values:
519 * @arg @ref LL_SPI_FULL_DUPLEX
520 * @arg @ref LL_SPI_SIMPLEX_RX
521 * @arg @ref LL_SPI_HALF_DUPLEX_RX
522 * @arg @ref LL_SPI_HALF_DUPLEX_TX
523 * @retval None
524 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)525 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
526 {
527 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
528 }
529
530 /**
531 * @brief Get transfer direction mode
532 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
533 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
534 * CR1 BIDIOE LL_SPI_GetTransferDirection
535 * @param SPIx SPI Instance
536 * @retval Returned value can be one of the following values:
537 * @arg @ref LL_SPI_FULL_DUPLEX
538 * @arg @ref LL_SPI_SIMPLEX_RX
539 * @arg @ref LL_SPI_HALF_DUPLEX_RX
540 * @arg @ref LL_SPI_HALF_DUPLEX_TX
541 */
LL_SPI_GetTransferDirection(SPI_TypeDef * SPIx)542 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
543 {
544 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
545 }
546
547 /**
548 * @brief Set frame data width
549 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
550 * @param SPIx SPI Instance
551 * @param DataWidth This parameter can be one of the following values:
552 * @arg @ref LL_SPI_DATAWIDTH_8BIT
553 * @arg @ref LL_SPI_DATAWIDTH_16BIT
554 * @retval None
555 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)556 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
557 {
558 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
559 }
560
561 /**
562 * @brief Get frame data width
563 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
564 * @param SPIx SPI Instance
565 * @retval Returned value can be one of the following values:
566 * @arg @ref LL_SPI_DATAWIDTH_8BIT
567 * @arg @ref LL_SPI_DATAWIDTH_16BIT
568 */
LL_SPI_GetDataWidth(SPI_TypeDef * SPIx)569 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
570 {
571 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
572 }
573
574 /**
575 * @}
576 */
577
578 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
579 * @{
580 */
581
582 /**
583 * @brief Enable CRC
584 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
585 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
586 * @param SPIx SPI Instance
587 * @retval None
588 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)589 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
590 {
591 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
592 }
593
594 /**
595 * @brief Disable CRC
596 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
597 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
598 * @param SPIx SPI Instance
599 * @retval None
600 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)601 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
602 {
603 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
604 }
605
606 /**
607 * @brief Check if CRC is enabled
608 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
609 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
610 * @param SPIx SPI Instance
611 * @retval State of bit (1 or 0).
612 */
LL_SPI_IsEnabledCRC(SPI_TypeDef * SPIx)613 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
614 {
615 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
616 }
617
618 /**
619 * @brief Set CRCNext to transfer CRC on the line
620 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
621 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
622 * @param SPIx SPI Instance
623 * @retval None
624 */
LL_SPI_SetCRCNext(SPI_TypeDef * SPIx)625 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
626 {
627 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
628 }
629
630 /**
631 * @brief Set polynomial for CRC calculation
632 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
633 * @param SPIx SPI Instance
634 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
635 * @retval None
636 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)637 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
638 {
639 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
640 }
641
642 /**
643 * @brief Get polynomial for CRC calculation
644 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
645 * @param SPIx SPI Instance
646 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
647 */
LL_SPI_GetCRCPolynomial(SPI_TypeDef * SPIx)648 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
649 {
650 return (uint32_t)(READ_REG(SPIx->CRCPR));
651 }
652
653 /**
654 * @brief Get Rx CRC
655 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
656 * @param SPIx SPI Instance
657 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
658 */
LL_SPI_GetRxCRC(SPI_TypeDef * SPIx)659 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
660 {
661 return (uint32_t)(READ_REG(SPIx->RXCRCR));
662 }
663
664 /**
665 * @brief Get Tx CRC
666 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
667 * @param SPIx SPI Instance
668 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
669 */
LL_SPI_GetTxCRC(SPI_TypeDef * SPIx)670 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
671 {
672 return (uint32_t)(READ_REG(SPIx->TXCRCR));
673 }
674
675 /**
676 * @}
677 */
678
679 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
680 * @{
681 */
682
683 /**
684 * @brief Set NSS mode
685 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
686 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
687 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
688 * @param SPIx SPI Instance
689 * @param NSS This parameter can be one of the following values:
690 * @arg @ref LL_SPI_NSS_SOFT
691 * @arg @ref LL_SPI_NSS_HARD_INPUT
692 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
693 * @retval None
694 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)695 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
696 {
697 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
698 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
699 }
700
701 /**
702 * @brief Get NSS mode
703 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
704 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
705 * @param SPIx SPI Instance
706 * @retval Returned value can be one of the following values:
707 * @arg @ref LL_SPI_NSS_SOFT
708 * @arg @ref LL_SPI_NSS_HARD_INPUT
709 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
710 */
LL_SPI_GetNSSMode(SPI_TypeDef * SPIx)711 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
712 {
713 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
714 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
715 return (Ssm | Ssoe);
716 }
717
718 /**
719 * @}
720 */
721
722 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
723 * @{
724 */
725
726 /**
727 * @brief Check if Rx buffer is not empty
728 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
729 * @param SPIx SPI Instance
730 * @retval State of bit (1 or 0).
731 */
LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef * SPIx)732 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
733 {
734 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
735 }
736
737 /**
738 * @brief Check if Tx buffer is empty
739 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
740 * @param SPIx SPI Instance
741 * @retval State of bit (1 or 0).
742 */
LL_SPI_IsActiveFlag_TXE(SPI_TypeDef * SPIx)743 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
744 {
745 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
746 }
747
748 /**
749 * @brief Get CRC error flag
750 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
751 * @param SPIx SPI Instance
752 * @retval State of bit (1 or 0).
753 */
LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef * SPIx)754 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
755 {
756 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
757 }
758
759 /**
760 * @brief Get mode fault error flag
761 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
762 * @param SPIx SPI Instance
763 * @retval State of bit (1 or 0).
764 */
LL_SPI_IsActiveFlag_MODF(SPI_TypeDef * SPIx)765 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
766 {
767 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
768 }
769
770 /**
771 * @brief Get overrun error flag
772 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
773 * @param SPIx SPI Instance
774 * @retval State of bit (1 or 0).
775 */
LL_SPI_IsActiveFlag_OVR(SPI_TypeDef * SPIx)776 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
777 {
778 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
779 }
780
781 /**
782 * @brief Get busy flag
783 * @note The BSY flag is cleared under any one of the following conditions:
784 * -When the SPI is correctly disabled
785 * -When a fault is detected in Master mode (MODF bit set to 1)
786 * -In Master mode, when it finishes a data transmission and no new data is ready to be
787 * sent
788 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
789 * each data transfer.
790 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
791 * @param SPIx SPI Instance
792 * @retval State of bit (1 or 0).
793 */
LL_SPI_IsActiveFlag_BSY(SPI_TypeDef * SPIx)794 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
795 {
796 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
797 }
798
799 /**
800 * @brief Get frame format error flag
801 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
802 * @param SPIx SPI Instance
803 * @retval State of bit (1 or 0).
804 */
LL_SPI_IsActiveFlag_FRE(SPI_TypeDef * SPIx)805 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
806 {
807 return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
808 }
809
810 /**
811 * @brief Clear CRC error flag
812 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
813 * @param SPIx SPI Instance
814 * @retval None
815 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)816 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
817 {
818 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
819 }
820
821 /**
822 * @brief Clear mode fault error flag
823 * @note Clearing this flag is done by a read access to the SPIx_SR
824 * register followed by a write access to the SPIx_CR1 register
825 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
826 * @param SPIx SPI Instance
827 * @retval None
828 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)829 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
830 {
831 __IO uint32_t tmpreg_sr;
832 tmpreg_sr = SPIx->SR;
833 (void) tmpreg_sr;
834 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
835 }
836
837 /**
838 * @brief Clear overrun error flag
839 * @note Clearing this flag is done by a read access to the SPIx_DR
840 * register followed by a read access to the SPIx_SR register
841 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
842 * @param SPIx SPI Instance
843 * @retval None
844 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)845 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
846 {
847 __IO uint32_t tmpreg;
848 tmpreg = SPIx->DR;
849 (void) tmpreg;
850 tmpreg = SPIx->SR;
851 (void) tmpreg;
852 }
853
854 /**
855 * @brief Clear frame format error flag
856 * @note Clearing this flag is done by reading SPIx_SR register
857 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
858 * @param SPIx SPI Instance
859 * @retval None
860 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)861 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
862 {
863 __IO uint32_t tmpreg;
864 tmpreg = SPIx->SR;
865 (void) tmpreg;
866 }
867
868 /**
869 * @}
870 */
871
872 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
873 * @{
874 */
875
876 /**
877 * @brief Enable error interrupt
878 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
879 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
880 * @param SPIx SPI Instance
881 * @retval None
882 */
LL_SPI_EnableIT_ERR(SPI_TypeDef * SPIx)883 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
884 {
885 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
886 }
887
888 /**
889 * @brief Enable Rx buffer not empty interrupt
890 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
891 * @param SPIx SPI Instance
892 * @retval None
893 */
LL_SPI_EnableIT_RXNE(SPI_TypeDef * SPIx)894 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
895 {
896 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
897 }
898
899 /**
900 * @brief Enable Tx buffer empty interrupt
901 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
902 * @param SPIx SPI Instance
903 * @retval None
904 */
LL_SPI_EnableIT_TXE(SPI_TypeDef * SPIx)905 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
906 {
907 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
908 }
909
910 /**
911 * @brief Disable error interrupt
912 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
913 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
914 * @param SPIx SPI Instance
915 * @retval None
916 */
LL_SPI_DisableIT_ERR(SPI_TypeDef * SPIx)917 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
918 {
919 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
920 }
921
922 /**
923 * @brief Disable Rx buffer not empty interrupt
924 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
925 * @param SPIx SPI Instance
926 * @retval None
927 */
LL_SPI_DisableIT_RXNE(SPI_TypeDef * SPIx)928 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
929 {
930 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
931 }
932
933 /**
934 * @brief Disable Tx buffer empty interrupt
935 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
936 * @param SPIx SPI Instance
937 * @retval None
938 */
LL_SPI_DisableIT_TXE(SPI_TypeDef * SPIx)939 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
940 {
941 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
942 }
943
944 /**
945 * @brief Check if error interrupt is enabled
946 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
947 * @param SPIx SPI Instance
948 * @retval State of bit (1 or 0).
949 */
LL_SPI_IsEnabledIT_ERR(SPI_TypeDef * SPIx)950 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
951 {
952 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
953 }
954
955 /**
956 * @brief Check if Rx buffer not empty interrupt is enabled
957 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
958 * @param SPIx SPI Instance
959 * @retval State of bit (1 or 0).
960 */
LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef * SPIx)961 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
962 {
963 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
964 }
965
966 /**
967 * @brief Check if Tx buffer empty interrupt
968 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
969 * @param SPIx SPI Instance
970 * @retval State of bit (1 or 0).
971 */
LL_SPI_IsEnabledIT_TXE(SPI_TypeDef * SPIx)972 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
973 {
974 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
975 }
976
977 /**
978 * @}
979 */
980
981 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
982 * @{
983 */
984
985 /**
986 * @brief Enable DMA Rx
987 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
988 * @param SPIx SPI Instance
989 * @retval None
990 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)991 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
992 {
993 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
994 }
995
996 /**
997 * @brief Disable DMA Rx
998 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
999 * @param SPIx SPI Instance
1000 * @retval None
1001 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)1002 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1003 {
1004 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1005 }
1006
1007 /**
1008 * @brief Check if DMA Rx is enabled
1009 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1010 * @param SPIx SPI Instance
1011 * @retval State of bit (1 or 0).
1012 */
LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)1013 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1014 {
1015 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
1016 }
1017
1018 /**
1019 * @brief Enable DMA Tx
1020 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1021 * @param SPIx SPI Instance
1022 * @retval None
1023 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)1024 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1025 {
1026 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1027 }
1028
1029 /**
1030 * @brief Disable DMA Tx
1031 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1032 * @param SPIx SPI Instance
1033 * @retval None
1034 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)1035 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1036 {
1037 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1038 }
1039
1040 /**
1041 * @brief Check if DMA Tx is enabled
1042 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1043 * @param SPIx SPI Instance
1044 * @retval State of bit (1 or 0).
1045 */
LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)1046 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1047 {
1048 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
1049 }
1050
1051 /**
1052 * @brief Get the data register address used for DMA transfer
1053 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1054 * @param SPIx SPI Instance
1055 * @retval Address of data register
1056 */
LL_SPI_DMA_GetRegAddr(SPI_TypeDef * SPIx)1057 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1058 {
1059 return (uint32_t) &(SPIx->DR);
1060 }
1061
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1067 * @{
1068 */
1069
1070 /**
1071 * @brief Read 8-Bits in the data register
1072 * @rmtoll DR DR LL_SPI_ReceiveData8
1073 * @param SPIx SPI Instance
1074 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1075 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)1076 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1077 {
1078 return (uint8_t)(READ_REG(SPIx->DR));
1079 }
1080
1081 /**
1082 * @brief Read 16-Bits in the data register
1083 * @rmtoll DR DR LL_SPI_ReceiveData16
1084 * @param SPIx SPI Instance
1085 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1086 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)1087 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1088 {
1089 return (uint16_t)(READ_REG(SPIx->DR));
1090 }
1091
1092 /**
1093 * @brief Write 8-Bits in the data register
1094 * @rmtoll DR DR LL_SPI_TransmitData8
1095 * @param SPIx SPI Instance
1096 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1097 * @retval None
1098 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)1099 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1100 {
1101 #if defined (__GNUC__)
1102 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
1103 *spidr = TxData;
1104 #else
1105 *((__IO uint8_t *)&SPIx->DR) = TxData;
1106 #endif /* __GNUC__ */
1107 }
1108
1109 /**
1110 * @brief Write 16-Bits in the data register
1111 * @rmtoll DR DR LL_SPI_TransmitData16
1112 * @param SPIx SPI Instance
1113 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1114 * @retval None
1115 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1116 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1117 {
1118 #if defined (__GNUC__)
1119 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
1120 *spidr = TxData;
1121 #else
1122 SPIx->DR = TxData;
1123 #endif /* __GNUC__ */
1124 }
1125
1126 /**
1127 * @}
1128 */
1129 #if defined(USE_FULL_LL_DRIVER)
1130 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1131 * @{
1132 */
1133
1134 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1135 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1136 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1137
1138 /**
1139 * @}
1140 */
1141 #endif /* USE_FULL_LL_DRIVER */
1142 /**
1143 * @}
1144 */
1145
1146 /**
1147 * @}
1148 */
1149
1150 /** @defgroup I2S_LL I2S
1151 * @{
1152 */
1153
1154 /* Private variables ---------------------------------------------------------*/
1155 /* Private constants ---------------------------------------------------------*/
1156 /* Private macros ------------------------------------------------------------*/
1157
1158 /* Exported types ------------------------------------------------------------*/
1159 #if defined(USE_FULL_LL_DRIVER)
1160 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1161 * @{
1162 */
1163
1164 /**
1165 * @brief I2S Init structure definition
1166 */
1167
1168 typedef struct
1169 {
1170 uint32_t Mode; /*!< Specifies the I2S operating mode.
1171 This parameter can be a value of @ref I2S_LL_EC_MODE
1172
1173 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1174
1175 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1176 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1177
1178 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1179
1180
1181 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1182 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1183
1184 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1185
1186
1187 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1188 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1189
1190 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1191
1192
1193 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1194 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1195
1196 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1197 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1198
1199
1200 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1201 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1202
1203 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1204
1205 } LL_I2S_InitTypeDef;
1206
1207 /**
1208 * @}
1209 */
1210 #endif /*USE_FULL_LL_DRIVER*/
1211
1212 /* Exported constants --------------------------------------------------------*/
1213 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1214 * @{
1215 */
1216
1217 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1218 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1219 * @{
1220 */
1221 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1222 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1223 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1224 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1225 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1226 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1227 /**
1228 * @}
1229 */
1230
1231 /** @defgroup SPI_LL_EC_IT IT Defines
1232 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1233 * @{
1234 */
1235 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1236 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1237 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1238 /**
1239 * @}
1240 */
1241
1242 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1243 * @{
1244 */
1245 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
1246 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
1247 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
1248 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1254 * @{
1255 */
1256 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1257 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1263 * @{
1264 */
1265 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1266 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1267 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1268 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1269 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1270 /**
1271 * @}
1272 */
1273
1274 /** @defgroup I2S_LL_EC_MODE Operation Mode
1275 * @{
1276 */
1277 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1278 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1279 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1280 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1281 /**
1282 * @}
1283 */
1284
1285 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1286 * @{
1287 */
1288 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1289 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1290 /**
1291 * @}
1292 */
1293
1294 #if defined(USE_FULL_LL_DRIVER)
1295
1296 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1297 * @{
1298 */
1299 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1300 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1306 * @{
1307 */
1308
1309 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1310 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1311 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1312 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1313 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1314 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1315 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1316 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1317 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1318 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1319 /**
1320 * @}
1321 */
1322 #endif /* USE_FULL_LL_DRIVER */
1323
1324 /**
1325 * @}
1326 */
1327
1328 /* Exported macro ------------------------------------------------------------*/
1329 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1330 * @{
1331 */
1332
1333 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1334 * @{
1335 */
1336
1337 /**
1338 * @brief Write a value in I2S register
1339 * @param __INSTANCE__ I2S Instance
1340 * @param __REG__ Register to be written
1341 * @param __VALUE__ Value to be written in the register
1342 * @retval None
1343 */
1344 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1345
1346 /**
1347 * @brief Read a value in I2S register
1348 * @param __INSTANCE__ I2S Instance
1349 * @param __REG__ Register to be read
1350 * @retval Register value
1351 */
1352 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1353 /**
1354 * @}
1355 */
1356
1357 /**
1358 * @}
1359 */
1360
1361
1362 /* Exported functions --------------------------------------------------------*/
1363
1364 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1365 * @{
1366 */
1367
1368 /** @defgroup I2S_LL_EF_Configuration Configuration
1369 * @{
1370 */
1371
1372 /**
1373 * @brief Select I2S mode and Enable I2S peripheral
1374 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1375 * I2SCFGR I2SE LL_I2S_Enable
1376 * @param SPIx SPI Instance
1377 * @retval None
1378 */
LL_I2S_Enable(SPI_TypeDef * SPIx)1379 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1380 {
1381 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1382 }
1383
1384 /**
1385 * @brief Disable I2S peripheral
1386 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1387 * @param SPIx SPI Instance
1388 * @retval None
1389 */
LL_I2S_Disable(SPI_TypeDef * SPIx)1390 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1391 {
1392 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1393 }
1394
1395 /**
1396 * @brief Check if I2S peripheral is enabled
1397 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1398 * @param SPIx SPI Instance
1399 * @retval State of bit (1 or 0).
1400 */
LL_I2S_IsEnabled(SPI_TypeDef * SPIx)1401 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1402 {
1403 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
1404 }
1405
1406 /**
1407 * @brief Set I2S data frame length
1408 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1409 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1410 * @param SPIx SPI Instance
1411 * @param DataFormat This parameter can be one of the following values:
1412 * @arg @ref LL_I2S_DATAFORMAT_16B
1413 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1414 * @arg @ref LL_I2S_DATAFORMAT_24B
1415 * @arg @ref LL_I2S_DATAFORMAT_32B
1416 * @retval None
1417 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataFormat)1418 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1419 {
1420 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1421 }
1422
1423 /**
1424 * @brief Get I2S data frame length
1425 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1426 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1427 * @param SPIx SPI Instance
1428 * @retval Returned value can be one of the following values:
1429 * @arg @ref LL_I2S_DATAFORMAT_16B
1430 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1431 * @arg @ref LL_I2S_DATAFORMAT_24B
1432 * @arg @ref LL_I2S_DATAFORMAT_32B
1433 */
LL_I2S_GetDataFormat(SPI_TypeDef * SPIx)1434 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1435 {
1436 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1437 }
1438
1439 /**
1440 * @brief Set I2S clock polarity
1441 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1442 * @param SPIx SPI Instance
1443 * @param ClockPolarity This parameter can be one of the following values:
1444 * @arg @ref LL_I2S_POLARITY_LOW
1445 * @arg @ref LL_I2S_POLARITY_HIGH
1446 * @retval None
1447 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1448 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1449 {
1450 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1451 }
1452
1453 /**
1454 * @brief Get I2S clock polarity
1455 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1456 * @param SPIx SPI Instance
1457 * @retval Returned value can be one of the following values:
1458 * @arg @ref LL_I2S_POLARITY_LOW
1459 * @arg @ref LL_I2S_POLARITY_HIGH
1460 */
LL_I2S_GetClockPolarity(SPI_TypeDef * SPIx)1461 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1462 {
1463 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1464 }
1465
1466 /**
1467 * @brief Set I2S standard protocol
1468 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1469 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1470 * @param SPIx SPI Instance
1471 * @param Standard This parameter can be one of the following values:
1472 * @arg @ref LL_I2S_STANDARD_PHILIPS
1473 * @arg @ref LL_I2S_STANDARD_MSB
1474 * @arg @ref LL_I2S_STANDARD_LSB
1475 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1476 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1477 * @retval None
1478 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1479 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1480 {
1481 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1482 }
1483
1484 /**
1485 * @brief Get I2S standard protocol
1486 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1487 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1488 * @param SPIx SPI Instance
1489 * @retval Returned value can be one of the following values:
1490 * @arg @ref LL_I2S_STANDARD_PHILIPS
1491 * @arg @ref LL_I2S_STANDARD_MSB
1492 * @arg @ref LL_I2S_STANDARD_LSB
1493 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1494 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1495 */
LL_I2S_GetStandard(SPI_TypeDef * SPIx)1496 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1497 {
1498 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1499 }
1500
1501 /**
1502 * @brief Set I2S transfer mode
1503 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1504 * @param SPIx SPI Instance
1505 * @param Mode This parameter can be one of the following values:
1506 * @arg @ref LL_I2S_MODE_SLAVE_TX
1507 * @arg @ref LL_I2S_MODE_SLAVE_RX
1508 * @arg @ref LL_I2S_MODE_MASTER_TX
1509 * @arg @ref LL_I2S_MODE_MASTER_RX
1510 * @retval None
1511 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Mode)1512 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1513 {
1514 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1515 }
1516
1517 /**
1518 * @brief Get I2S transfer mode
1519 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1520 * @param SPIx SPI Instance
1521 * @retval Returned value can be one of the following values:
1522 * @arg @ref LL_I2S_MODE_SLAVE_TX
1523 * @arg @ref LL_I2S_MODE_SLAVE_RX
1524 * @arg @ref LL_I2S_MODE_MASTER_TX
1525 * @arg @ref LL_I2S_MODE_MASTER_RX
1526 */
LL_I2S_GetTransferMode(SPI_TypeDef * SPIx)1527 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1528 {
1529 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1530 }
1531
1532 /**
1533 * @brief Set I2S linear prescaler
1534 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1535 * @param SPIx SPI Instance
1536 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1537 * @retval None
1538 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint8_t PrescalerLinear)1539 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1540 {
1541 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1542 }
1543
1544 /**
1545 * @brief Get I2S linear prescaler
1546 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1547 * @param SPIx SPI Instance
1548 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1549 */
LL_I2S_GetPrescalerLinear(SPI_TypeDef * SPIx)1550 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1551 {
1552 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1553 }
1554
1555 /**
1556 * @brief Set I2S parity prescaler
1557 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1558 * @param SPIx SPI Instance
1559 * @param PrescalerParity This parameter can be one of the following values:
1560 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1561 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1562 * @retval None
1563 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)1564 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1565 {
1566 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1567 }
1568
1569 /**
1570 * @brief Get I2S parity prescaler
1571 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1572 * @param SPIx SPI Instance
1573 * @retval Returned value can be one of the following values:
1574 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1575 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1576 */
LL_I2S_GetPrescalerParity(SPI_TypeDef * SPIx)1577 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1578 {
1579 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1580 }
1581
1582 /**
1583 * @brief Enable the master clock ouput (Pin MCK)
1584 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1585 * @param SPIx SPI Instance
1586 * @retval None
1587 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)1588 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1589 {
1590 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1591 }
1592
1593 /**
1594 * @brief Disable the master clock ouput (Pin MCK)
1595 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1596 * @param SPIx SPI Instance
1597 * @retval None
1598 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)1599 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1600 {
1601 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1602 }
1603
1604 /**
1605 * @brief Check if the master clock ouput (Pin MCK) is enabled
1606 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1607 * @param SPIx SPI Instance
1608 * @retval State of bit (1 or 0).
1609 */
LL_I2S_IsEnabledMasterClock(SPI_TypeDef * SPIx)1610 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1611 {
1612 return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
1613 }
1614
1615 #if defined(SPI_I2SCFGR_ASTRTEN)
1616 /**
1617 * @brief Enable asynchronous start
1618 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
1619 * @param SPIx SPI Instance
1620 * @retval None
1621 */
LL_I2S_EnableAsyncStart(SPI_TypeDef * SPIx)1622 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
1623 {
1624 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1625 }
1626
1627 /**
1628 * @brief Disable asynchronous start
1629 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
1630 * @param SPIx SPI Instance
1631 * @retval None
1632 */
LL_I2S_DisableAsyncStart(SPI_TypeDef * SPIx)1633 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
1634 {
1635 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1636 }
1637
1638 /**
1639 * @brief Check if asynchronous start is enabled
1640 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
1641 * @param SPIx SPI Instance
1642 * @retval State of bit (1 or 0).
1643 */
LL_I2S_IsEnabledAsyncStart(SPI_TypeDef * SPIx)1644 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
1645 {
1646 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
1647 }
1648 #endif /* SPI_I2SCFGR_ASTRTEN */
1649
1650 /**
1651 * @}
1652 */
1653
1654 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1655 * @{
1656 */
1657
1658 /**
1659 * @brief Check if Rx buffer is not empty
1660 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1661 * @param SPIx SPI Instance
1662 * @retval State of bit (1 or 0).
1663 */
LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef * SPIx)1664 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1665 {
1666 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1667 }
1668
1669 /**
1670 * @brief Check if Tx buffer is empty
1671 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1672 * @param SPIx SPI Instance
1673 * @retval State of bit (1 or 0).
1674 */
LL_I2S_IsActiveFlag_TXE(SPI_TypeDef * SPIx)1675 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1676 {
1677 return LL_SPI_IsActiveFlag_TXE(SPIx);
1678 }
1679
1680 /**
1681 * @brief Get busy flag
1682 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1683 * @param SPIx SPI Instance
1684 * @retval State of bit (1 or 0).
1685 */
LL_I2S_IsActiveFlag_BSY(SPI_TypeDef * SPIx)1686 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1687 {
1688 return LL_SPI_IsActiveFlag_BSY(SPIx);
1689 }
1690
1691 /**
1692 * @brief Get overrun error flag
1693 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1694 * @param SPIx SPI Instance
1695 * @retval State of bit (1 or 0).
1696 */
LL_I2S_IsActiveFlag_OVR(SPI_TypeDef * SPIx)1697 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1698 {
1699 return LL_SPI_IsActiveFlag_OVR(SPIx);
1700 }
1701
1702 /**
1703 * @brief Get underrun error flag
1704 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1705 * @param SPIx SPI Instance
1706 * @retval State of bit (1 or 0).
1707 */
LL_I2S_IsActiveFlag_UDR(SPI_TypeDef * SPIx)1708 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1709 {
1710 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1711 }
1712
1713 /**
1714 * @brief Get frame format error flag
1715 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
1716 * @param SPIx SPI Instance
1717 * @retval State of bit (1 or 0).
1718 */
LL_I2S_IsActiveFlag_FRE(SPI_TypeDef * SPIx)1719 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1720 {
1721 return LL_SPI_IsActiveFlag_FRE(SPIx);
1722 }
1723
1724 /**
1725 * @brief Get channel side flag.
1726 * @note 0: Channel Left has to be transmitted or has been received\n
1727 * 1: Channel Right has to be transmitted or has been received\n
1728 * It has no significance in PCM mode.
1729 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1730 * @param SPIx SPI Instance
1731 * @retval State of bit (1 or 0).
1732 */
LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef * SPIx)1733 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
1734 {
1735 return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
1736 }
1737
1738 /**
1739 * @brief Clear overrun error flag
1740 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1741 * @param SPIx SPI Instance
1742 * @retval None
1743 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)1744 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1745 {
1746 LL_SPI_ClearFlag_OVR(SPIx);
1747 }
1748
1749 /**
1750 * @brief Clear underrun error flag
1751 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1752 * @param SPIx SPI Instance
1753 * @retval None
1754 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)1755 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1756 {
1757 __IO uint32_t tmpreg;
1758 tmpreg = SPIx->SR;
1759 (void)tmpreg;
1760 }
1761
1762 /**
1763 * @brief Clear frame format error flag
1764 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
1765 * @param SPIx SPI Instance
1766 * @retval None
1767 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)1768 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
1769 {
1770 LL_SPI_ClearFlag_FRE(SPIx);
1771 }
1772
1773 /**
1774 * @}
1775 */
1776
1777 /** @defgroup I2S_LL_EF_IT Interrupt Management
1778 * @{
1779 */
1780
1781 /**
1782 * @brief Enable error IT
1783 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1784 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1785 * @param SPIx SPI Instance
1786 * @retval None
1787 */
LL_I2S_EnableIT_ERR(SPI_TypeDef * SPIx)1788 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1789 {
1790 LL_SPI_EnableIT_ERR(SPIx);
1791 }
1792
1793 /**
1794 * @brief Enable Rx buffer not empty IT
1795 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1796 * @param SPIx SPI Instance
1797 * @retval None
1798 */
LL_I2S_EnableIT_RXNE(SPI_TypeDef * SPIx)1799 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1800 {
1801 LL_SPI_EnableIT_RXNE(SPIx);
1802 }
1803
1804 /**
1805 * @brief Enable Tx buffer empty IT
1806 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1807 * @param SPIx SPI Instance
1808 * @retval None
1809 */
LL_I2S_EnableIT_TXE(SPI_TypeDef * SPIx)1810 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1811 {
1812 LL_SPI_EnableIT_TXE(SPIx);
1813 }
1814
1815 /**
1816 * @brief Disable error IT
1817 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1818 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1819 * @param SPIx SPI Instance
1820 * @retval None
1821 */
LL_I2S_DisableIT_ERR(SPI_TypeDef * SPIx)1822 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1823 {
1824 LL_SPI_DisableIT_ERR(SPIx);
1825 }
1826
1827 /**
1828 * @brief Disable Rx buffer not empty IT
1829 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1830 * @param SPIx SPI Instance
1831 * @retval None
1832 */
LL_I2S_DisableIT_RXNE(SPI_TypeDef * SPIx)1833 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1834 {
1835 LL_SPI_DisableIT_RXNE(SPIx);
1836 }
1837
1838 /**
1839 * @brief Disable Tx buffer empty IT
1840 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1841 * @param SPIx SPI Instance
1842 * @retval None
1843 */
LL_I2S_DisableIT_TXE(SPI_TypeDef * SPIx)1844 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1845 {
1846 LL_SPI_DisableIT_TXE(SPIx);
1847 }
1848
1849 /**
1850 * @brief Check if ERR IT is enabled
1851 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1852 * @param SPIx SPI Instance
1853 * @retval State of bit (1 or 0).
1854 */
LL_I2S_IsEnabledIT_ERR(SPI_TypeDef * SPIx)1855 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1856 {
1857 return LL_SPI_IsEnabledIT_ERR(SPIx);
1858 }
1859
1860 /**
1861 * @brief Check if RXNE IT is enabled
1862 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1863 * @param SPIx SPI Instance
1864 * @retval State of bit (1 or 0).
1865 */
LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef * SPIx)1866 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1867 {
1868 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1869 }
1870
1871 /**
1872 * @brief Check if TXE IT is enabled
1873 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1874 * @param SPIx SPI Instance
1875 * @retval State of bit (1 or 0).
1876 */
LL_I2S_IsEnabledIT_TXE(SPI_TypeDef * SPIx)1877 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1878 {
1879 return LL_SPI_IsEnabledIT_TXE(SPIx);
1880 }
1881
1882 /**
1883 * @}
1884 */
1885
1886 /** @defgroup I2S_LL_EF_DMA DMA Management
1887 * @{
1888 */
1889
1890 /**
1891 * @brief Enable DMA Rx
1892 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1893 * @param SPIx SPI Instance
1894 * @retval None
1895 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)1896 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1897 {
1898 LL_SPI_EnableDMAReq_RX(SPIx);
1899 }
1900
1901 /**
1902 * @brief Disable DMA Rx
1903 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1904 * @param SPIx SPI Instance
1905 * @retval None
1906 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)1907 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1908 {
1909 LL_SPI_DisableDMAReq_RX(SPIx);
1910 }
1911
1912 /**
1913 * @brief Check if DMA Rx is enabled
1914 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1915 * @param SPIx SPI Instance
1916 * @retval State of bit (1 or 0).
1917 */
LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)1918 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1919 {
1920 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1921 }
1922
1923 /**
1924 * @brief Enable DMA Tx
1925 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1926 * @param SPIx SPI Instance
1927 * @retval None
1928 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)1929 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1930 {
1931 LL_SPI_EnableDMAReq_TX(SPIx);
1932 }
1933
1934 /**
1935 * @brief Disable DMA Tx
1936 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1937 * @param SPIx SPI Instance
1938 * @retval None
1939 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)1940 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1941 {
1942 LL_SPI_DisableDMAReq_TX(SPIx);
1943 }
1944
1945 /**
1946 * @brief Check if DMA Tx is enabled
1947 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1948 * @param SPIx SPI Instance
1949 * @retval State of bit (1 or 0).
1950 */
LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)1951 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1952 {
1953 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1954 }
1955
1956 /**
1957 * @}
1958 */
1959
1960 /** @defgroup I2S_LL_EF_DATA DATA Management
1961 * @{
1962 */
1963
1964 /**
1965 * @brief Read 16-Bits in data register
1966 * @rmtoll DR DR LL_I2S_ReceiveData16
1967 * @param SPIx SPI Instance
1968 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1969 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)1970 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1971 {
1972 return LL_SPI_ReceiveData16(SPIx);
1973 }
1974
1975 /**
1976 * @brief Write 16-Bits in data register
1977 * @rmtoll DR DR LL_I2S_TransmitData16
1978 * @param SPIx SPI Instance
1979 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1980 * @retval None
1981 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1982 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1983 {
1984 LL_SPI_TransmitData16(SPIx, TxData);
1985 }
1986
1987 /**
1988 * @}
1989 */
1990
1991 #if defined(USE_FULL_LL_DRIVER)
1992 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
1993 * @{
1994 */
1995
1996 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
1997 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
1998 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
1999 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
2000 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
2001 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
2002 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
2003
2004 /**
2005 * @}
2006 */
2007 #endif /* USE_FULL_LL_DRIVER */
2008
2009 /**
2010 * @}
2011 */
2012
2013 /**
2014 * @}
2015 */
2016
2017 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
2018
2019 /**
2020 * @}
2021 */
2022
2023 #ifdef __cplusplus
2024 }
2025 #endif
2026
2027 #endif /* STM32F4xx_LL_SPI_H */
2028
2029 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2030