1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* 4 * AMD I/O Virtualization Technology (IOMMU) 5 * Specification 48882-Rev 2.62-February 2015 6 * 7 * from http://www.uefi.org/acpi 8 * I/O Virtualization Reporting Structure (IVRS) 9 */ 10 11 #ifndef __ACPI_ACPI_IVRS_H__ 12 #define __ACPI_ACPI_IVRS_H__ 13 14 #include <stdint.h> 15 16 /* I/O Virtualization Reporting Structure (IVRS) */ 17 #define IVHD_BLOCK_TYPE_LEGACY__FIXED 0x10 18 #define IVHD_BLOCK_TYPE_FULL__FIXED 0x11 19 #define IVHD_BLOCK_TYPE_FULL__ACPI_HID 0x40 20 21 /* IVRS Revision Field */ 22 #define IVRS_FORMAT_FIXED 0x01 /* Type 10h & 11h only */ 23 #define IVRS_FORMAT_MIXED 0x02 /* Type 10h, 11h, & 40h */ 24 25 /* IVRS IVinfo Field */ 26 /* ATS response address range reserved */ 27 #define IVINFO_HT_ATS_RESERVED (1 << 22) 28 29 /* Virtual Address size - All other values are reserved */ 30 #define IVINFO_VA_SIZE_32_BITS (0x20 << 15) 31 #define IVINFO_VA_SIZE_40_BITS (0x28 << 15) 32 #define IVINFO_VA_SIZE_48_BITS (0x30 << 15) 33 #define IVINFO_VA_SIZE_64_BITS (0x40 << 15) 34 35 /* Physical Address size - All other values are reserved */ 36 #define IVINFO_PA_SIZE_40_BITS (0x28 << 8) 37 #define IVINFO_PA_SIZE_48_BITS (0x30 << 8) 38 #define IVINFO_PA_SIZE_52_BITS (0x34 << 8) 39 40 /* Guest Virtual Address size - All other values are reserved */ 41 #define IVINFO_GVA_SIZE_48_BITS (0x02 << 5) 42 43 /* Extended Feature Support */ 44 #define IVINFO_EFR_SUPPORTED 0x01 45 #define EFR_FEATURE_SUP (1 << 27) 46 47 /* IVHD Flags Field */ 48 #define IVHD_FLAG_PPE_SUP (1 << 7) /* Type 10h only */ 49 #define IVHD_FLAG_PREF_SUP (1 << 6) /* Type 10h only */ 50 #define IVHD_FLAG_COHERENT (1 << 5) 51 #define IVHD_FLAG_IOTLB_SUP (1 << 4) 52 #define IVHD_FLAG_ISOC (1 << 3) 53 #define IVHD_FLAG_RES_PASS_PW (1 << 2) 54 #define IVHD_FLAG_PASS_PW (1 << 1) 55 #define IVHD_FLAG_HT_TUN_EN (1 << 0) 56 57 /* IVHD IOMMU Info Field */ 58 #define IOMMU_INFO_UNIT_ID_SHIFT 8 59 60 /* IVHD IOMMU Feature Reporting Field */ 61 #define IOMMU_FEATURE_HATS_SHIFT 30 /* Type 10h only */ 62 #define IOMMU_FEATURE_GATS_SHIFT 28 /* Type 10h only */ 63 #define IOMMU_FEATURE_MSI_NUM_PPR_SHIFT 23 64 #define IOMMU_FEATURE_PN_BANKS_SHIFT 17 65 #define IOMMU_FEATURE_PN_COUNTERS_SHIFT 13 66 #define IOMMU_FEATURE_PA_SMAX_SHIFT 8 /* Type 10h only */ 67 #define IOMMU_FEATURE_GLX_SHIFT 3 68 69 #define IOMMU_FEATURE_HE_SUP (1 << 7) /* Type 10h only */ 70 #define IOMMU_FEATURE_GA_SUP (1 << 6) /* Type 10h only */ 71 #define IOMMU_FEATURE_IA_SUP (1 << 5) /* Type 10h only */ 72 #define IOMMU_FEATURE_GLX_SINGLE_LEVEL (0 << 3) /* Type 10h only */ 73 #define IOMMU_FEATURE_GLX_TWO_LEVEL (1 << 3) /* Type 10h only */ 74 #define IOMMU_FEATURE_GLX_THREE_LEVEL (2 << 3) /* Type 10h only */ 75 #define IOMMU_FEATURE_GT_SUP (1 << 2) /* Type 10h only */ 76 #define IOMMU_FEATURE_NX_SUP (1 << 1) /* Type 10h only */ 77 #define IOMMU_FEATURE_XT_SUP (1 << 0) 78 79 /* IVHD Device Entry Type Codes */ 80 #define IVHD_DEV_4_BYTE_ALL 0x01 81 #define IVHD_DEV_4_BYTE_SELECT 0x02 82 #define IVHD_DEV_4_BYTE_START_RANGE 0x03 83 #define IVHD_DEV_4_BYTE_END_RANGE 0x04 84 #define IVHD_DEV_8_BYTE_ALIAS_SELECT 0x42 85 #define IVHD_DEV_8_BYTE_ALIAS_START_RANGE 0x43 86 #define IVHD_DEV_8_BYTE_EXT_SELECT 0x46 87 #define IVHD_DEV_8_BYTE_EXT_START_RANGE 0x47 88 #define IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV 0x48 89 #define IVHD_DEV_VARIABLE 0xF0 90 91 /* IVHD Device Table Entry (DTE) Settings */ 92 #define IVHD_DTE_LINT_1_PASS (1 << 7) 93 #define IVHD_DTE_LINT_0_PASS (1 << 6) 94 #define IVHD_DTE_SYS_MGT_TGT_ABT (0 << 4) 95 #define IVHD_DTE_SYS_MGT_NO_TRANS (1 << 4) 96 #define IVHD_DTE_SYS_MGT_INTX_NO_TRANS (2 << 4) 97 #define IVHD_DTE_SYS_MGT_TRANS (3 << 4) 98 #define IVHD_DTE_NMI_PASS (1 << 2) 99 #define IVHD_DTE_EXT_INT_PASS (1 << 1) 100 #define IVHD_DTE_INIT_PASS (1 << 0) 101 102 /* IVHD Device Entry Extended DTE Setting Field */ 103 #define IVHD_DEV_EXT_ATS_DISABLE (1 << 31) 104 105 /* IVHD Special Device Entry Variety Field */ 106 #define IVHD_SPECIAL_DEV_IOAPIC 0x01 107 #define IVHD_SPECIAL_DEV_HPET 0x02 108 109 /* Device EntryType F0h UID Format */ 110 #define IVHD_UID_NOT_PRESENT 0x00 111 #define IVHD_UID_INT 0x01 112 #define IVHD_UID_STRING 0x02 113 114 #define IOMMU_CAP_ID 0x0f 115 116 /* MMIO Offset 0x30: IOMMU Extended Feature Register */ 117 #define MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT 0 118 #define MMIO_EXT_FEATURE_PRE_F_SUP (0x1 << MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT) 119 #define MMIO_EXT_FEATURE_PPR_SUP_SHIFT 1 120 #define MMIO_EXT_FEATURE_PPR_SUP (0x1 << MMIO_EXT_FEATURE_PPR_SUP_SHIFT) 121 #define MMIO_EXT_FEATURE_XT_SUP_SHIFT 2 122 #define MMIO_EXT_FEATURE_XT_SUP (0x1 << MMIO_EXT_FEATURE_XT_SUP_SHIFT) 123 #define MMIO_EXT_FEATURE_NX_SUP_SHIFT 3 124 #define MMIO_EXT_FEATURE_NX_SUP (0x1 << MMIO_EXT_FEATURE_NX_SUP_SHIFT) 125 #define MMIO_EXT_FEATURE_GT_SUP_SHIFT 4 126 #define MMIO_EXT_FEATURE_GT_SUP (0x1 << MMIO_EXT_FEATURE_GT_SUP_SHIFT) 127 #define MMIO_EXT_FEATURE_IA_SUP_SHIFT 6 128 #define MMIO_EXT_FEATURE_IA_SUP (0x1 << MMIO_EXT_FEATURE_IA_SUP_SHIFT) 129 #define MMIO_EXT_FEATURE_GA_SUP_SHIFT 7 130 #define MMIO_EXT_FEATURE_GA_SUP (0x1 << MMIO_EXT_FEATURE_GA_SUP_SHIFT) 131 #define MMIO_EXT_FEATURE_HE_SUP_SHIFT 8 132 #define MMIO_EXT_FEATURE_HE_SUP (0x1 << MMIO_EXT_FEATURE_HE_SUP_SHIFT) 133 #define MMIO_EXT_FEATURE_PC_SUP_SHIFT 9 134 #define MMIO_EXT_FEATURE_PC_SUP (0x1 << MMIO_EXT_FEATURE_PC_SUP_SHIFT) 135 #define MMIO_EXT_FEATURE_HATS_SHIFT 10 136 #define MMIO_EXT_FEATURE_HATS_MASK (0x3 << MMIO_EXT_FEATURE_HATS_SHIFT) 137 #define MMIO_EXT_FEATURE_GATS_SHIFT 12 138 #define MMIO_EXT_FEATURE_GATS_MASK (0x3 << MMIO_EXT_FEATURE_GATS_SHIFT) 139 #define MMIO_EXT_FEATURE_GLX_SHIFT 14 140 #define MMIO_EXT_FEATURE_GLX_SUP_MASK (0x3 << MMIO_EXT_FEATURE_GLX_SHIFT) 141 #define MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT 16 142 #define MMIO_EXT_FEATURE_SMI_F_SUP_MASK (0x3 << MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT) 143 #define MMIO_EXT_FEATURE_SMI_FRC_SHIFT 18 144 #define MMIO_EXT_FEATURE_SMI_FRC_MASK (0x7 << MMIO_EXT_FEATURE_SMI_FRC_SHIFT) 145 #define MMIO_EXT_FEATURE_GAM_SUP_SHIFT 21 146 #define MMIO_EXT_FEATURE_GAM_SUP_MASK (0x7 << MMIO_EXT_FEATURE_GAM_SUP_SHIFT) 147 #define MMIO_EXT_FEATURE_PAS_MAX_SHIFT 32 148 #define MMIO_EXT_FEATURE_PAS_MAX_MASK (0x1fULL << MMIO_EXT_FEATURE_PAS_MAX_SHIFT) 149 150 /* MMIO Offset 0x18: IOMMU Control Register */ 151 #define MMIO_CTRL_IOMMU_EN (1 << 0) 152 #define MMIO_CTRL_HT_TUN_EN (1 << 1) 153 #define MMIO_CTRL_PASS_PW (1 << 8) 154 #define MMIO_CTRL_RES_PASS_PW (1 << 9) 155 #define MMIO_CTRL_COHERENT (1 << 10) 156 #define MMIO_CTRL_ISOC (1 << 11) 157 158 /* MMIO Offset 0x4000: Counter Configuration Register */ 159 #define MMIO_CNT_CFG_N_CNT_BANKS_SHIFT 12 160 #define MMIO_CNT_CFG_N_COUNTER_BANKS (0x3f << MMIO_CNT_CFG_N_CNT_BANKS_SHIFT) 161 #define MMIO_CNT_CFG_N_COUNTER_SHIFT 7 162 #define MMIO_CNT_CFG_N_COUNTER (0xf << MMIO_CNT_CFG_N_COUNTER_SHIFT) 163 164 /* Capability offset 0 */ 165 #define CAP_OFFSET_0_IOTLB_SP_SHIFT 24 166 #define CAP_OFFSET_0_IOTLB_SP (1 << CAP_OFFSET_0_IOTLB_SP_SHIFT) 167 168 /// Capability offset 10h 169 #define CAP_OFFSET_10_MSI_NUM_PPR_SHIFT 27 170 #define CAP_OFFSET_10_MSI_NUM_PPR (0x1f << CAP_OFFSET_10_MSI_NUM_PPR_SHIFT) 171 172 /* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ 173 typedef struct ivrs_ivhd_generic { 174 uint8_t type; 175 uint16_t dev_id; 176 uint8_t dte_setting; 177 } __packed ivrs_ivhd_generic_t; 178 179 /* IVHD (I/O Virtualization Hardware Definition Block) 8-byte entries */ 180 typedef struct ivrs_ivhd_alias { 181 uint8_t type; 182 uint16_t dev_id; 183 uint8_t dte_setting; 184 uint8_t reserved1; 185 uint16_t source_dev_id; 186 uint8_t reserved2; 187 } __packed ivrs_ivhd_alias_t; 188 189 /* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 40h */ 190 typedef struct acpi_ivrs_ivhd_40 { 191 uint8_t type; 192 uint8_t flags; 193 uint16_t length; 194 uint16_t device_id; 195 uint16_t capability_offset; 196 uint32_t iommu_base_low; 197 uint32_t iommu_base_high; 198 uint16_t pci_segment_group; 199 uint16_t iommu_info; 200 uint32_t iommu_attributes; 201 uint32_t efr_reg_image_low; 202 uint32_t efr_reg_image_high; 203 uint32_t reserved[2]; 204 uint8_t entry[]; 205 } __packed acpi_ivrs_ivhd40_t; 206 207 typedef struct ivrs_ivhd_extended { 208 uint8_t type; 209 uint16_t dev_id; 210 uint8_t dte_setting; 211 uint32_t extended_dte_setting; 212 } __packed ivrs_ivhd_extended_t; 213 214 typedef struct ivrs_ivhd_special { 215 uint8_t type; 216 uint16_t reserved; 217 uint8_t dte_setting; 218 uint8_t handle; 219 uint16_t source_dev_id; 220 uint8_t variety; 221 } __packed ivrs_ivhd_special_t; 222 223 typedef struct ivrs_ivhd_f0_entry { 224 uint8_t type; 225 uint16_t dev_id; 226 uint8_t dte_setting; 227 uint8_t hardware_id[8]; 228 uint8_t compatible_id[8]; 229 uint8_t uuid_format; 230 uint8_t uuid_length; 231 } __packed ivrs_ivhd_f0_entry_t; 232 233 #endif /* __ACPI_ACPI_IVRS_H__ */ 234