1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _input_system_ctrl_defs_h 8 #define _input_system_ctrl_defs_h 9 10 #define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */ 11 12 /* --------------------------------------------------*/ 13 14 /* --------------------------------------------------*/ 15 /* REGISTER INFO */ 16 /* --------------------------------------------------*/ 17 18 // Number of registers 19 #define ISYS_CTRL_NOF_REGS 23 20 21 // Register id's of MMIO slave accessible registers 22 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0 23 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1 24 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2 25 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3 26 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4 27 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5 28 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6 29 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7 30 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8 31 #define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9 32 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10 33 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11 34 #define ISYS_CTRL_INIT_REG_ID 12 35 #define ISYS_CTRL_LAST_COMMAND_REG_ID 13 36 #define ISYS_CTRL_NEXT_COMMAND_REG_ID 14 37 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15 38 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16 39 #define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17 40 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18 41 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19 42 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20 43 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21 44 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22 45 46 /* register reset value */ 47 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0 48 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0 49 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0 50 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128 51 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128 52 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128 53 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3 54 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3 55 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3 56 #define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0 57 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 58 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 59 #define ISYS_CTRL_INIT_REG_RSTVAL 0 60 #define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) 61 #define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) 62 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) 63 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) 64 #define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0 65 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0 66 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0 67 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0 68 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0 69 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0 70 71 /* register width value */ 72 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9 73 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9 74 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9 75 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9 76 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9 77 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9 78 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9 79 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9 80 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9 81 #define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9 82 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9 83 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 84 #define ISYS_CTRL_INIT_REG_WIDTH 3 85 #define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */ 86 #define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32 87 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32 88 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32 89 #define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32 90 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32 91 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32 92 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32 93 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32 94 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1 95 96 /* bit definitions */ 97 98 /* --------------------------------------------------*/ 99 /* TOKEN INFO */ 100 /* --------------------------------------------------*/ 101 102 /* 103 InpSysCaptFramesAcq 1/0 [3:0] - 'b0000 104 [7:4] - CaptPortId, 105 CaptA-'b0000 106 CaptB-'b0001 107 CaptC-'b0010 108 [31:16] - NOF_frames 109 InpSysCaptFrameExt 2/0 [3:0] - 'b0001' 110 [7:4] - CaptPortId, 111 'b0000 - CaptA 112 'b0001 - CaptB 113 'b0010 - CaptC 114 115 2/1 [31:0] - external capture address 116 InpSysAcqFrame 2/0 [3:0] - 'b0010, 117 [31:4] - NOF_ext_mem_words 118 2/1 [31:0] - external memory read start address 119 InpSysOverruleON 1/0 [3:0] - 'b0011, 120 [7:4] - overrule port id (opid) 121 'b0000 - CaptA 122 'b0001 - CaptB 123 'b0010 - CaptC 124 'b0011 - Acq 125 'b0100 - DMA 126 127 InpSysOverruleOFF 1/0 [3:0] - 'b0100, 128 [7:4] - overrule port id (opid) 129 'b0000 - CaptA 130 'b0001 - CaptB 131 'b0010 - CaptC 132 'b0011 - Acq 133 'b0100 - DMA 134 135 InpSysOverruleCmd 2/0 [3:0] - 'b0101, 136 [7:4] - overrule port id (opid) 137 'b0000 - CaptA 138 'b0001 - CaptB 139 'b0010 - CaptC 140 'b0011 - Acq 141 'b0100 - DMA 142 143 2/1 [31:0] - command token value for port opid 144 145 acknowledge tokens: 146 147 InpSysAckCFA 1/0 [3:0] - 'b0000 148 [7:4] - CaptPortId, 149 CaptA-'b0000 150 CaptB- 'b0001 151 CaptC-'b0010 152 [31:16] - NOF_frames 153 InpSysAckCFE 1/0 [3:0] - 'b0001' 154 [7:4] - CaptPortId, 155 'b0000 - CaptA 156 'b0001 - CaptB 157 'b0010 - CaptC 158 159 InpSysAckAF 1/0 [3:0] - 'b0010 160 InpSysAckOverruleON 1/0 [3:0] - 'b0011, 161 [7:4] - overrule port id (opid) 162 'b0000 - CaptA 163 'b0001 - CaptB 164 'b0010 - CaptC 165 'b0011 - Acq 166 'b0100 - DMA 167 168 InpSysAckOverruleOFF 1/0 [3:0] - 'b0100, 169 [7:4] - overrule port id (opid) 170 'b0000 - CaptA 171 'b0001 - CaptB 172 'b0010 - CaptC 173 'b0011 - Acq 174 'b0100 - DMA 175 176 InpSysAckOverrule 2/0 [3:0] - 'b0101, 177 [7:4] - overrule port id (opid) 178 'b0000 - CaptA 179 'b0001 - CaptB 180 'b0010 - CaptC 181 'b0011 - Acq 182 'b0100 - DMA 183 184 2/1 [31:0] - acknowledge token value from port opid 185 186 */ 187 188 /* Command and acknowledge tokens IDs */ 189 #define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */ 190 #define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */ 191 #define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */ 192 #define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */ 193 #define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */ 194 #define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */ 195 196 #define ISYS_CTRL_ACK_CFA_TOKEN_ID 0 197 #define ISYS_CTRL_ACK_CFE_TOKEN_ID 1 198 #define ISYS_CTRL_ACK_AF_TOKEN_ID 2 199 #define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3 200 #define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4 201 #define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5 202 #define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6 203 204 #define ISYS_CTRL_TOKEN_ID_MSB 3 205 #define ISYS_CTRL_TOKEN_ID_LSB 0 206 #define ISYS_CTRL_PORT_ID_TOKEN_MSB 7 207 #define ISYS_CTRL_PORT_ID_TOKEN_LSB 4 208 #define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31 209 #define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16 210 #define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31 211 #define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8 212 213 #define ISYS_CTRL_TOKEN_ID_IDX 0 214 #define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1) 215 #define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS) 216 #define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1) 217 #define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB 218 #define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1) 219 #define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB 220 #define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1) 221 222 #define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */ 223 #define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */ 224 #define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */ 225 #define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */ 226 #define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */ 227 #define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */ 228 #define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */ 229 #define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */ 230 231 #define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */ 232 #define ISYS_CTRL_NO_DMA_ACK 0 233 #define ISYS_CTRL_NO_CAPT_ACK 16 234 235 #endif /* _input_system_ctrl_defs_h */ 236