1 /*
2  * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
3  * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /* Versal IPI management enums and defines */
9 
10 #ifndef PLAT_IPI_H
11 #define PLAT_IPI_H
12 
13 #include <stdint.h>
14 
15 #include <ipi.h>
16 
17 /*********************************************************************
18  * IPI agent IDs macros
19  ********************************************************************/
20 #define IPI_ID_PMC	1U
21 #define IPI_ID_APU	2U
22 #define IPI_ID_RPU0	3U
23 #define IPI_ID_RPU1	4U
24 #define IPI_ID_3	5U
25 #define IPI_ID_4	6U
26 #define IPI_ID_5	7U
27 #define IPI_ID_PMC_NOBUF	8U
28 #define IPI_ID_6_NOBUF_95	9U
29 #define IPI_ID_1_NOBUF	10U
30 #define IPI_ID_2_NOBUF	11U
31 #define IPI_ID_3_NOBUF	12U
32 #define IPI_ID_4_NOBUF	13U
33 #define IPI_ID_5_NOBUF	14U
34 #define IPI_ID_6_NOBUF_101	15U
35 #define IPI_ID_MAX	16U
36 
37 /*********************************************************************
38  * IPI message buffers
39  ********************************************************************/
40 #define IPI_BUFFER_BASEADDR	(0xEB3F0000U)
41 
42 #define IPI_LOCAL_ID		IPI_ID_APU
43 #define IPI_REMOTE_ID		IPI_ID_PMC
44 
45 #define IPI_BUFFER_LOCAL_BASE	(IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U))
46 #define IPI_BUFFER_REMOTE_BASE	(IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U))
47 
48 #define IPI_BUFFER_TARGET_LOCAL_OFFSET	(IPI_LOCAL_ID * 0x40U)
49 #define IPI_BUFFER_TARGET_REMOTE_OFFSET	(IPI_REMOTE_ID * 0x40U)
50 
51 #define IPI_BUFFER_MAX_WORDS	8
52 
53 #define IPI_BUFFER_REQ_OFFSET	0x0U
54 #define IPI_BUFFER_RESP_OFFSET	0x20U
55 
56 /*********************************************************************
57  * Platform specific IPI API declarations
58  ********************************************************************/
59 
60 /* Configure IPI table for versal_net */
61 void versal_net_ipi_config_table_init(void);
62 
63 /*******************************************************************************
64  * IPI registers and bitfields
65  ******************************************************************************/
66 #define IPI0_REG_BASE		(0xEB330000U)
67 #define IPI0_TRIG_BIT		(1 << 2)
68 #define PMC_IPI_TRIG_BIT	(1 << 1)
69 #define IPI1_REG_BASE		(0xEB340000U)
70 #define IPI1_TRIG_BIT		(1 << 3)
71 #define IPI2_REG_BASE		(0xEB350000U)
72 #define IPI2_TRIG_BIT		(1 << 4)
73 #define IPI3_REG_BASE		(0xEB360000U)
74 #define IPI3_TRIG_BIT		(1 << 5)
75 #define IPI4_REG_BASE		(0xEB370000U)
76 #define IPI4_TRIG_BIT		(1 << 6)
77 #define IPI5_REG_BASE		(0xEB380000U)
78 #define IPI5_TRIG_BIT		(1 << 7)
79 #define PMC_NOBUF_REG_BASE	(0xEB390000U)
80 #define PMC_NOBUF_TRIG_BIT	(1 << 8)
81 #define IPI6_NOBUF_95_REG_BASE	(0xEB3A0000U)
82 #define IPI6_NOBUF_95_TRIG_BIT	(1 << 9)
83 #define IPI1_NOBUF_REG_BASE	(0xEB3B0000U)
84 #define IPI1_NOBUF_TRIG_BIT	(1 << 10)
85 #define IPI2_NOBUF_REG_BASE	(0xEB3B1000U)
86 #define IPI2_NOBUF_TRIG_BIT	(1 << 11)
87 #define IPI3_NOBUF_REG_BASE	(0xEB3B2000U)
88 #define IPI3_NOBUF_TRIG_BIT	(1 << 12)
89 #define IPI4_NOBUF_REG_BASE	(0xEB3B3000U)
90 #define IPI4_NOBUF_TRIG_BIT	(1 << 13)
91 #define IPI5_NOBUF_REG_BASE	(0xEB3B4000U)
92 #define IPI5_NOBUF_TRIG_BIT	(1 << 14)
93 #define IPI6_NOBUF_101_REG_BASE	(0xEB3B5000U)
94 #define IPI6_NOBUF_101_TRIG_BIT	(1 << 15)
95 
96 #endif /* PLAT_IPI_H */
97