1 /***********************************************************************************************************************
2 * Copyright [2015-2017] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
3 *
4 * This file is part of Renesas SynergyTM Software Package (SSP)
5 *
6 * The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
7 * and/or its licensors ("Renesas") and subject to statutory and contractual protections.
8 *
9 * This file is subject to a Renesas SSP license agreement. Unless otherwise agreed in an SSP license agreement with
10 * Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
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12 * MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
13 * "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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17 * included in this file may be subject to different terms.
18 **********************************************************************************************************************/
19 /**********************************************************************************************************************
20 * File Name : hw_sci_common.h
21 * @brief SCI LLD definitions, common portion
22 ***********************************************************************************************************************/
23
24 #ifndef HW_SCI_COMMON_H
25 #define HW_SCI_COMMON_H
26
27 /***********************************************************************************************************************
28 Includes
29 ***********************************************************************************************************************/
30 /* Includes board and MCU related header files. */
31 #include "bsp_api.h"
32
33 /***********************************************************************************************************************
34 Macro definitions
35 ***********************************************************************************************************************/
36 /** SCI SCR register bit masks */
37 #define SCI_SCR_TE_MASK (0x20U) ///< transmitter enable
38 #define SCI_SCR_RE_MASK (0x10U) ///< receiver enable
39 #define SCI_SCR_TE_RE_MASK (0x30U) ///< transmitter & receiver enable
40 #define SCI_SCR_CKE_VALUE_MASK (0x03U) ///< CKE: 2 bits
41
42 /** SCI SEMR register bit masks */
43 #define SCI_SEMR_BGDM_VALUE_MASK (0x01U) ///< BGDM: 1 bit
44 #define SCI_SEMR_ABCS_VALUE_MASK (0x01U) ///< ABCS: 1 bit
45 #define SCI_SEMR_ABCSE_VALUE_MASK (0x01U) ///< ABCSE: 1 bit
46
47 /** SCI SMR register bit masks */
48 #define SCI_SMR_CKS_VALUE_MASK (0x03U) ///< CKS: 2 bits
49
50 /** SCI SSR register receiver error bit masks */
51 #define SCI_SSR_ORER_MASK (0x20U) ///< overflow error
52 #define SCI_SSR_FER_MASK (0x10U) ///< framing error
53 #define SCI_SSR_PER_MASK (0x08U) ///< parity err
54 #define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK)
55
56 /***********************************************************************************************************************
57 Typedef definitions
58 ***********************************************************************************************************************/
59 /** Baud rate divisor information
60 * BRR(N) = (PCLK / (divisor * Baudrate(B))) - 1
61 * when ABCSE=1, divisor = 12*pow(2,2N-1)
62 * when ABCSE=1, BGDM=1&&ABCS=1, divisor = 16*pow(2,2N-1)
63 * when ABCSE=0, one of BGDM or ABCS =1, divisor = 32*pow(2,2N-1)
64 * when ABCSE=0, BGDM=0&&ABCS=0, divisor = 64*pow(2,2N-1)
65 */
66 typedef struct st_baud_setting_t
67 {
68 uint16_t div_coefficient; /**< Divisor coefficient */
69 uint8_t bgdm; /**< BGDM value to get divisor */
70 uint8_t abcs; /**< ABCS value to get divisor */
71 uint8_t abcse; /**< ABCSE value to get divisor */
72 uint8_t cks; /**< CKS value to get divisor (CKS = N) */
73 } baud_setting_t;
74
75 /** Noise filter setting definition */
76 typedef enum e_noise_cancel_lvl
77 {
78 NOISE_CANCEL_LVL1, /**< Noise filter level 1(weak) */
79 NOISE_CANCEL_LVL2, /**< Noise filter level 2 */
80 NOISE_CANCEL_LVL3, /**< Noise filter level 3 */
81 NOISE_CANCEL_LVL4 /**< Noise filter level 4(strong) */
82 } noise_cancel_lvl_t;
83
84 /***********************************************************************************************************************
85 Private function prototypes
86 ***********************************************************************************************************************/
87
88 /***********************************************************************************************************************
89 Private global variables
90 ***********************************************************************************************************************/
91
92 /***********************************************************************************************************************
93 Private Functions
94 ***********************************************************************************************************************/
95
96 /*******************************************************************************************************************//**
97 * Enables reception for the specified SCI channel
98 * @param[in] p_reg Base register for this channel
99 * @retval void
100 * @note Channel number is not checked in this function, caller function must check it.
101 ***********************************************************************************************************************/
HW_SCI_ReceiverEnable(R_SCI0_Type * p_reg)102 __STATIC_INLINE void HW_SCI_ReceiverEnable (R_SCI0_Type * p_reg)
103 {
104 p_reg->SCR |= SCI_SCR_RE_MASK;
105 } /* End of function HW_SCI_ReceiverEnable() */
106
107 /*******************************************************************************************************************//**
108 * Enables transmission for the specified SCI channel
109 * @param[in] p_reg Base register for this channel
110 * @retval void
111 * @note Channel number is not checked in this function, caller function must check it.
112 ***********************************************************************************************************************/
HW_SCI_TransmitterEnable(R_SCI0_Type * p_reg)113 __STATIC_INLINE void HW_SCI_TransmitterEnable (R_SCI0_Type * p_reg)
114 {
115 p_reg->SCR |= SCI_SCR_TE_MASK;
116 } /* End of function HW_SCI_ReceiverEnable() */
117
118 /*******************************************************************************************************************//**
119 * This function writes data to transmit data register.
120 * @param[in] p_reg Base register for this channel
121 * @param[in] data Data to be sent
122 * @retval void
123 * @note All the parameter check must be handled by HLD
124 ***********************************************************************************************************************/
HW_SCI_Write(R_SCI0_Type * p_reg,uint8_t const data)125 __STATIC_INLINE void HW_SCI_Write (R_SCI0_Type * p_reg, uint8_t const data)
126 {
127 while (0U == p_reg->SSR_b.TDRE)
128 {
129 /* Wait until TDRE is cleared */
130 }
131
132 /* Write 1byte data to data register */
133 p_reg->TDR = data;
134 } /* End of function HW_SCI_Write() */
135
136 /*******************************************************************************************************************//**
137 * This function reads data from receive data register
138 * @param[in] p_reg Base register for this channel
139 * @retval Received data
140 * @note Channel number is not checked in this function, caller function must check it.
141 ***********************************************************************************************************************/
HW_SCI_Read(R_SCI0_Type * p_reg)142 __STATIC_INLINE uint8_t HW_SCI_Read (R_SCI0_Type * p_reg)
143 {
144 return p_reg->RDR;
145 } /* End of function HW_SCI_Read() */
146
147 /*******************************************************************************************************************//**
148 * This function initializes all SCI registers.
149 * @param[in] p_reg Base register for this channel
150 * @retval void
151 * @note All the parameter check must be handled by HLD
152 ***********************************************************************************************************************/
HW_SCI_RegisterReset(R_SCI0_Type * p_reg)153 __STATIC_INLINE void HW_SCI_RegisterReset (R_SCI0_Type * p_reg)
154 {
155 p_reg->SMR = 0U;
156 p_reg->SCR = 0U;
157 if (p_reg->SSR > 0U)
158 {
159 p_reg->SSR = 0U;
160 }
161 p_reg->SCMR = 0xF2U;
162 p_reg->BRR = 0xFFU;
163 p_reg->MDDR = 0xFFU;
164 p_reg->SEMR = 0U;
165 p_reg->SNFR = 0U;
166 p_reg->SIMR1 = 0U;
167 p_reg->SIMR2 = 0U;
168 p_reg->SIMR3 = 0U;
169 p_reg->SISR = 0U;
170 p_reg->SPMR = 0U;
171 p_reg->SISR = 0U;
172 p_reg->FCR = 0xF800U;
173 p_reg->CDR = 0U;
174 p_reg->DCCR = 0x40U;
175 p_reg->SPTR = 0x03U;
176 } /* End of function HW_SCI_RegisterReset() */
177
178 /*******************************************************************************************************************//**
179 * Selects internal clock for baud rate generator
180 * @param[in] p_reg Base register for this channel
181 * @retval void
182 * @note All the parameter check must be handled by HLD
183 ***********************************************************************************************************************/
HW_SCI_BaudRateGenInternalClkSelect(R_SCI0_Type * p_reg)184 __STATIC_INLINE void HW_SCI_BaudRateGenInternalClkSelect (R_SCI0_Type * p_reg)
185 {
186 p_reg->SCR_b.CKE = 0U; /* Internal clock */
187 } /* End of function HW_SCI_BaudRateGenInternalClkSelect() */
188
189 /*******************************************************************************************************************//**
190 * Selects external clock for baud rate generator
191 * @param[in] p_reg Base register for this channel
192 * @retval void
193 * @note All the parameter check must be handled by HLD
194 ***********************************************************************************************************************/
HW_SCI_BaudRateGenExternalClkSelect(R_SCI0_Type * p_reg)195 __STATIC_INLINE void HW_SCI_BaudRateGenExternalClkSelect (R_SCI0_Type * p_reg)
196 {
197 /* Use external clock for baud rate */
198 p_reg->SCR_b.CKE = 0x2U; /* External clock */
199 } /* End of function HW_SCI_BaudRateGenExternalClkSelect() */
200
201 /*******************************************************************************************************************//**
202 * Checks if Internal clock is selected or not
203 * @param[in] p_reg Base register for this channel
204 * @retval true Internal clock is selected
205 * @retval false External clock is selected
206 * @note All the parameter check must be handled by HLD
207 ***********************************************************************************************************************/
HW_SCI_IsBaudRateInternalClkSelected(R_SCI0_Type * p_reg)208 __STATIC_INLINE bool HW_SCI_IsBaudRateInternalClkSelected (R_SCI0_Type * p_reg)
209 {
210 return (p_reg->SCR_b.CKE == 0U);
211 } /* End of function HW_SCI_IsBaudRateInternalClkSelected() */
212
213 /*******************************************************************************************************************//**
214 * Selects 8 base clock cycles for 1-bit period
215 * @param[in] p_reg Base register for this channel
216 * @retval void
217 * @note All the parameter check must be handled by HLD
218 ***********************************************************************************************************************/
HW_SCI_BaudRateGenExternalClkDivideBy8(R_SCI0_Type * p_reg)219 __STATIC_INLINE void HW_SCI_BaudRateGenExternalClkDivideBy8 (R_SCI0_Type * p_reg)
220 {
221 p_reg->SEMR_b.ABCS = 1U; /* set baud rate as (external clock / 8) */
222 } /* End of function HW_SCI_BaudRateGenExternalClkDivideBy8() */
223
224 /*******************************************************************************************************************//**
225 * Sets baud rate generator related registers as configured
226 * @param[in] p_reg Base register for this channel
227 * @param[in] brr BRR register setting value
228 * @param[in] pbaudinfo Baud rate information to be configured
229 * @retval void
230 * @note All the parameter check must be handled by HLD
231 ***********************************************************************************************************************/
HW_SCI_UartBitRateSet(R_SCI0_Type * p_reg,const uint8_t brr,baud_setting_t const * const pbaudinfo)232 __STATIC_INLINE void HW_SCI_UartBitRateSet (R_SCI0_Type * p_reg, const uint8_t brr, baud_setting_t const * const pbaudinfo)
233 {
234 p_reg->BRR = brr;
235 p_reg->SEMR_b.BGDM = (uint8_t)(SCI_SEMR_BGDM_VALUE_MASK & pbaudinfo->bgdm);
236 p_reg->SEMR_b.ABCS = (uint8_t)(SCI_SEMR_ABCS_VALUE_MASK & pbaudinfo->abcs);
237 p_reg->SEMR_b.ABCSE = (uint8_t)(SCI_SEMR_ABCSE_VALUE_MASK & pbaudinfo->abcse);
238 p_reg->SMR_b.CKS = (uint8_t)(SCI_SMR_CKS_VALUE_MASK & pbaudinfo->cks);
239 } /* End of function HW_SCI_UartBitRateSet() */
240
241 /*******************************************************************************************************************//**
242 * Sets baud rate generator related registers as default
243 * @param[in] p_reg Base register for this channel
244 * @retval void
245 * @note All the parameter check must be handled by HLD
246 ***********************************************************************************************************************/
HW_SCI_BitRateDefaultSet(R_SCI0_Type * p_reg)247 __STATIC_INLINE void HW_SCI_BitRateDefaultSet (R_SCI0_Type * p_reg)
248 {
249 /* Use external clock for baud rate */
250 p_reg->BRR = 0xFFU;
251 p_reg->SEMR_b.BGDM = 0U;
252 p_reg->SEMR_b.ABCSE = 0U;
253 p_reg->SMR_b.CKS = 0U;
254 } /* End of function HW_SCI_BitRateDefaultSet() */
255
256 /*******************************************************************************************************************//**
257 * Enables to output baud rate clock
258 * @param[in] p_reg Base register for this channel
259 * @param[in] enable Baud rate clock output enable
260 * @retval void
261 * @note Channel number is not checked in this function, caller function must check it.
262 ***********************************************************************************************************************/
HW_SCI_BaudClkOutputEnable(R_SCI0_Type * p_reg,bool enable)263 __STATIC_INLINE void HW_SCI_BaudClkOutputEnable (R_SCI0_Type * p_reg, bool enable)
264 {
265 uint8_t temp_cke = p_reg->SCR_b.CKE;
266 uint8_t temp_enable = enable ? 1U : 0U;
267 temp_cke |= temp_enable;
268 p_reg->SCR_b.CKE = (temp_cke & 3U); /* enable to output baud clock on SCK pin */
269 } /* End of function HW_SCI_BaudClkOutputEnable() */
270
271 /*******************************************************************************************************************//**
272 * Disables to output baud rate clock
273 * @param[in] p_reg Base register for this channel
274 * @retval void
275 * @note Channel number is not checked in this function, caller function must check it.
276 ***********************************************************************************************************************/
HW_SCI_BaudClkOutputDisable(R_SCI0_Type * p_reg)277 __STATIC_INLINE void HW_SCI_BaudClkOutputDisable (R_SCI0_Type * p_reg)
278 {
279 p_reg->SCR_b.CKE &= (SCI_SCR_CKE_VALUE_MASK & (uint8_t) ~0x01U); /* disable to output baud clock on SCK pin */
280 } /* End of function HW_SCI_BaudClkOutputDisable() */
281
282 /*******************************************************************************************************************//**
283 * Sets Noise cancel filter
284 * @param[in] p_reg Base register for this channel
285 * @param[in] enabled Noise cancel enable
286 * @retval void
287 * @note Channel number and argument check is omitted, must be checked by SCI HLD
288 ***********************************************************************************************************************/
HW_SCI_NoiseFilterSet(R_SCI0_Type * p_reg,bool enabled)289 __STATIC_INLINE void HW_SCI_NoiseFilterSet (R_SCI0_Type * p_reg, bool enabled)
290 {
291 p_reg->SEMR_b.NFEN = enabled ? 1U : 0U; /* enable noise filter */
292 p_reg->SNFR = NOISE_CANCEL_LVL1;
293 } /* End of function HW_SCI_NoiseFilterSet() */
294
295 /*******************************************************************************************************************//**
296 * Checks if overrun error happen or not
297 * @param[in] p_reg Base register for this channel
298 * @retval true : Overrun error happens
299 * @retval false : Overrun error does not happen
300 * @note Channel number is not checked in this function, caller function must check it.
301 ***********************************************************************************************************************/
HW_SCI_OverRunErrorCheck(R_SCI0_Type * p_reg)302 __STATIC_INLINE bool HW_SCI_OverRunErrorCheck (R_SCI0_Type * p_reg)
303 {
304 return (1U == p_reg->SSR_b.ORER);
305 } /* End of function HW_SCI_OverRunErrorCheck() */
306
307 /*******************************************************************************************************************//**
308 * Checks if framing error happen or not
309 * @param[in] p_reg Base register for this channel
310 * @retval true : Framing error happens
311 * @retval false : Framing error does not happen
312 * @note Channel number is not checked in this function, caller function must check it.
313 ***********************************************************************************************************************/
HW_SCI_FramingErrorCheck(R_SCI0_Type * p_reg)314 __STATIC_INLINE bool HW_SCI_FramingErrorCheck (R_SCI0_Type * p_reg)
315 {
316 return (1U == p_reg->SSR_b.FER);
317 } /* End of function HW_SCI_FramingErrorCheck() */
318
319 /*******************************************************************************************************************//**
320 * Checks if Break signal is found or not
321 * @param[in] p_reg Base register for this channel
322 * @retval true : Break signal is found
323 * @retval false : Break signal is not found
324 * @note Channel number is not checked in this function, caller function must check it. This function is only valid
325 * when called in case of HW_SCI_FramingErrorCheck() returns true just before calling this function. If level
326 * of RxD pin is low when framing error happens, that means receiving break signal.
327 ***********************************************************************************************************************/
HW_SCI_BreakDetectionCheck(R_SCI0_Type * p_reg)328 __STATIC_INLINE bool HW_SCI_BreakDetectionCheck (R_SCI0_Type * p_reg)
329 {
330 return (0U == p_reg->SPTR_b.RXDMON);
331 } /* End of function HW_SCI_BreakDetectionCheck() */
332
333 /*******************************************************************************************************************//**
334 * Checks if parity error happen or not
335 * @param[in] p_reg Base register for this channel
336 * @retval true : Parity Error happens
337 * @retval false : Parity Error does not happen
338 * @note Channel number is not checked in this function, caller function must check it.
339 ***********************************************************************************************************************/
HW_SCI_ParityErrorCheck(R_SCI0_Type * p_reg)340 __STATIC_INLINE bool HW_SCI_ParityErrorCheck (R_SCI0_Type * p_reg)
341 {
342 return (1U == p_reg->SSR_b.PER);
343 } /* End of function HW_SCI_ParityErrorCheck() */
344
345 /*******************************************************************************************************************//**
346 * Clears error status
347 * @param[in] p_reg Base register for this channel
348 * @retval void
349 * @note Channel number is not checked in this function, caller function must check it.
350 ***********************************************************************************************************************/
HW_SCI_ErrorConditionClear(R_SCI0_Type * p_reg)351 __STATIC_INLINE void HW_SCI_ErrorConditionClear (R_SCI0_Type * p_reg)
352 {
353 p_reg->SSR &= (uint8_t)(~SCI_RCVR_ERR_MASK);
354 } /* End of function HW_SCI_ErrorConditionClear() */
355
356 /*******************************************************************************************************************//**
357 * Function for enabling/disabling bit rate modulation function in serial extended mode register (SEMR).
358 * @param[in] p_reg Base register for this channel
359 * @param[in] enable Enables or disables the bitrate modulation function
360 * @retval void
361 * @note Channel number is not checked in this function, caller function must check it.
362 **********************************************************************************************************************/
HW_SCI_BitRateModulationEnable(R_SCI0_Type * p_reg,bool const enable)363 __STATIC_INLINE void HW_SCI_BitRateModulationEnable(R_SCI0_Type * p_reg, bool const enable)
364 {
365 /* enable/disable bit */
366 p_reg->SEMR_b.BRME = (uint8_t) (enable & 1U);
367 } /* End of function HW_SCI_BitRateModulationEnable() */
368
369 /*******************************************************************************************************************//**
370 * Sets MDDR register as calculated
371 * @param[in] p_reg Base register for this channel
372 * @param[in] mddr BRR register setting value
373 * @retval void
374 * @note All the parameter check must be handled by HLD
375 ***********************************************************************************************************************/
HW_SCI_UartBitRateModulationSet(R_SCI0_Type * p_reg,const uint8_t mddr)376 __STATIC_INLINE void HW_SCI_UartBitRateModulationSet (R_SCI0_Type * p_reg, const uint8_t mddr)
377 {
378 /* Set MBBR register value*/
379 p_reg->MDDR = mddr;
380
381 } /* End of function HW_SCI_UartBitRateModulationSet() */
382
383 #endif // HW_SCI_COMMON_H
384
385 /* End of file */
386