1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ 4 #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ 5 6 #include <stddef.h> 7 #include <stdint.h> 8 9 enum { 10 TEGRA_SRAM_BASE = 0x40000000, 11 TEGRA_SRAM_SIZE = 0x40000 12 }; 13 14 enum { 15 TEGRA_ARM_PCIE_A1_BASE = 0x01000000, 16 TEGRA_ARM_LOWEST_PERIPH = TEGRA_ARM_PCIE_A1_BASE, 17 TEGRA_ARM_PERIPHBASE = 0x50040000, 18 TEGRA_GICD_BASE = 0x50041000, 19 TEGRA_GICC_BASE = 0x50042000, 20 TEGRA_MSELECT_CONFIG = 0x50060000, 21 TEGRA_ARM_DISPLAYA = 0x54200000, 22 TEGRA_ARM_DISPLAYB = 0x54240000, 23 TEGRA_DSIA_BASE = 0x54300000, 24 TEGRA_DSIB_BASE = 0x54400000, 25 TEGRA_ARM_SOR = 0x54540000, 26 TEGRA_ARM_DPAUX = 0x545c0000, 27 TEGRA_PG_UP_BASE = 0x60000000, 28 TEGRA_TMRUS_BASE = 0x60005010, 29 TEGRA_CLK_RST_BASE = 0x60006000, 30 TEGRA_FLOW_BASE = 0x60007000, 31 TEGRA_SB_BASE = 0x6000C200, 32 TEGRA_GPIO_BASE = 0x6000D000, 33 TEGRA_EVP_BASE = 0x6000F000, 34 TEGRA_APB_DMA_BASE = 0x60020000, 35 TEGRA_APB_MISC_BASE = 0x70000000, 36 TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, 37 TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, 38 TEGRA_APB_PINMUX_BASE = TEGRA_APB_MISC_BASE + 0x3000, 39 TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000, 40 TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040, 41 TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200, 42 TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300, 43 TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400, 44 TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000, 45 TEGRA_PWM_BASE = TEGRA_APB_MISC_BASE + 0xA000, 46 TEGRA_I2C1_BASE = TEGRA_APB_MISC_BASE + 0xC000, 47 TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380, 48 TEGRA_I2C2_BASE = TEGRA_APB_MISC_BASE + 0xC400, 49 TEGRA_I2C3_BASE = TEGRA_APB_MISC_BASE + 0xC500, 50 TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700, 51 TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000, 52 TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100, 53 TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400, 54 TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600, 55 TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800, 56 TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, 57 TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, 58 TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, 59 TEGRA_SBC1_BASE = TEGRA_SPI1_BASE, 60 TEGRA_SBC2_BASE = TEGRA_SPI2_BASE, 61 TEGRA_SBC3_BASE = TEGRA_SPI3_BASE, 62 TEGRA_SBC4_BASE = TEGRA_SPI4_BASE, 63 TEGRA_SBC5_BASE = TEGRA_SPI5_BASE, 64 TEGRA_SBC6_BASE = TEGRA_SPI6_BASE, 65 TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, 66 TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, 67 TEGRA_MC_BASE = 0x70019000, 68 TEGRA_EMC_BASE = 0x7001B000, 69 TEGRA_CLUSTER_CLOCK_BASE = 0x70040000, 70 TEGRA_QSPI_BASE = 0x70410000, 71 TEGRA_CSITE_BASE = 0x70800000, 72 TEGRA_SDMMC_BASE = 0x700b0000, 73 TEGRA_SDMMC1_BASE = TEGRA_SDMMC_BASE + 0x0000, 74 TEGRA_SDMMC2_BASE = TEGRA_SDMMC_BASE + 0x0200, 75 TEGRA_SDMMC3_BASE = TEGRA_SDMMC_BASE + 0x0400, 76 TEGRA_SDMMC4_BASE = TEGRA_SDMMC_BASE + 0x0600, 77 TEGRA_MIPI_CAL_BASE = 0x700E3000, 78 TEGRA_SYSCTR0_BASE = 0x700F0000, 79 TEGRA_I2S1_BASE = 0x70301100, 80 TEGRA_USBD_BASE = 0x7D000000, 81 TEGRA_USB2_BASE = 0x7D004000, 82 TEGRA_USB3_BASE = 0x7D008000, 83 }; 84 85 enum { 86 TEGRA_I2C_BASE_COUNT = 6, 87 }; 88 89 #define GPU_CARVEOUT_SIZE_MB 1 90 #define NVDEC_CARVEOUT_SIZE_MB 1 91 #define TSEC_CARVEOUT_SIZE_MB 2 92 #define VPR_CARVEOUT_SIZE_MB 128 93 94 /* Return total size of DRAM memory configured on the platform. */ 95 int sdram_size_mb(void); 96 97 /* Find memory below and above 4GiB boundary respectively. All units 1MiB. */ 98 void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib); 99 void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib); 100 101 enum { 102 CARVEOUT_TZ, 103 CARVEOUT_SEC, 104 CARVEOUT_MTS, 105 CARVEOUT_VPR, 106 CARVEOUT_GPU, 107 CARVEOUT_NVDEC, 108 CARVEOUT_TSEC, 109 CARVEOUT_NUM, 110 }; 111 112 /* Provided the careout id, obtain the base and size in 1MiB units. */ 113 void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib); 114 void print_carveouts(void); 115 116 /* 117 * There are complications accessing the Trust Zone carveout region. The 118 * AVP cannot access these registers and the CPU can't access this register 119 * as a non-secure access. When the page tables live in non-secure memory 120 * these registers cannot be accessed either. Thus, this function handles 121 * both the AVP case and non-secured access case by keeping global state. 122 */ 123 void trustzone_region_init(void); 124 void gpu_region_init(void); 125 void nvdec_region_init(void); 126 void tsec_region_init(void); 127 void vpr_region_init(void); 128 129 #endif /* __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ */ 130