1 /***********************************************************************************************************************
2  * Copyright [2015-2017] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
3  *
4  * This file is part of Renesas SynergyTM Software Package (SSP)
5  *
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17  * included in this file may be subject to different terms.
18  **********************************************************************************************************************/
19 
20 /**********************************************************************************************************************
21  * File Name    : hw_gpt_common.h
22  * Description  : Lower level driver (register access) functions for GPT.
23  **********************************************************************************************************************/
24 
25 #ifndef HW_GPT_COMMON_H
26 #define HW_GPT_COMMON_H
27 
28 /**********************************************************************************************************************
29  * Includes
30  **********************************************************************************************************************/
31 #include "bsp_api.h"
32 
33 /**********************************************************************************************************************
34  * Macro Definitions
35  **********************************************************************************************************************/
36 
37 /* Common macro for SSP header files. There is also a corresponding SSP_FOOTER macro at the end of this file. */
38 SSP_HEADER
39 
40 /***********************************************************************************************************************
41  * Private global variables
42  **********************************************************************************************************************/
43 /** Pointer to GPT channels */
44 #ifdef R_GPTA0_BASE
45 /*LDRA_INSPECTED 77 S Adding parentheses to this macro changes the meaning. */
46 #define GPT_BASE_PTR  R_GPTA0_Type *
47 #elif defined(R_GPTB0_BASE)
48 /*LDRA_INSPECTED 77 S Adding parentheses to this macro changes the meaning. */
49 #define GPT_BASE_PTR  R_GPTB0_Type *
50 #endif
51 
52 /***********************************************************************************************************************
53  * Private Functions
54  **********************************************************************************************************************/
55 /*******************************************************************************************************************//**
56  * Sets the timer operational mode.
57  * @param  p_gpt_base  Pointer to base register of GPT channel.
58  * @param  mode        Select mode to set.  See ::gpt_mode_t.
59  **********************************************************************************************************************/
HW_GPT_ModeSet(GPT_BASE_PTR p_gpt_base,gpt_mode_t mode)60 __STATIC_INLINE void HW_GPT_ModeSet (GPT_BASE_PTR p_gpt_base, gpt_mode_t mode)
61 {
62     /* Set mode */
63     p_gpt_base->GTCR_b.MD = mode;
64 }
65 
66 /*******************************************************************************************************************//**
67  * Sets the timer cycle (compare match value).  The timer cycle, along with the PCLK frequency and the GPT PCLK divisor
68  * control the timer period.
69  * @param  p_gpt_base   Pointer to base register of GPT channel.
70  * @param  timer_cycle  Any number from 0 to 0xFFFFFFFF.  The resulting delay period can be calculated according to:
71  *                           \f$period=\frac{(timer_cycle+1) \times GPTPCLKDivisor}{PCLKFrequencyHz}\f$
72  *                           where GPTPCLKDivisor is any of the following: 1, 4, 16, 64, 256, or 1024
73  *                           (see ::HW_GPT_DivisorSet)
74  **********************************************************************************************************************/
HW_GPT_TimerCycleSet(GPT_BASE_PTR p_gpt_base,uint32_t timer_cycle)75 __STATIC_INLINE void HW_GPT_TimerCycleSet (GPT_BASE_PTR p_gpt_base, uint32_t timer_cycle)
76 {
77     /* Set delay */
78     p_gpt_base->GTPR = timer_cycle;
79 }
80 
81 /*******************************************************************************************************************//**
82  * Returns the timer cycle (compare match value).  The timer cycle, along with the PCLK frequency and the GPT PCLK
83  * divisor control the timer period.
84  * @param   p_gpt_base  Pointer to base register of GPT channel.
85  * @return  The timer cycle value.  See ::HW_GPT_TimerCycleSet for relationship to timer period.
86  **********************************************************************************************************************/
HW_GPT_TimerCycleGet(GPT_BASE_PTR p_gpt_base)87 __STATIC_INLINE uint32_t HW_GPT_TimerCycleGet (GPT_BASE_PTR p_gpt_base)
88 {
89     return p_gpt_base->GTPR;
90 }
91 
92 /*******************************************************************************************************************//**
93  * Sets the GPT PCLK divisor.  The GPT PCLK divisor, along with the PCLK frequency and the timer cycle control the
94  * timer period.
95  * @param   p_gpt_base    Pointer to base register of GPT channel.
96  * @param   pclk_divisor  See ::gpt_pclk_div_t for available divisors.
97  **********************************************************************************************************************/
HW_GPT_DivisorSet(GPT_BASE_PTR p_gpt_base,gpt_pclk_div_t pclk_divisor)98 __STATIC_INLINE void HW_GPT_DivisorSet (GPT_BASE_PTR p_gpt_base, gpt_pclk_div_t pclk_divisor)
99 {
100     p_gpt_base->GTCR_b.TPCS = pclk_divisor;
101 }
102 
103 /*******************************************************************************************************************//**
104  * Gets the GPT PCLK divisor.  The GPT PCLK divisor, along with the PCLK frequency and the timer cycle control the
105  * timer period.
106  * @param   p_gpt_base  Pointer to base register of GPT channel.
107  * @retval  PCLK divisor value. See ::gpt_pclk_div_t for the detail.
108  **********************************************************************************************************************/
HW_GPT_DivisorGet(GPT_BASE_PTR p_gpt_base)109 __STATIC_INLINE gpt_pclk_div_t HW_GPT_DivisorGet (GPT_BASE_PTR p_gpt_base)
110 {
111     return (gpt_pclk_div_t) p_gpt_base->GTCR_b.TPCS;
112 }
113 
114 /*******************************************************************************************************************//**
115  * Starts the counter.
116  * @param  p_gpt_base  Pointer to base register of GPT channel.
117  **********************************************************************************************************************/
HW_GPT_CounterStartStop(GPT_BASE_PTR p_gpt_base,gpt_start_status_t start_stop)118 __STATIC_INLINE void HW_GPT_CounterStartStop (GPT_BASE_PTR p_gpt_base, gpt_start_status_t start_stop)
119 {
120     p_gpt_base->GTCR_b.CST = start_stop;
121 }
122 
123 /*******************************************************************************************************************//**
124  * Sets the counter value.
125  * @param  p_gpt_base   Pointer to base register of GPT channel.
126  * @param  value        Any number from 0 to 0xFFFFFFFF.
127  **********************************************************************************************************************/
HW_GPT_CounterSet(GPT_BASE_PTR p_gpt_base,uint32_t value)128 __STATIC_INLINE void HW_GPT_CounterSet (GPT_BASE_PTR p_gpt_base, uint32_t value)
129 {
130     /* Set counter value */
131     p_gpt_base->GTCNT = value;
132 }
133 
134 
135 /*******************************************************************************************************************//**
136  * Returns the current counter value.
137  * @param   p_gpt_base  Pointer to base register of GPT channel.
138  * @return  Current counter value in the range 0 to 0xFFFFFFFF.
139  **********************************************************************************************************************/
HW_GPT_CounterGet(GPT_BASE_PTR p_gpt_base)140 __STATIC_INLINE uint32_t HW_GPT_CounterGet (GPT_BASE_PTR p_gpt_base)
141 {
142     /* Get counter value */
143     return p_gpt_base->GTCNT;
144 }
145 
146 /*******************************************************************************************************************//**
147  * Sets the direction the counter counts.
148  * @param  p_gpt_base   Pointer to base register of GPT channel.
149  * @param  dir          See ::gpt_dir_t for available values.
150  **********************************************************************************************************************/
HW_GPT_DirectionSet(GPT_BASE_PTR p_gpt_base,gpt_dir_t dir)151 __STATIC_INLINE void HW_GPT_DirectionSet (GPT_BASE_PTR p_gpt_base, gpt_dir_t dir)
152 {
153     /* Force setting */
154     p_gpt_base->GTUDDTYC_b.UDF = 1U;
155 
156     /* Start timer */
157     p_gpt_base->GTUDDTYC_b.UD = dir;
158 
159     /* Clear forcing */
160     p_gpt_base->GTUDDTYC_b.UDF = 0U;
161 }
162 
163 /*******************************************************************************************************************//**
164  * Sets the direction the counter counts.
165  * @param  p_gpt_base  Pointer to base register of GPT channel.
166  * @retval Count Direction Setting(GPT_DIR_COUNT_DOWN or GPT_DIR_COUNT_UP)
167  **********************************************************************************************************************/
HW_GPT_DirectionGet(GPT_BASE_PTR p_gpt_base)168 __STATIC_INLINE timer_direction_t HW_GPT_DirectionGet (GPT_BASE_PTR p_gpt_base)
169 {
170     /* Read cound direction setting */
171     return (timer_direction_t) p_gpt_base->GTUDDTYC_b.UD;
172 }
173 
174 /*******************************************************************************************************************//**
175  * Clears interrupts for specified channel.
176  * @param  p_gpt_base  Pointer to base register of GPT channel.
177  **********************************************************************************************************************/
HW_GPT_InterruptClear(GPT_BASE_PTR p_gpt_base)178 __STATIC_INLINE void HW_GPT_InterruptClear (GPT_BASE_PTR p_gpt_base)
179 {
180     p_gpt_base->GTST_b.TCPFO = 0U;
181 }
182 
183 /*******************************************************************************************************************//**
184  * Returns the value of the start bit, indicating if the counter is counting or not.
185  * @param   p_gpt_base  Pointer to base register of GPT channel.
186  * @return  Start bit value
187  **********************************************************************************************************************/
HW_GPT_CounterStartBitGet(GPT_BASE_PTR p_gpt_base)188 __STATIC_INLINE gpt_start_status_t HW_GPT_CounterStartBitGet (GPT_BASE_PTR p_gpt_base)
189 {
190     return (gpt_start_status_t) p_gpt_base->GTCR_b.CST;
191 }
192 
193 /*******************************************************************************************************************//**
194  * Lookup base address of input/output control register for specified channel and pin.
195  * @param   p_gpt_base   Pointer to base register of GPT channel.
196  * @param   gtioc        Specify which output pin to use.
197  * @param[out] pp_reg    Pointer to pointer to GTIORH or GTIORL.
198  **********************************************************************************************************************/
HW_GPT_GTIOCRegLookup(GPT_BASE_PTR p_gpt_base,gpt_gtioc_t gtioc)199 __STATIC_INLINE gtior_t * HW_GPT_GTIOCRegLookup (GPT_BASE_PTR p_gpt_base, gpt_gtioc_t gtioc)
200 {
201     if (GPT_GTIOCA == gtioc)
202     {
203         return ((gtior_t *) &p_gpt_base->GTIOR) + 1;
204     }
205     else
206     {
207         return ((gtior_t *) &p_gpt_base->GTIOR);
208     }
209 }
210 
211 /*******************************************************************************************************************//**
212  * Set level to output when counter is stopped.
213  * @param   p_reg        Pointer to input/output control register
214  * @param   level        Level to output when counter is stopped.
215  **********************************************************************************************************************/
HW_GPT_GTIOCPinLevelStoppedSet(gtior_t * const p_reg,gpt_pin_level_t const level)216 __STATIC_INLINE void HW_GPT_GTIOCPinLevelStoppedSet (gtior_t * const p_reg, gpt_pin_level_t const level)
217 {
218     p_reg->GTIOR_b.OADFLT = level;
219 }
220 
221 /*******************************************************************************************************************//**
222  * Enable output to pin.
223  * @param   p_reg        Pointer to input/output control register
224  **********************************************************************************************************************/
HW_GPT_GTIOCPinOutputEnable(gtior_t * const p_reg,bool enable)225 __STATIC_INLINE void HW_GPT_GTIOCPinOutputEnable (gtior_t * const p_reg, bool enable)
226 {
227     p_reg->GTIOR_b.OAE = (uint16_t) (enable & 1U);
228 }
229 
230 /*******************************************************************************************************************//**
231  * Disable output to pin.
232  * @param   p_reg        Pointer to input/output control register
233  **********************************************************************************************************************/
HW_GPT_GTIOCPinOutputDisable(gtior_t * const p_reg)234 __STATIC_INLINE void HW_GPT_GTIOCPinOutputDisable (gtior_t * const p_reg)
235 {
236     p_reg->GTIOR_b.OAE = 0U;
237 }
238 
239 /*******************************************************************************************************************//**
240  * Set how to change output at cycle end.
241  * @param   p_reg        Pointer to input/output control register
242  * @param   mode         Level to output at cycle end
243  **********************************************************************************************************************/
HW_GPT_GTIOCCycleEndOutputSet(gtior_t * const p_reg,gpt_output_t const output)244 __STATIC_INLINE void HW_GPT_GTIOCCycleEndOutputSet (gtior_t * const p_reg, gpt_output_t const output)
245 {
246     p_reg->GTIOR_b.GTIOCE = output;
247 }
248 
249 /*******************************************************************************************************************//**
250  * Set compare match mode
251  * @param   p_reg        Pointer to input/output control register
252  * @param   value        Compare match value to set
253  **********************************************************************************************************************/
HW_GPT_DutyCycleModeSet(GPT_BASE_PTR p_gpt_base,gpt_gtioc_t gtio,gpt_duty_cycle_mode_t mode)254 __STATIC_INLINE void HW_GPT_DutyCycleModeSet (GPT_BASE_PTR p_gpt_base, gpt_gtioc_t gtio, gpt_duty_cycle_mode_t mode)
255 {
256     if (GPT_GTIOCA == gtio)
257     {
258         p_gpt_base->GTUDDTYC_b.OADTY = mode;
259     }
260     else if (GPT_GTIOCB == gtio)
261     {
262         p_gpt_base->GTUDDTYC_b.OBDTY = mode;
263     }
264 }
265 
266 /*******************************************************************************************************************//**
267  * Set compare match value
268  * @param   p_gpt_base   Pointer to base register of GPT channel.
269  * @param   value        Compare match value to set
270  **********************************************************************************************************************/
HW_GPT_InitialCompareMatchSet(GPT_BASE_PTR p_gpt_base,gpt_gtioc_t gtio,uint32_t const value)271 __STATIC_INLINE void HW_GPT_InitialCompareMatchSet (GPT_BASE_PTR p_gpt_base, gpt_gtioc_t gtio, uint32_t const value)
272 {
273     if (GPT_GTIOCA == gtio)
274     {
275         /* GTCCRA buffer register. */
276         p_gpt_base->GTCCRA = value;
277     }
278     else
279     {
280         /* GTCCRB buffer register. */
281         p_gpt_base->GTCCRB = value;
282     }
283 }
284 
285 /*******************************************************************************************************************//**
286  * Enable buffer.
287  * @param   p_reg        Pointer to input/output control register
288  * @param   value        Compare match value to set
289  **********************************************************************************************************************/
HW_GPT_SingleBufferEnable(GPT_BASE_PTR p_gpt_base,gpt_gtioc_t gtio)290 __STATIC_INLINE void HW_GPT_SingleBufferEnable (GPT_BASE_PTR p_gpt_base, gpt_gtioc_t gtio)
291 {
292     if (GPT_GTIOCA == gtio)
293     {
294         /* GTCCRA buffer enable. */
295         p_gpt_base->GTBER_b.CCRA = 1U;
296     }
297     else
298     {
299         /* GTCCRB buffer enable. */
300         p_gpt_base->GTBER_b.CCRB = 1U;
301     }
302 }
303 
304 /*******************************************************************************************************************//**
305  * Set compare match value
306  * @param   p_gpt_base   Pointer to base register of GPT channel.
307  * @param   value        Compare match value to set
308  **********************************************************************************************************************/
HW_GPT_CompareMatchSet(GPT_BASE_PTR p_gpt_base,gpt_gtioc_t gtio,uint32_t const value)309 __STATIC_INLINE void HW_GPT_CompareMatchSet (GPT_BASE_PTR p_gpt_base, gpt_gtioc_t gtio, uint32_t const value)
310 {
311     if (GPT_GTIOCA == gtio)
312     {
313         /* GTCCRA buffer register. */
314         p_gpt_base->GTCCRC = value;
315     }
316     else
317     {
318         /* GTCCRB buffer register. */
319         p_gpt_base->GTCCRE = value;
320     }
321 }
322 
323 /*******************************************************************************************************************//**
324  * Set compare match value
325  * @param   p_gpt_base   Pointer to base register of GPT channel.
326  * @param   gtio         GPT output pin used.
327  * @return  Pointer to duty cycle register.
328  **********************************************************************************************************************/
HW_GPT_DutyCycleAddrGet(GPT_BASE_PTR p_gpt_base,gpt_gtioc_t gtio)329 __STATIC_INLINE volatile void * HW_GPT_DutyCycleAddrGet(GPT_BASE_PTR p_gpt_base, gpt_gtioc_t gtio)
330 {
331     volatile uint32_t * p_reg;
332     if (GPT_GTIOCA == gtio)
333     {
334         /* GTCCRA buffer register. */
335         p_reg = &p_gpt_base->GTCCRC;
336     }
337     else
338     {
339         /* GTCCRB buffer register. */
340         p_reg = &p_gpt_base->GTCCRE;
341     }
342     return p_reg;
343 }
344 
345 /*******************************************************************************************************************//**
346  * Set how to change output at compare match.
347  * @param   p_reg        Pointer to input/output control register
348  * @param   output       Level to output at compare match
349  **********************************************************************************************************************/
HW_GPT_GTIOCCompareMatchOutputSet(gtior_t * const p_reg,gpt_output_t const output)350 __STATIC_INLINE void HW_GPT_GTIOCCompareMatchOutputSet (gtior_t * const p_reg, gpt_output_t const output)
351 {
352     p_reg->GTIOR_b.GTIOCM = output;
353 }
354 
355 /*******************************************************************************************************************//**
356  * Set initial output value
357  * @param   p_reg        Pointer to input/output control register
358  * @param   output       Level to output at compare match
359  **********************************************************************************************************************/
HW_GPT_GTIOCInitialOutputSet(gtior_t * const p_reg,gpt_pin_level_t const output)360 __STATIC_INLINE void HW_GPT_GTIOCInitialOutputSet (gtior_t * const p_reg, gpt_pin_level_t const output)
361 {
362     p_reg->GTIOR_b.GTIOCI = output;
363 }
364 
365 /*******************************************************************************************************************//**
366  * Select Additional Stop Source
367  * @param   p_gpt_base   Pointer to base register of GPT channel.
368  * @param   source       Signal which triggers the action.
369  **********************************************************************************************************************/
HW_GPT_StopSourceSelectAdd(GPT_BASE_PTR p_gpt_base,gpt_trigger_t const source)370 __STATIC_INLINE void HW_GPT_StopSourceSelectAdd (GPT_BASE_PTR p_gpt_base, gpt_trigger_t const source)
371 {
372     p_gpt_base->GTPSR |= (uint32_t) source;
373 }
374 /*******************************************************************************************************************//**
375  * Select Start Source
376  * @param   p_gpt_base   Pointer to base register of GPT channel.
377  * @param   source       Signal which triggers the action.
378  **********************************************************************************************************************/
HW_GPT_StartSourceSelect(GPT_BASE_PTR p_gpt_base,gpt_trigger_t const source)379 __STATIC_INLINE void HW_GPT_StartSourceSelect(GPT_BASE_PTR p_gpt_base, gpt_trigger_t const source)
380 {
381     p_gpt_base->GTSSR = source;
382 }
383 
384 /*******************************************************************************************************************//**
385  * Select Stop Source
386  * @param   p_gpt_base   Pointer to base register of GPT channel.
387  * @param   source       Signal which triggers the action.
388  **********************************************************************************************************************/
HW_GPT_StopSourceSelect(GPT_BASE_PTR p_gpt_base,gpt_trigger_t const source)389 __STATIC_INLINE void HW_GPT_StopSourceSelect(GPT_BASE_PTR p_gpt_base, gpt_trigger_t const source)
390 {
391     p_gpt_base->GTPSR = source;
392 }
393 
394 /*******************************************************************************************************************//**
395  * Select Clear Source
396  * @param   p_gpt_base   Pointer to base register of GPT channel.
397  * @param   source       Signal which triggers the action.
398  **********************************************************************************************************************/
HW_GPT_ClearSourceSelect(GPT_BASE_PTR p_gpt_base,gpt_trigger_t const source)399 __STATIC_INLINE void HW_GPT_ClearSourceSelect(GPT_BASE_PTR p_gpt_base, gpt_trigger_t const source)
400 {
401     p_gpt_base->GTCSR = source;
402 }
403 
404 /*******************************************************************************************************************//**
405  * Select Capture-to-RegA Source
406  * @param   p_gpt_base   Pointer to base register of GPT channel.
407  * @param   source       Signal which triggers the action.
408  **********************************************************************************************************************/
HW_GPT_CaptureASourceSelect(GPT_BASE_PTR p_gpt_base,gpt_trigger_t const source)409 __STATIC_INLINE void HW_GPT_CaptureASourceSelect(GPT_BASE_PTR p_gpt_base, gpt_trigger_t const source)
410 {
411     p_gpt_base->GTICASR = source;
412 }
413 
414 /*******************************************************************************************************************//**
415  * Select Capture-to-RegB Source
416  * @param   p_gpt_base   Pointer to base register of GPT channel.
417  * @param   source       Signal which triggers the action.
418  **********************************************************************************************************************/
HW_GPT_CaptureBSourceSelect(GPT_BASE_PTR p_gpt_base,gpt_trigger_t const source)419 __STATIC_INLINE void HW_GPT_CaptureBSourceSelect(GPT_BASE_PTR p_gpt_base, gpt_trigger_t const source)
420 {
421     p_gpt_base->GTICBSR = source;
422 }
423 
424 /*******************************************************************************************************************//**
425  * Return captured value from register GTCCRA
426  * @param   p_gpt_base   Pointer to base register of GPT channel.
427  **********************************************************************************************************************/
HW_GPT_RegisterAGet(GPT_BASE_PTR p_gpt_base)428 __STATIC_INLINE uint32_t HW_GPT_RegisterAGet(GPT_BASE_PTR p_gpt_base)
429 {
430     return p_gpt_base->GTCCRA;
431 }
432 
433 /*******************************************************************************************************************//**
434  * Initialize channel specific registers to default values.
435  * @param   p_gpt_base   Pointer to base register of GPT channel.
436  * @param   variant      0 for base, 1 for matsu
437  **********************************************************************************************************************/
HW_GPT_RegisterInit(GPT_BASE_PTR p_gpt_base,uint16_t variant)438 __STATIC_INLINE void HW_GPT_RegisterInit(GPT_BASE_PTR p_gpt_base, uint16_t variant)
439 {
440     /* Skip these since they affect all channels, and are initialized in other registers: GTSTR, GTSTP, GTCLR. */
441     p_gpt_base->GTWP = 0xA500UL;
442     p_gpt_base->GTSSR = 0U;
443     p_gpt_base->GTPSR = 0U;
444     p_gpt_base->GTPSR = 0U;
445     p_gpt_base->GTUPSR = 0U;
446     p_gpt_base->GTDNSR = 0U;
447     p_gpt_base->GTICASR = 0U;
448     p_gpt_base->GTICBSR = 0U;
449     p_gpt_base->GTCR = 0U;
450     p_gpt_base->GTUDDTYC = 1U;
451     p_gpt_base->GTIOR = 0U;
452     p_gpt_base->GTINTAD = 0U;
453     p_gpt_base->GTST = 0U;
454     p_gpt_base->GTBER = 0U;
455     p_gpt_base->GTCNT = 0U;
456     p_gpt_base->GTCCRA = 0xFFFFFFFFULL;
457     p_gpt_base->GTCCRB = 0xFFFFFFFFULL;
458     p_gpt_base->GTCCRC = 0xFFFFFFFFULL;
459     p_gpt_base->GTCCRE = 0xFFFFFFFFULL;
460     p_gpt_base->GTPR = 0xFFFFFFFFULL;
461     p_gpt_base->GTPBR = 0xFFFFFFFFULL;
462     p_gpt_base->GTDTCR = 0U;
463     p_gpt_base->GTDVU = 0xFFFFFFFFULL;
464 #ifdef R_GPTA0_BASE
465     if (variant > 0U)
466     {
467         /* These registers available on GPTA only. */
468         p_gpt_base->GTITC = 0U;
469         p_gpt_base->GTPDBR = 0xFFFFFFFFULL;
470         p_gpt_base->GTADTRA = 0xFFFFFFFFULL;
471         p_gpt_base->GTADTRB = 0xFFFFFFFFULL;
472         p_gpt_base->GTADTBRA = 0xFFFFFFFFULL;
473         p_gpt_base->GTADTBRB = 0xFFFFFFFFULL;
474         p_gpt_base->GTADTDBRA = 0xFFFFFFFFULL;
475         p_gpt_base->GTADTDBRB = 0xFFFFFFFFULL;
476         p_gpt_base->GTDVD = 0xFFFFFFFFULL;
477         p_gpt_base->GTDBU = 0xFFFFFFFFULL;
478         p_gpt_base->GTDBD = 0xFFFFFFFFULL;
479         /* GTSOS skipped - read only */
480         p_gpt_base->GTSOTR = 0U;
481     }
482 #else
483     SSP_PARAMETER_NOT_USED(variant);
484 #endif
485 }
486 
487 /*******************************************************************************************************************//**
488  * Return the event associated with the GPT counter overflow
489  * @param   channel           The channel corresponds to the hardware channel number.
490  **********************************************************************************************************************/
HW_GPT_GetCounterOverFlowEvent(uint8_t const channel)491 __STATIC_INLINE elc_event_t HW_GPT_GetCounterOverFlowEvent(uint8_t const channel)
492 {
493     /* For Synergy MCUs, same event of different channels are maintained at fixed offsets from each other.
494      * S7 and S3 has the same offsets (10), while S1 has a different offset (6).
495      */
496     return (elc_event_t) ((uint32_t) ELC_EVENT_GPT0_COUNTER_OVERFLOW +
497            (channel * ((uint32_t) ELC_EVENT_GPT1_COUNTER_OVERFLOW - (uint32_t) ELC_EVENT_GPT0_COUNTER_OVERFLOW)));
498 }
499 
500 /*******************************************************************************************************************//**
501  * Clears the counter counts.
502  * @param  p_gpt_base   Pointer to base register of GPT channel.
503  * @param  channel      Channel number from 0 to 6
504  **********************************************************************************************************************/
HW_GPT_ClearCounter(GPT_BASE_PTR p_gpt_base,uint8_t channel)505 __STATIC_INLINE void HW_GPT_ClearCounter (GPT_BASE_PTR p_gpt_base, uint8_t channel)
506 {
507     /* Setting CCLR bit in GTCSR enables GTCLR register to reset GTCNT register */
508     p_gpt_base->GTCSR_b.CCLR = 1U;
509     /* Clears the GTCNT counter operation for the particular channel */
510     p_gpt_base->GTCLR = (1UL << channel);
511     /* clear CCLR bit */
512     p_gpt_base->GTCSR_b.CCLR = 0U;
513 }
514 
515 /* Common macro for SSP header files. There is also a corresponding SSP_HEADER macro at the top of this file. */
516 SSP_FOOTER
517 
518 #endif /* HW_GPT_COMMON_H */
519