| /aosp_15_r20/external/coreboot/src/soc/intel/denverton_ns/include/soc/ |
| H A D | gpio.h | 31 #define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/skylake/include/soc/ |
| H A D | gpio_defs.h | 12 #define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/cannonlake/include/soc/ |
| H A D | gpio_defs.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
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| H A D | gpio_defs_cnp_h.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/meteorlake/include/soc/ |
| H A D | gpio_defs.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/jasperlake/include/soc/ |
| H A D | gpio_defs.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/tigerlake/include/soc/ |
| H A D | gpio_defs.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
|
| H A D | gpio_defs_pch_h.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/alderlake/include/soc/ |
| H A D | gpio_defs_pch_s.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
|
| H A D | gpio_defs.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/xeon_sp/ebg/include/soc/ |
| H A D | gpio_soc_defs.h | 350 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/elkhartlake/include/soc/ |
| H A D | gpio_defs.h | 8 #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/apollolake/include/soc/ |
| H A D | gpio_apl.h | 468 #define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ macro
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| H A D | gpio_glk.h | 469 #define GPIO_NUM_PAD_CFG_REGS 4 macro
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| /aosp_15_r20/external/coreboot/src/soc/intel/xeon_sp/lbg/include/soc/ |
| H A D | gpio_soc_defs.h | 338 #define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ macro
|