1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_BLOCK_GPIO_DEFS_H 4 #define AMD_BLOCK_GPIO_DEFS_H 5 6 #define GPIO_MASTER_SWITCH 0xfc 7 #define GPIO_MASK_STS_EN BIT(28) 8 #define GPIO_INTERRUPT_EN BIT(30) 9 #define GPIO_WAKE_EN BIT(31) 10 11 #define GPIO_WAKE_STAT_0 0x2f0 12 #define GPIO_WAKE_STAT_1 0x2f4 13 #define GPIO_IRQ_STAT_0 0x2f8 14 #define GPIO_IRQ_STAT_1 0x2fc 15 16 /* Pad trigger type - Level or Edge */ 17 #define GPIO_TRIGGER_EDGE (0 << 8) 18 #define GPIO_TRIGGER_LEVEL (1 << 8) 19 #define GPIO_TRIGGER_MASK (1 << 8) 20 21 /* 22 * Pad polarity: 23 * Level trigger - High or Low 24 * Edge trigger - High (Rising), Low (Falling), Both 25 */ 26 #define GPIO_ACTIVE_HIGH (0 << 9) 27 #define GPIO_ACTIVE_LOW (1 << 9) 28 #define GPIO_ACTIVE_BOTH (2 << 9) 29 #define GPIO_ACTIVE_MASK (3 << 9) 30 31 /* 32 * Pad trigger and polarity configuration. 33 * This determines the filtering applied on the input signal at the pad. 34 */ 35 #define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE) 36 #define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE) 37 #define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE) 38 #define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL) 39 #define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL) 40 41 #define GPIO_INT_ENABLE_STATUS (1 << 11) 42 #define GPIO_INT_ENABLE_DELIVERY (1 << 12) 43 #define GPIO_INT_ENABLE_STATUS_DELIVERY (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) 44 #define GPIO_INT_ENABLE_MASK (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) 45 46 #define GPIO_WAKE_S0i3 (1 << 13) 47 #define GPIO_WAKE_S3 (1 << 14) 48 #define GPIO_WAKE_S4_S5 (1 << 15) 49 #define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) 50 #define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) 51 #define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) 52 #define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) 53 54 #define GPIO_PIN_STS_SHIFT 16 55 #define GPIO_PIN_STS (1 << GPIO_PIN_STS_SHIFT) 56 57 #define GPIO_PULLUP_ENABLE (1 << 20) 58 #define GPIO_PULLDOWN_ENABLE (1 << 21) 59 #define GPIO_PULL_MASK (GPIO_PULLUP_ENABLE | GPIO_PULLDOWN_ENABLE) 60 61 #define GPIO_OUTPUT_SHIFT 22 62 #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) 63 #define GPIO_OUTPUT_ENABLE (1 << 23) 64 #define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT) 65 66 #define GPIO_INT_STATUS (1 << 28) 67 #define GPIO_WAKE_STATUS (1 << 29) 68 #define GPIO_STATUS_MASK (GPIO_INT_STATUS | GPIO_WAKE_STATUS) 69 70 #define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) 71 #define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE 72 73 #define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE 74 #define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE 75 #define GPIO_PULL_PULL_NONE 0 76 77 #define AMD_GPIO_MUX_MASK 0x03 78 79 #define AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER 256 80 /* The GPIO MUX registers for the remote GPIOs are at the end of the remote GPIO bank */ 81 #define AMD_GPIO_REMOTE_GPIO_MUX_OFFSET 0xc0 82 83 /* 84 * Flags used for GPIO configuration. These provide additional information that does not go 85 * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. 86 */ 87 #define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0) 88 #define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0) 89 #define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0) 90 #define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1) 91 #define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1) 92 #define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1) 93 #define GPIO_FLAG_SCI (1 << 2) 94 #define GPIO_FLAG_SMI (1 << 3) 95 96 /* Trigger configuration for GPIO SCI/SMI events. */ 97 #define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ 98 GPIO_FLAG_EVENT_ACTIVE_HIGH) 99 #define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ 100 GPIO_FLAG_EVENT_ACTIVE_LOW) 101 #define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ 102 GPIO_FLAG_EVENT_ACTIVE_HIGH) 103 #define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ 104 GPIO_FLAG_EVENT_ACTIVE_LOW) 105 #define DEB_GLITCH_SHIFT 5 106 #define DEB_GLITCH_NO_DEBOUNCE 0 107 #define DEB_GLITCH_LOW 1 108 #define DEB_GLITCH_HIGH 2 109 #define DEB_GLITCH_REMOVE 3 110 #define GPIO_DEB_PRESERVE_GLITCH (DEB_GLITCH_NO_DEBOUNCE << DEB_GLITCH_SHIFT) 111 #define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) 112 #define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) 113 #define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT) 114 115 #define GPIO_TIMEBASE_61uS 0 116 /* The next value is only 183uS on Picasso. It is 244uS on Cezanne and later SoCs */ 117 #define GPIO_TIMEBASE_183uS (1 << 4) 118 #define GPIO_TIMEBASE_15560uS (1 << 7) 119 #define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS) 120 #define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) 121 #define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) 122 #define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) 123 #define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS) 124 #define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS) 125 #define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS) 126 #define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS) 127 #define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS) 128 #define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS) 129 #define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS) 130 #define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS) 131 #define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS) 132 133 #define GPIO_DEB_MASK 0xff 134 135 /* 136 * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` 137 * Bits that are preserved/untouched: 138 * - Reserved bits 139 * - Drive strength bits 140 * - Read only bits 141 */ 142 #define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \ 143 GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \ 144 GPIO_OUTPUT_MASK | GPIO_STATUS_MASK) 145 146 /* 147 * Several macros are available to declare programming of GPIO pins. The defined macros and 148 * their parameters are: 149 * PAD_NF Define native alternate function for the pin. 150 * pin the pin to be programmed 151 * function the native function 152 * pull pull up, pull down or no pull 153 * PAD_GPI The pin is a GPIO input 154 * pin the pin to be programmed 155 * pull pull up, pull down or no pull 156 * PAD_GPO The pin is a GPIO output 157 * pin the pin to be programmed 158 * direction high or low 159 * PAD_INT The pin is regular interrupt that works while booting 160 * pin the pin to be programmed 161 * pull pull up, pull down or no pull 162 * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES 163 * action STATUS, DELIVERY, STATUS_DELIVERY 164 * PAD_SCI The pin is a SCI source 165 * pin the pin to be programmed 166 * pull pull up, pull down or no pull 167 * event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH 168 * PAD_SMI The pin is a SMI source 169 * pin the pin to be programmed 170 * pull pull up, pull down or no pull 171 * event trigger LEVEL_LOW, LEVEL_HIGH 172 * PAD_NF_SCI Define native alternate function and confiure SCI source 173 * pin the pin to be programmed 174 * function the native function 175 * pull pull up, pull down or no pull 176 * event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH 177 * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI 178 * pin the pin to be programmed 179 * pull pull up, pull down or no pull 180 * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES 181 * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) 182 * PAD_DEBOUNCE The input or interrupt will be debounced 183 * pin the pin to be programmed 184 * pull pull up, pull down or no pull 185 * debounce_type preserve low glitch, preserve high glitch, no glitch 186 * debounce_time the debounce time 187 */ 188 189 #define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \ 190 { \ 191 .gpio = __pin, \ 192 .function = __function, \ 193 .control = __control, \ 194 .flags = __flags, \ 195 } 196 197 #define PAD_CFG_STRUCT(__pin, __function, __control) \ 198 PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0) 199 200 #define PAD_PULL(__pull) GPIO_PULL_ ## __pull 201 #define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir 202 #define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig 203 #define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action 204 #define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig 205 #define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake 206 #define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb 207 208 /* Native function pad configuration with PAD_PULL */ 209 #define PAD_NF(pin, func, pull) \ 210 PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull)) 211 212 /* Native function pad configuration with PAD_OUTPUT */ 213 #define PAD_NFO(pin, func, direction) \ 214 PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_OUTPUT(direction)) 215 216 /* General purpose input pad configuration */ 217 #define PAD_GPI(pin, pull) \ 218 PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull)) 219 220 /* General purpose output pad configuration */ 221 #define PAD_GPO(pin, direction) \ 222 PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction)) 223 224 /* Legacy interrupt pad configuration */ 225 #define PAD_INT(pin, pull, trigger, action) \ 226 PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ 227 PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action)) 228 229 /* SCI pad configuration */ 230 #define PAD_SCI(pin, pull, trigger) \ 231 PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ 232 PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ 233 PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) 234 235 /* SMI pad configuration */ 236 #define PAD_SMI(pin, pull, trigger) \ 237 PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ 238 PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ 239 PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI) 240 241 /* Native function + SCI pad configuration */ 242 #define PAD_NF_SCI(pin, func, pull, trigger) \ 243 PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_ ## func, \ 244 PAD_PULL(pull), \ 245 PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) 246 247 /* WAKE pad configuration */ 248 #define PAD_WAKE(pin, pull, trigger, type) \ 249 PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ 250 PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type)) 251 252 /* pin debounce configuration */ 253 #define PAD_DEBOUNCE(pin, pull, type, time) \ 254 PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ 255 PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time)) 256 257 /* Wake + debounce configuration */ 258 #define PAD_WAKE_DEBOUNCE(pin, pull, trigger, waketype, debtype, time) \ 259 PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ 260 PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(waketype) | \ 261 PAD_DEBOUNCE_CONFIG(debtype) | PAD_DEBOUNCE_CONFIG(time)) 262 263 /* No-connect pad - configured as input with PULL_DOWN */ 264 #define PAD_NC(pin) \ 265 PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN)) 266 267 #define GEVENT_0 0 268 #define GEVENT_1 1 269 #define GEVENT_2 2 270 #define GEVENT_3 3 271 #define GEVENT_4 4 272 #define GEVENT_5 5 273 #define GEVENT_6 6 274 #define GEVENT_7 7 275 #define GEVENT_8 8 276 #define GEVENT_9 9 277 #define GEVENT_10 10 278 #define GEVENT_11 11 279 #define GEVENT_12 12 280 #define GEVENT_13 13 281 #define GEVENT_14 14 282 #define GEVENT_15 15 283 #define GEVENT_16 16 284 #define GEVENT_17 17 285 #define GEVENT_18 18 286 #define GEVENT_19 19 287 #define GEVENT_20 20 288 #define GEVENT_21 21 289 #define GEVENT_22 22 290 #define GEVENT_23 23 291 #define GEVENT_24 24 292 #define GEVENT_25 25 293 #define GEVENT_26 26 294 #define GEVENT_27 27 295 #define GEVENT_28 28 296 #define GEVENT_29 29 297 #define GEVENT_30 30 298 #define GEVENT_31 31 299 300 #endif /* AMD_BLOCK_GPIO_DEFS_H */ 301