1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DENVERTON_NS_GPIO_DEFS_H_ 4 #define _DENVERTON_NS_GPIO_DEFS_H_ 5 6 #include <soc/pcr.h> 7 8 /* 9 * There are 3 GPIO groups. North Community, South Community DFX/Group0/Group1. 10 * The GPIO groups are accessed through register blocks called communities. 11 */ 12 13 #define V_PCH_GPIO_NC_PAD_MAX 41 14 #define V_PCH_GPIO_SC_DFX_PAD_MAX 18 15 #define V_PCH_GPIO_SC0_PAD_MAX 53 16 #define V_PCH_GPIO_SC1_PAD_MAX 42 17 #define V_PCH_GPIO_GROUP_MAX 4 18 19 #define TOTAL_PADS (V_PCH_GPIO_NC_PAD_MAX + V_PCH_GPIO_SC_DFX_PAD_MAX\ 20 + V_PCH_GPIO_SC0_PAD_MAX + V_PCH_GPIO_SC1_PAD_MAX) 21 22 // 23 // GPIO Community 0 Private Configuration Registers 24 // 25 26 // 27 // Power Group NORTH_ALL 28 // 29 #define R_PCH_PCR_GPIO_NC_PAD_OWN 0x20 30 #define R_PCH_PCR_GPIO_NC_GPI_VWM_EN 0x70 31 #define R_PCH_PCR_GPIO_NC_PADCFGLOCK 0x90 32 #define R_PCH_PCR_GPIO_NC_PADCFGLOCKTX 0x94 33 #define R_PCH_PCR_GPIO_NC1_PADCFGLOCK_1 0x98 34 #define R_PCH_PCR_GPIO_NC1_PADCFGLOCKTX_1 0x9C 35 #define R_PCH_PCR_GPIO_NC_HOSTSW_OWN 0xC0 36 #define R_PCH_PCR_GPIO_NC_GPI_IS 0x0100 37 #define R_PCH_PCR_GPIO_NC_GPI_IE 0x0120 38 #define R_PCH_PCR_GPIO_NC_GPI_GPE_STS 0x0140 39 #define R_PCH_PCR_GPIO_NC_GPI_GPE_EN 0x0160 40 #define R_PCH_PCR_GPIO_NC_SMI_STS 0x0180 41 #define R_PCH_PCR_GPIO_NC_SMI_EN 0x01A0 42 #define R_PCH_PCR_GPIO_NC_NMI_STS 0x01C0 43 #define R_PCH_PCR_GPIO_NC_NMI_EN 0x01E0 44 #define R_PCH_PCR_GPIO_NC_PADCFG_OFFSET 0x400 45 46 // 47 // GPIO Community 1 Private Configuration Registers 48 // 49 50 // 51 // Power Group SOUTH_DFX 52 // 53 #define R_PCH_PCR_GPIO_SC_DFX_PAD_OWN 0x20 54 #define R_PCH_PCR_GPIO_SC_DFX_GPI_VWM_EN 0x70 55 #define R_PCH_PCR_GPIO_SC_DFX_PADCFGLOCK 0x90 56 #define R_PCH_PCR_GPIO_SC_DFX_PADCFGLOCKTX 0x94 57 #define R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN 0xC0 58 #define R_PCH_PCR_GPIO_SC_DFX_GPI_IS 0x0100 59 #define R_PCH_PCR_GPIO_SC_DFX_GPI_IE 0x0120 60 #define R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS 0x0140 61 #define R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN 0x0160 62 #define R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET 0x400 63 // 64 // Power Group SOUTH_GROUP0 65 // 66 #define R_PCH_PCR_GPIO_SC0_PAD_OWN 0x2C 67 #define R_PCH_PCR_GPIO_SC0_GPI_VWM_EN 0x74 68 #define R_PCH_PCR_GPIO_SC0_PADCFGLOCK 0x98 69 #define R_PCH_PCR_GPIO_SC0_PADCFGLOCKTX 0x9C 70 #define R_PCH_PCR_GPIO_SC0_HOSTSW_OWN 0xC4 71 #define R_PCH_PCR_GPIO_SC0_GPI_IS 0x0104 72 #define R_PCH_PCR_GPIO_SC0_GPI_IE 0x0124 73 #define R_PCH_PCR_GPIO_SC0_GPI_GPE_STS 0x0144 74 #define R_PCH_PCR_GPIO_SC0_GPI_GPE_EN 0x0164 75 #define R_PCH_PCR_GPIO_SC0_SMI_STS 0x0184 76 #define R_PCH_PCR_GPIO_SC0_SMI_EN 0x01A4 77 #define R_PCH_PCR_GPIO_SC0_NMI_STS 0x01C4 78 #define R_PCH_PCR_GPIO_SC0_NMI_EN 0x01E4 79 #define R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET 0x490 80 // 81 // Power Group SOUTH_GROUP1 82 // 83 #define R_PCH_PCR_GPIO_SC1_PAD_OWN 0x48 84 #define R_PCH_PCR_GPIO_SC1_GPI_VWM_EN 0x7C 85 #define R_PCH_PCR_GPIO_SC1_PADCFGLOCK 0xA8 86 #define R_PCH_PCR_GPIO_SC1_PADCFGLOCKTX 0xAC 87 #define R_PCH_PCR_GPIO_SC1_HOSTSW_OWN 0xCC 88 #define R_PCH_PCR_GPIO_SC1_GPI_IS 0x010C 89 #define R_PCH_PCR_GPIO_SC1_GPI_IE 0x012C 90 #define R_PCH_PCR_GPIO_SC1_GPI_GPE_STS 0x014C 91 #define R_PCH_PCR_GPIO_SC1_GPI_GPE_EN 0x016C 92 #define R_PCH_PCR_GPIO_SC1_SMI_STS 0x018C 93 #define R_PCH_PCR_GPIO_SC1_SMI_EN 0x01AC 94 #define R_PCH_PCR_GPIO_SC1_NMI_STS 0x01CC 95 #define R_PCH_PCR_GPIO_SC1_NMI_EN 0x01EC 96 #define R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET 0x638 97 98 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_NORTH_ALL_0 0x90 99 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_NORTH_ALL_0 0x94 100 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_NORTH_ALL_1 0x98 101 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_NORTH_ALL_1 0x9C 102 103 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_DFX_0 0x90 104 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_DFX_0 0x94 105 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP0_0 0x98 106 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP0_0 0x9C 107 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP0_1 0xA0 108 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP0_1 0xA4 109 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP1_0 0xA8 110 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP1_0 0xAC 111 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP1_1 0xB0 112 #define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP1_1 0xB4 113 114 // 115 // Pad Configuration Register DW0 116 // 117 118 // Pad Reset Config 119 #define B_PCH_GPIO_RST_CONF ((1 << 31) | (1 << 30)) 120 #define N_PCH_GPIO_RST_CONF 30 121 #define V_PCH_GPIO_RST_CONF_POW_GOOD 0x00 122 #define V_PCH_GPIO_RST_CONF_DEEP_RST 0x01 123 #define V_PCH_GPIO_RST_CONF_GPIO_RST 0x02 124 #define V_PCH_GPIO_RST_CONF_RESUME_RST 0x03 // Only for GPD Group 125 126 // RX Pad State Select 127 #define B_PCH_GPIO_RX_PAD_STATE (1 << 29) 128 #define N_PCH_GPIO_RX_PAD_STATE 29 129 #define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00 130 #define V_PCH_GPIO_RX_PAD_STATE_INT 0x01 131 132 // RX Raw Override to 1 133 #define B_PCH_GPIO_RX_RAW1 (1 << 28) 134 #define N_PCH_GPIO_RX_RAW1 28 135 #define V_PCH_GPIO_RX_RAW1_DIS 0x00 136 #define V_PCH_GPIO_RX_RAW1_EN 0x01 137 138 // RX Level/Edge Configuration 139 #define B_PCH_GPIO_RX_LVL_EDG ((1 << 26) | (1 << 25)) 140 #define N_PCH_GPIO_RX_LVL_EDG 25 141 #define V_PCH_GPIO_RX_LVL_EDG_LVL 0x00 142 #define V_PCH_GPIO_RX_LVL_EDG_EDG 0x01 143 #define V_PCH_GPIO_RX_LVL_EDG_0 0x02 144 #define V_PCH_GPIO_RX_LVL_EDG_RIS_FAL 0x03 145 146 // RX Level/Edge Configuration 147 #define B_PCH_GPIO_PRE_GFRX_SEL (1 << 24) 148 #define N_PCH_GPIO_PRE_GFRX_SEL 24 149 #define V_PCH_GPIO_PRE_GFRX_SEL_DIS 0x00 150 #define V_PCH_GPIO_PRE_GFRX_SEL_EN 0x01 151 152 // RX Invert 153 #define B_PCH_GPIO_RXINV (1 << 23) 154 #define N_PCH_GPIO_RXINV 23 155 #define V_PCH_GPIO_RXINV_NO 0x00 156 #define V_PCH_GPIO_RXINV_YES 0x01 157 158 // RXTXENCFG 159 #define B_PCH_GPIO_RXTXENCFG ((1 << 22) | (1 << 21)) 160 #define N_PCH_GPIO_RXTXENCFG 21 161 #define V_PCH_GPIO_RXTXENCFG_DEF_FUN 0x00 162 #define V_PCH_GPIO_RXTXENCFG_TX_EN_L 0x01 163 #define V_PCH_GPIO_RXTXENCFG_TX_EN_H 0x02 164 #define V_PCH_GPIO_RXTXENCFG_TXRXEN 0x03 165 166 // GPIO Input Route IOxAPIC 167 #define B_PCH_GPIO_RX_APIC_ROUTE (1 << 20) 168 #define N_PCH_GPIO_RX_APIC_ROUTE 20 169 #define V_PCH_GPIO_RX_APIC_ROUTE_DIS 0x00 170 #define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01 171 172 // GPIO Input Route SCI 173 #define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19) 174 #define N_PCH_GPIO_RX_SCI_ROUTE 19 175 #define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 176 #define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01 177 178 // GPIO Input Route SMI 179 #define B_PCH_GPIO_RX_SMI_ROUTE (1 << 18) 180 #define N_PCH_GPIO_RX_SMI_ROUTE 18 181 #define V_PCH_GPIO_RX_SMI_ROUTE_DIS 0x00 182 #define V_PCH_GPIO_RX_SMI_ROUTE_EN 0x01 183 184 // GPIO Input Route NMI 185 #define B_PCH_GPIO_RX_NMI_ROUTE (1 << 17) 186 #define N_PCH_GPIO_RX_NMI_ROUTE 17 187 #define V_PCH_GPIO_RX_NMI_ROUTE_DIS 0x00 188 #define V_PCH_GPIO_RX_NMI_ROUTE_EN 0x01 189 190 // GPIO Pad Mode 191 #define B_PCH_GPIO_PAD_MODE ((1 << 12) | (1 << 11) | (1 << 10)) 192 #define N_PCH_GPIO_PAD_MODE 10 193 #define V_PCH_GPIO_PAD_MODE_GPIO 0 194 #define V_PCH_GPIO_PAD_MODE_NAT_1 1 195 #define V_PCH_GPIO_PAD_MODE_NAT_2 2 196 #define V_PCH_GPIO_PAD_MODE_NAT_3 3 197 #define V_PCH_GPIO_PAD_MODE_NAT_4 4 198 #define V_PCH_GPIO_PAD_MODE_NAT_5 5 199 #define V_PCH_GPIO_PAD_MODE_NAT_6 6 200 #define V_PCH_GPIO_PAD_MODE_NAT_7 7 201 202 // GPIO RX Disable 203 #define B_PCH_GPIO_RXDIS (1 << 9) 204 #define N_PCH_GPIO_RXDIS 9 205 #define V_PCH_GPIO_RXDIS_EN 0x00 206 #define V_PCH_GPIO_RXDIS_DIS 0x01 207 208 // GPIO TX Disable 209 #define B_PCH_GPIO_TXDIS (1 << 8) 210 #define N_PCH_GPIO_TXDIS 8 211 #define V_PCH_GPIO_TXDIS_EN 0x00 212 #define V_PCH_GPIO_TXDIS_DIS 0x01 213 214 // GPIO RX State 215 #define B_PCH_GPIO_RX_STATE (1 << 1) 216 #define N_PCH_GPIO_RX_STATE 1 217 #define V_PCH_GPIO_RX_STATE_LOW 0x00 218 #define V_PCH_GPIO_RX_STATE_HIGH 0x01 219 220 // GPIO TX State 221 #define B_PCH_GPIO_TX_STATE (1 << 0) 222 #define N_PCH_GPIO_TX_STATE 0 223 #define V_PCH_GPIO_TX_STATE_LOW 0x00 224 #define V_PCH_GPIO_TX_STATE_HIGH 0x01 225 226 // 227 // Pad Configuration Register DW1 228 // 229 230 // Padtol 231 #define B_PCH_GPIO_PADTOL (1 << 25) 232 #define N_PCH_GPIO_PADTOL 25 233 #define V_PCH_GPIO_PADTOL_NONE 0x00 234 #define V_PCH_GPIO_PADTOL_CLEAR 0x00 235 #define V_PCH_GPIO_PADTOL_SET 0x01 236 237 // Termination 238 #define B_PCH_GPIO_TERM ((1 << 13) | (1 << 12) | (1 << 11) | (1 << 10)) 239 #define N_PCH_GPIO_TERM 10 240 #define V_PCH_GPIO_TERM_WPD_NONE 0x00 241 #define V_PCH_GPIO_TERM_WPD_5K 0x02 242 #define V_PCH_GPIO_TERM_WPD_20K 0x04 243 #define V_PCH_GPIO_TERM_WPU_NONE 0x08 244 #define V_PCH_GPIO_TERM_WPU_1K 0x09 245 #define V_PCH_GPIO_TERM_WPU_2K 0x0B 246 #define V_PCH_GPIO_TERM_WPU_5K 0x0A 247 #define V_PCH_GPIO_TERM_WPU_20K 0x0C 248 #define V_PCH_GPIO_TERM_WPU_1K_2K 0x0D 249 #define V_PCH_GPIO_TERM_NATIVE 0x0F 250 251 #define PID_NorthCommunity PID_GPIOCOM0 252 #define PID_SouthCommunity PID_GPIOCOM1 253 254 // GPIO_MISC0 255 // HSUART0: 101, 102, 13, 98 256 // HSUART1: 96, 97,95 94 257 258 #define GPIO_SMB3_CLTT_DATA 12 259 #define R_PAD_CFG_DW0_SMB3_CLTT_DATA 0x490 260 #define PID_SMB3_CLTT_DATA PID_SouthCommunity 261 262 #define GPIO_SMB3_CLTT_CLK 13 263 #define R_PAD_CFG_DW0_SMB3_CLTT_CLK 0x498 264 #define PID_SMB3_CLTT_CLK PID_SouthCommunity 265 266 #define GPIO_PCIE_CLKREQ5_N 98 267 #define R_PAD_CFG_DW0_PCIE_CLKREQ5_N 0x4A0 268 #define PID_PCIE_CLKREQ5_N PID_SouthCommunity 269 270 #define GPIO_PCIE_CLKREQ6_N 99 271 #define R_PAD_CFG_DW0_PCIE_CLKREQ6_N 0x4a8 272 #define PID_PCIE_CLKREQ6_N PID_SouthCommunity 273 274 #define GPIO_PCIE_CLKREQ7_N 100 275 #define R_PAD_CFG_DW0_PCIE_CLKREQ7_N 0x4b0 276 #define PID_PCIE_CLKREQ7_N PID_SouthCommunity 277 278 #define GPIO_UART0_RXD 101 279 #define R_PAD_CFG_DW0_UART0_RXD 0x4b8 280 #define PID_UART0_RXD PID_SouthCommunity 281 282 #define GPIO_UART0_TXD 102 283 #define R_PAD_CFG_DW0_UART0_TXD 0x4c0 284 #define PID_UART0_TXD PID_SouthCommunity 285 286 #define GPIO_UART1_RXD 96 287 #define R_PAD_CFG_DW0_UART1_RXD 0x5b8 288 #define PID_UART1_RXD PID_SouthCommunity 289 290 #define GPIO_UART1_TXD 97 291 #define R_PAD_CFG_DW0_UART1_TXD 0x5c0 292 #define PID_UART1_TXD PID_SouthCommunity 293 294 #define GPIO_SATA1_SDOUT 95 295 #define R_PAD_CFG_DW0_SATA1_SDOUT 0x5b0 296 #define PID_SATA1_SDOUT PID_SouthCommunity 297 298 #define GPIO_SATA0_SDOUT 94 299 #define R_PAD_CFG_DW0_SATA0_SDOUT 0x5a8 300 #define PID_SATA0_SDOUT PID_SouthCommunity 301 302 /// 303 /// Denverton GPIO Groups 304 /// 305 306 #define GPIO_DNV_GROUP_NC 0x0100 307 #define GPIO_DNV_GROUP_SC_DFX 0x0101 308 #define GPIO_DNV_GROUP_SC0 0x0102 309 #define GPIO_DNV_GROUP_SC1 0x0103 310 #define GPIO_DNV_GROUP_MIN GPIO_DNV_GROUP_NC 311 #define GPIO_DNV_GROUP_MAX GPIO_DNV_GROUP_SC1 312 #define NORTH_ALL_GBE0_SDP0 0x01000000 313 #define NORTH_ALL_GBE1_SDP0 0x01000001 314 #define NORTH_ALL_GBE0_SDP1 0x01000002 315 #define NORTH_ALL_GBE1_SDP1 0x01000003 316 #define NORTH_ALL_GBE0_SDP2 0x01000004 317 #define NORTH_ALL_GBE1_SDP2 0x01000005 318 #define NORTH_ALL_GBE0_SDP3 0x01000006 319 #define NORTH_ALL_GBE1_SDP3 0x01000007 320 #define NORTH_ALL_GBE2_LED0 0x01000008 321 #define NORTH_ALL_GBE2_LED1 0x01000009 322 #define NORTH_ALL_GBE0_I2C_CLK 0x0100000A 323 #define NORTH_ALL_GBE0_I2C_DATA 0x0100000B 324 #define NORTH_ALL_GBE1_I2C_CLK 0x0100000C 325 #define NORTH_ALL_GBE1_I2C_DATA 0x0100000D 326 #define NORTH_ALL_NCSI_RXD0 0x0100000E 327 #define NORTH_ALL_NCSI_CLK_IN 0x0100000F 328 #define NORTH_ALL_NCSI_RXD1 0x01000010 329 #define NORTH_ALL_NCSI_CRS_DV 0x01000011 330 #define NORTH_ALL_NCSI_ARB_IN 0x01000012 331 #define NORTH_ALL_NCSI_TX_EN 0x01000013 332 #define NORTH_ALL_NCSI_TXD0 0x01000014 333 #define NORTH_ALL_NCSI_TXD1 0x01000015 334 #define NORTH_ALL_NCSI_ARB_OUT 0x01000016 335 #define NORTH_ALL_GBE0_LED0 0x01000017 336 #define NORTH_ALL_GBE0_LED1 0x01000018 337 #define NORTH_ALL_GBE1_LED0 0x01000019 338 #define NORTH_ALL_GBE1_LED1 0x0100001A 339 #define NORTH_ALL_GPIO_0 0x0100001B 340 #define NORTH_ALL_PCIE_CLKREQ0_N 0x0100001C 341 #define NORTH_ALL_PCIE_CLKREQ1_N 0x0100001D 342 #define NORTH_ALL_PCIE_CLKREQ2_N 0x0100001E 343 #define NORTH_ALL_PCIE_CLKREQ3_N 0x0100001F 344 #define NORTH_ALL_PCIE_CLKREQ4_N 0x01000020 345 #define NORTH_ALL_GPIO_1 0x01000021 346 #define NORTH_ALL_GPIO_2 0x01000022 347 #define NORTH_ALL_SVID_ALERT_N 0x01000023 348 #define NORTH_ALL_SVID_DATA 0x01000024 349 #define NORTH_ALL_SVID_CLK 0x01000025 350 #define NORTH_ALL_THERMTRIP_N 0x01000026 351 #define NORTH_ALL_PROCHOT_N 0x01000027 352 #define NORTH_ALL_MEMHOT_N 0x01000028 353 #define SOUTH_DFX_DFX_PORT_CLK0 0x01010000 354 #define SOUTH_DFX_DFX_PORT_CLK1 0x01010001 355 #define SOUTH_DFX_DFX_PORT0 0x01010002 356 #define SOUTH_DFX_DFX_PORT1 0x01010003 357 #define SOUTH_DFX_DFX_PORT2 0x01010004 358 #define SOUTH_DFX_DFX_PORT3 0x01010005 359 #define SOUTH_DFX_DFX_PORT4 0x01010006 360 #define SOUTH_DFX_DFX_PORT5 0x01010007 361 #define SOUTH_DFX_DFX_PORT6 0x01010008 362 #define SOUTH_DFX_DFX_PORT7 0x01010009 363 #define SOUTH_DFX_DFX_PORT8 0x0101000A 364 #define SOUTH_DFX_DFX_PORT9 0x0101000B 365 #define SOUTH_DFX_DFX_PORT10 0x0101000C 366 #define SOUTH_DFX_DFX_PORT11 0x0101000D 367 #define SOUTH_DFX_DFX_PORT12 0x0101000E 368 #define SOUTH_DFX_DFX_PORT13 0x0101000F 369 #define SOUTH_DFX_DFX_PORT14 0x01010010 370 #define SOUTH_DFX_DFX_PORT15 0x01010011 371 #define SOUTH_GROUP0_SMB3_CLTT_DATA 0x01020000 372 #define SOUTH_GROUP0_SMB3_CLTT_CLK 0x01020001 373 #define SOUTH_GROUP0_GPIO_12 0x01020000 374 #define SOUTH_GROUP0_SMB5_GBE_ALRT_N 0x01020001 375 #define SOUTH_GROUP0_PCIE_CLKREQ5_N 0x01020002 376 #define SOUTH_GROUP0_PCIE_CLKREQ6_N 0x01020003 377 #define SOUTH_GROUP0_PCIE_CLKREQ7_N 0x01020004 378 #define SOUTH_GROUP0_UART0_RXD 0x01020005 379 #define SOUTH_GROUP0_UART0_TXD 0x01020006 380 #define SOUTH_GROUP0_SMB5_GBE_CLK 0x01020007 381 #define SOUTH_GROUP0_SMB5_GBE_DATA 0x01020008 382 #define SOUTH_GROUP0_ERROR2_N 0x01020009 383 #define SOUTH_GROUP0_ERROR1_N 0x0102000A 384 #define SOUTH_GROUP0_ERROR0_N 0x0102000B 385 #define SOUTH_GROUP0_IERR_N 0x0102000C 386 #define SOUTH_GROUP0_MCERR_N 0x0102000D 387 #define SOUTH_GROUP0_SMB0_LEG_CLK 0x0102000E 388 #define SOUTH_GROUP0_SMB0_LEG_DATA 0x0102000F 389 #define SOUTH_GROUP0_SMB0_LEG_ALRT_N 0x01020010 390 #define SOUTH_GROUP0_SMB1_HOST_DATA 0x01020011 391 #define SOUTH_GROUP0_SMB1_HOST_CLK 0x01020012 392 #define SOUTH_GROUP0_SMB2_PECI_DATA 0x01020013 393 #define SOUTH_GROUP0_SMB2_PECI_CLK 0x01020014 394 #define SOUTH_GROUP0_SMB4_CSME0_DATA 0x01020015 395 #define SOUTH_GROUP0_SMB4_CSME0_CLK 0x01020016 396 #define SOUTH_GROUP0_SMB4_CSME0_ALRT_N 0x01020017 397 #define SOUTH_GROUP0_USB_OC0_N 0x01020018 398 #define SOUTH_GROUP0_FLEX_CLK_SE0 0x01020019 399 #define SOUTH_GROUP0_FLEX_CLK_SE1 0x0102001A 400 #define SOUTH_GROUP0_GPIO_4 0x0102001B 401 #define SOUTH_GROUP0_GPIO_5 0x0102001C 402 #define SOUTH_GROUP0_GPIO_6 0x0102001D 403 #define SOUTH_GROUP0_GPIO_7 0x0102001E 404 #define SOUTH_GROUP0_SATA0_LED_N 0x0102001F 405 #define SOUTH_GROUP0_SATA1_LED_N 0x01020020 406 #define SOUTH_GROUP0_SATA_PDETECT0 0x01020021 407 #define SOUTH_GROUP0_SATA_PDETECT1 0x01020022 408 #define SOUTH_GROUP0_SATA0_SDOUT 0x01020023 409 #define SOUTH_GROUP0_SATA1_SDOUT 0x01020024 410 #define SOUTH_GROUP0_UART1_RXD 0x01020025 411 #define SOUTH_GROUP0_UART1_TXD 0x01020026 412 #define SOUTH_GROUP0_GPIO_8 0x01020027 413 #define SOUTH_GROUP0_GPIO_9 0x01020028 414 #define SOUTH_GROUP0_TCK 0x01020029 415 #define SOUTH_GROUP0_TRST_N 0x0102002A 416 #define SOUTH_GROUP0_TMS 0x0102002B 417 #define SOUTH_GROUP0_TDI 0x0102002C 418 #define SOUTH_GROUP0_TDO 0x0102002D 419 #define SOUTH_GROUP0_CX_PRDY_N 0x0102002E 420 #define SOUTH_GROUP0_CX_PREQ_N 0x0102002F 421 #define SOUTH_GROUP0_CTBTRIGINOUT 0x01020030 422 #define SOUTH_GROUP0_CTBTRIGOUT 0x01020031 423 #define SOUTH_GROUP0_DFX_SPARE2 0x01020032 424 #define SOUTH_GROUP0_DFX_SPARE3 0x01020033 425 #define SOUTH_GROUP0_DFX_SPARE4 0x01020034 426 #define SOUTH_GROUP1_SUSPWRDNACK 0x01030000 427 #define SOUTH_GROUP1_PMU_SUSCLK 0x01030001 428 #define SOUTH_GROUP1_ADR_TRIGGER 0x01030002 429 #define SOUTH_GROUP1_PMU_AC_PRESENT 0x01030002 430 #define SOUTH_GROUP1_PMU_SLP_S45_N 0x01030003 431 #define SOUTH_GROUP1_PMU_SLP_S3_N 0x01030004 432 #define SOUTH_GROUP1_PMU_WAKE_N 0x01030005 433 #define SOUTH_GROUP1_PMU_PWRBTN_N 0x01030006 434 #define SOUTH_GROUP1_PMU_RESETBUTTON_N 0x01030007 435 #define SOUTH_GROUP1_PMU_PLTRST_N 0x01030008 436 #define SOUTH_GROUP1_SUS_STAT_N 0x01030009 437 #define SOUTH_GROUP1_SLP_S0IX_N 0x0103000A 438 #define SOUTH_GROUP1_SPI_CS0_N 0x0103000B 439 #define SOUTH_GROUP1_SPI_CS1_N 0x0103000C 440 #define SOUTH_GROUP1_SPI_MOSI_IO0 0x0103000D 441 #define SOUTH_GROUP1_SPI_MISO_IO1 0x0103000E 442 #define SOUTH_GROUP1_SPI_IO2 0x0103000F 443 #define SOUTH_GROUP1_SPI_IO3 0x01030010 444 #define SOUTH_GROUP1_SPI_CLK 0x01030011 445 #define SOUTH_GROUP1_SPI_CLK_LOOPBK 0x01030012 446 #define SOUTH_GROUP1_ESPI_IO0 0x01030013 447 #define SOUTH_GROUP1_ESPI_IO1 0x01030014 448 #define SOUTH_GROUP1_ESPI_IO2 0x01030015 449 #define SOUTH_GROUP1_ESPI_IO3 0x01030016 450 #define SOUTH_GROUP1_ESPI_CS0_N 0x01030017 451 #define SOUTH_GROUP1_ESPI_CLK 0x01030018 452 #define SOUTH_GROUP1_ESPI_RST_N 0x01030019 453 #define SOUTH_GROUP1_ESPI_ALRT0_N 0x0103001A 454 #define SOUTH_GROUP1_GPIO_10 0x0103001B 455 #define SOUTH_GROUP1_GPIO_11 0x0103001C 456 #define SOUTH_GROUP1_ESPI_CLK_LOOPBK 0x0103001D 457 #define SOUTH_GROUP1_EMMC_CMD 0x0103001E 458 #define SOUTH_GROUP1_EMMC_STROBE 0x0103001F 459 #define SOUTH_GROUP1_EMMC_CLK 0x01030020 460 #define SOUTH_GROUP1_EMMC_D0 0x01030021 461 #define SOUTH_GROUP1_EMMC_D1 0x01030022 462 #define SOUTH_GROUP1_EMMC_D2 0x01030023 463 #define SOUTH_GROUP1_EMMC_D3 0x01030024 464 #define SOUTH_GROUP1_EMMC_D4 0x01030025 465 #define SOUTH_GROUP1_EMMC_D5 0x01030026 466 #define SOUTH_GROUP1_EMMC_D6 0x01030027 467 #define SOUTH_GROUP1_EMMC_D7 0x01030028 468 #define SOUTH_GROUP1_GPIO_3 0x01030029 469 470 // BIT15-0 - pad number 471 // BIT31-16 - group info 472 // BIT23- 16 - group index 473 // BIT31- 24 - chipset ID (default to 0x01) 474 #define PAD_INFO_MASK 0x0000FFFF 475 #define GROUP_INFO_POSITION 16 476 #define GROUP_INFO_MASK 0xFFFF0000 477 #define GROUP_INDEX_MASK 0x00FF0000 478 #define UNIQUE_ID_MASK 0xFF000000 479 #define UNIQUE_ID_POSITION 24 480 481 #define GPIO_PAD_DEF(Group, Pad) (uint32_t)((Group << 16) + Pad) 482 #define GPIO_GET_GROUP_INDEX(Group) (Group & 0xFF) 483 #define GPIO_GET_GROUP_FROM_PAD(Pad) (Pad >> 16) 484 #define GPIO_GET_GROUP_INDEX_FROM_PAD(Pad) GPIO_GET_GROUP_INDEX((Pad >> 16)) 485 #define GPIO_GET_PAD_NUMBER(Pad) (Pad & 0xFFFF) 486 #define GPIO_GET_CHIPSET_ID(Pad) (Pad >> 24) 487 488 #endif /* _DENVERTON_NS_GPIO_DEFS_H_ */ 489