1 /*
2  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef PLAT_SOCFPGA_DEF_H
9 #define PLAT_SOCFPGA_DEF_H
10 
11 #include "agilex5_memory_controller.h"
12 #include "agilex5_system_manager.h"
13 #include <platform_def.h>
14 
15 /* Platform Setting */
16 #define PLATFORM_MODEL						PLAT_SOCFPGA_AGILEX5
17 #define BOOT_SOURCE						BOOT_SOURCE_SDMMC
18 #define MMC_DEVICE_TYPE						1  /* MMC = 0, SD = 1 */
19 #define XLAT_TABLES_V2						U(1)
20 #define PLAT_PRIMARY_CPU_A55					0x000
21 #define PLAT_PRIMARY_CPU_A76					0x200
22 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT				MPIDR_AFF2_SHIFT
23 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT				MPIDR_AFF1_SHIFT
24 #define PLAT_L2_RESET_REQ			0xB007C0DE
25 
26 /* System Counter */
27 /* TODO: Update back to 400MHz.
28  * This shall be updated to read from L4 clock instead of hardcoded.
29  */
30 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS				(400000000)
31 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ				(400)
32 
33 /* FPGA config helpers */
34 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR				0x400000
35 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE				0x2000000
36 
37 /* QSPI Setting */
38 #define CAD_QSPIDATA_OFST					0x10900000
39 #define CAD_QSPI_OFFSET						0x108d2000
40 
41 /* Register Mapping */
42 #define SOCFPGA_CCU_NOC_REG_BASE				0x1c000000
43 #define SOCFPGA_F2SDRAMMGR_REG_BASE				0x18001000
44 
45 #define SOCFPGA_MMC_REG_BASE					0x10808000
46 #define SOCFPGA_MEMCTRL_REG_BASE				0x108CC000
47 #define SOCFPGA_RSTMGR_REG_BASE					0x10d11000
48 #define SOCFPGA_SYSMGR_REG_BASE					0x10d12000
49 #define SOCFPGA_PINMUX_REG_BASE					0x10d13000
50 #define SOCFPGA_NAND_REG_BASE					0x10B80000
51 #define SOCFPGA_ECC_QSPI_REG_BASE				0x10A22000
52 
53 #define SOCFPGA_L4_PER_SCR_REG_BASE				0x10d21000
54 #define SOCFPGA_L4_SYS_SCR_REG_BASE				0x10d21100
55 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE				0x10d21200
56 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE				0x10d21300
57 
58 /* Define maximum page size for NAND flash devices */
59 #define PLATFORM_MTD_MAX_PAGE_SIZE				U(0x2000)
60 
61 /*******************************************************************************
62  * Platform memory map related constants
63  ******************************************************************************/
64 #define DRAM_BASE						(0x80000000)
65 #define DRAM_SIZE						(0x80000000)
66 
67 #define OCRAM_BASE						(0x00000000)
68 #define OCRAM_SIZE						(0x00080000)
69 
70 #define MEM64_BASE						(0x0080000000)
71 #define MEM64_SIZE						(0x0080000000)
72 
73 //128MB PSS
74 #define PSS_BASE						(0x10000000)
75 #define PSS_SIZE						(0x08000000)
76 
77 //64MB MPFE
78 #define MPFE_BASE						(0x18000000)
79 #define MPFE_SIZE						(0x04000000)
80 
81 //16MB CCU
82 #define CCU_BASE						(0x1C000000)
83 #define CCU_SIZE						(0x01000000)
84 
85 //1MB GIC
86 #define GIC_BASE						(0x1D000000)
87 #define GIC_SIZE						(0x00100000)
88 
89 #define BL2_BASE						(0x00000000)
90 #define BL2_LIMIT						(0x0002b000)
91 
92 #define BL31_BASE						(0x80000000)
93 #define BL31_LIMIT						(0x82000000)
94 
95 /*******************************************************************************
96  * UART related constants
97  ******************************************************************************/
98 #define PLAT_UART0_BASE						(0x10C02000)
99 #define PLAT_UART1_BASE						(0x10C02100)
100 
101 /*******************************************************************************
102  * WDT related constants
103  ******************************************************************************/
104 #define WDT_BASE			(0x10D00200)
105 
106 /*******************************************************************************
107  * GIC related constants
108  ******************************************************************************/
109 #define PLAT_GIC_BASE						(0x1D000000)
110 #define PLAT_GICC_BASE						(PLAT_GIC_BASE + 0x20000)
111 #define PLAT_GICD_BASE						(PLAT_GIC_BASE + 0x00000)
112 #define PLAT_GICR_BASE						(PLAT_GIC_BASE + 0x60000)
113 
114 #define PLAT_INTEL_SOCFPGA_GICR_BASE				PLAT_GICR_BASE
115 
116 /*******************************************************************************
117  * SDMMC related pointer function
118  ******************************************************************************/
119 #define SDMMC_READ_BLOCKS	sdmmc_read_blocks
120 #define SDMMC_WRITE_BLOCKS	sdmmc_write_blocks
121 
122 /*******************************************************************************
123  * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
124  * is done and HPS should trigger warm reset via RMR_EL3.
125  ******************************************************************************/
126 #define L2_RESET_DONE_REG			0x10D12218
127 
128 #endif /* PLAT_SOCFPGA_DEF_H */
129