1 /*===================== begin_copyright_notice ================================== 2 3 # Copyright (c) 2023, Intel Corporation 4 5 # Permission is hereby granted, free of charge, to any person obtaining a 6 # copy of this software and associated documentation files (the "Software"), 7 # to deal in the Software without restriction, including without limitation 8 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 # and/or sell copies of the Software, and to permit persons to whom the 10 # Software is furnished to do so, subject to the following conditions: 11 12 # The above copyright notice and this permission notice shall be included 13 # in all copies or substantial portions of the Software. 14 15 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 # OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 25 //! 26 //! \file mhw_vdbox_vdenc_hwcmd_xe2_hpm.h 27 //! \brief Auto-generated constructors for MHW and states. 28 //! \details This file may not be included outside of Xe2_HPM as other components 29 //! should use MHW interface to interact with MHW commands and states. 30 //! 31 32 #ifndef __MHW_VDBOX_VDENC_HWCMD_XE2_HPM_H__ 33 #define __MHW_VDBOX_VDENC_HWCMD_XE2_HPM_H__ 34 35 #pragma once 36 #pragma pack(1) 37 38 #include "mhw_hwcmd.h" 39 #ifdef IGFX_VDENC_INTERFACE_EXT_SUPPORT 40 #include "mhw_vdbox_vdenc_hwcmd_ext.h" 41 #endif 42 43 namespace mhw 44 { 45 namespace vdbox 46 { 47 namespace vdenc 48 { 49 namespace xe_lpm_plus_base 50 { 51 namespace v1 52 { 53 struct _VDENC_CMD1_CMD 54 { 55 union 56 { 57 struct 58 { 59 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 60 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 61 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 62 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 63 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 64 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 65 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 66 }; 67 uint32_t Value; 68 } DW0; 69 union 70 { 71 //!< DWORD 1 72 struct 73 { 74 uint32_t VDENC_CMD1_DW1_BIT0 : __CODEGEN_BITFIELD(0, 7); 75 uint32_t VDENC_CMD1_DW1_BIT8 : __CODEGEN_BITFIELD(8, 15); 76 uint32_t VDENC_CMD1_DW1_BIT16 : __CODEGEN_BITFIELD(16, 23); 77 uint32_t VDENC_CMD1_DW1_BIT24 : __CODEGEN_BITFIELD(24, 31); 78 }; 79 uint32_t Value; 80 } DW1; 81 union 82 { 83 //!< DWORD 2 84 struct 85 { 86 uint32_t VDENC_CMD1_DW2_BIT0 : __CODEGEN_BITFIELD(0, 7); 87 uint32_t VDENC_CMD1_DW2_BIT8 : __CODEGEN_BITFIELD(8, 15); 88 uint32_t VDENC_CMD1_DW2_BIT16 : __CODEGEN_BITFIELD(16, 23); 89 uint32_t VDENC_CMD1_DW2_BIT24 : __CODEGEN_BITFIELD(24, 31); 90 }; 91 uint32_t Value; 92 } DW2; 93 union 94 { 95 //!< DWORD 3 96 struct 97 { 98 uint32_t VDENC_CMD1_DW3_BIT0 : __CODEGEN_BITFIELD(0, 7); 99 uint32_t VDENC_CMD1_DW3_BIT8 : __CODEGEN_BITFIELD(8, 15); 100 uint32_t VDENC_CMD1_DW3_BIT16 : __CODEGEN_BITFIELD(16, 23); 101 uint32_t VDENC_CMD1_DW3_BIT24 : __CODEGEN_BITFIELD(24, 31); 102 }; 103 uint32_t Value; 104 } DW3; 105 union 106 { 107 //!< DWORD 4 108 struct 109 { 110 uint32_t VDENC_CMD1_DW4_BIT0 : __CODEGEN_BITFIELD(0, 7); 111 uint32_t VDENC_CMD1_DW4_BIT8 : __CODEGEN_BITFIELD(8, 15); 112 uint32_t VDENC_CMD1_DW4_BIT16 : __CODEGEN_BITFIELD(16, 23); 113 uint32_t VDENC_CMD1_DW4_BIT24 : __CODEGEN_BITFIELD(24, 31); 114 }; 115 uint32_t Value; 116 } DW4; 117 union 118 { 119 //!< DWORD 5 120 struct 121 { 122 uint32_t VDENC_CMD1_DW5_BIT0 : __CODEGEN_BITFIELD(0, 7); 123 uint32_t VDENC_CMD1_DW5_BIT8 : __CODEGEN_BITFIELD(8, 15); 124 uint32_t VDENC_CMD1_DW5_BIT16 : __CODEGEN_BITFIELD(16, 23); 125 uint32_t VDENC_CMD1_DW5_BIT24 : __CODEGEN_BITFIELD(24, 31); 126 }; 127 uint32_t Value; 128 } DW5; 129 union 130 { 131 //!< DWORD 6 132 struct 133 { 134 uint32_t VDENC_CMD1_DW6_BIT0 : __CODEGEN_BITFIELD(0, 7); 135 uint32_t VDENC_CMD1_DW6_BIT8 : __CODEGEN_BITFIELD(8, 15); 136 uint32_t VDENC_CMD1_DW6_BIT16 : __CODEGEN_BITFIELD(16, 23); 137 uint32_t VDENC_CMD1_DW6_BIT24 : __CODEGEN_BITFIELD(24, 31); 138 }; 139 uint32_t Value; 140 } DW6; 141 union 142 { 143 //!< DWORD 7 144 struct 145 { 146 uint32_t VDENC_CMD1_DW7_BIT0 : __CODEGEN_BITFIELD(0, 7); 147 uint32_t VDENC_CMD1_DW7_BIT8 : __CODEGEN_BITFIELD(8, 15); 148 uint32_t VDENC_CMD1_DW7_BIT16 : __CODEGEN_BITFIELD(16, 23); 149 uint32_t VDENC_CMD1_DW7_BIT24 : __CODEGEN_BITFIELD(24, 31); 150 }; 151 uint32_t Value; 152 } DW7; 153 union 154 { 155 //!< DWORD 8 156 struct 157 { 158 uint32_t VDENC_CMD1_DW8_BIT0 : __CODEGEN_BITFIELD(0, 7); 159 uint32_t VDENC_CMD1_DW8_BIT8 : __CODEGEN_BITFIELD(8, 15); 160 uint32_t VDENC_CMD1_DW8_BIT16 : __CODEGEN_BITFIELD(16, 23); 161 uint32_t VDENC_CMD1_DW8_BIT24 : __CODEGEN_BITFIELD(24, 31); 162 }; 163 uint32_t Value; 164 } DW8; 165 union 166 { 167 //!< DWORD 9 168 struct 169 { 170 uint32_t VDENC_CMD1_DW9_BIT0 : __CODEGEN_BITFIELD(0, 7); 171 uint32_t VDENC_CMD1_DW9_BIT8 : __CODEGEN_BITFIELD(8, 15); 172 uint32_t VDENC_CMD1_DW9_BIT16 : __CODEGEN_BITFIELD(16, 23); 173 uint32_t VDENC_CMD1_DW9_BIT24 : __CODEGEN_BITFIELD(24, 31); 174 }; 175 uint32_t Value; 176 } DW9; 177 union 178 { 179 //!< DWORD 10 180 struct 181 { 182 uint32_t VDENC_CMD1_DW10_BIT0 : __CODEGEN_BITFIELD(0, 7); 183 uint32_t VDENC_CMD1_DW10_BIT8 : __CODEGEN_BITFIELD(8, 15); 184 uint32_t VDENC_CMD1_DW10_BIT16 : __CODEGEN_BITFIELD(16, 23); 185 uint32_t VDENC_CMD1_DW10_BIT24 : __CODEGEN_BITFIELD(24, 31); 186 }; 187 uint32_t Value; 188 } DW10; 189 union 190 { 191 //!< DWORD 11 192 struct 193 { 194 uint32_t VDENC_CMD1_DW11_BIT0 : __CODEGEN_BITFIELD(0, 7); 195 uint32_t VDENC_CMD1_DW11_BIT8 : __CODEGEN_BITFIELD(8, 15); 196 uint32_t VDENC_CMD1_DW11_BIT16 : __CODEGEN_BITFIELD(16, 23); 197 uint32_t VDENC_CMD1_DW11_BIT24 : __CODEGEN_BITFIELD(24, 31); 198 }; 199 uint32_t Value; 200 } DW11; 201 union 202 { 203 //!< DWORD 12 204 struct 205 { 206 uint32_t VDENC_CMD1_DW12_BIT0 : __CODEGEN_BITFIELD(0, 7); 207 uint32_t VDENC_CMD1_DW12_BIT8 : __CODEGEN_BITFIELD(8, 15); 208 uint32_t VDENC_CMD1_DW12_BIT16 : __CODEGEN_BITFIELD(16, 23); 209 uint32_t VDENC_CMD1_DW12_BIT24 : __CODEGEN_BITFIELD(24, 31); 210 }; 211 uint32_t Value; 212 } DW12; 213 union 214 { 215 //!< DWORD 13 216 struct 217 { 218 uint32_t VDENC_CMD1_DW13_BIT0 : __CODEGEN_BITFIELD(0, 7); 219 uint32_t VDENC_CMD1_DW13_BIT8 : __CODEGEN_BITFIELD(8, 15); 220 uint32_t VDENC_CMD1_DW13_BIT16 : __CODEGEN_BITFIELD(16, 23); 221 uint32_t VDENC_CMD1_DW13_BIT24 : __CODEGEN_BITFIELD(24, 31); 222 }; 223 uint32_t Value; 224 } DW13; 225 union 226 { 227 //!< DWORD 14 228 struct 229 { 230 uint32_t VDENC_CMD1_DW14_BIT0 : __CODEGEN_BITFIELD(0, 7); 231 uint32_t VDENC_CMD1_DW14_BIT8 : __CODEGEN_BITFIELD(8, 15); 232 uint32_t VDENC_CMD1_DW14_BIT16 : __CODEGEN_BITFIELD(16, 23); 233 uint32_t VDENC_CMD1_DW14_BIT24 : __CODEGEN_BITFIELD(24, 31); 234 }; 235 uint32_t Value; 236 } DW14; 237 union 238 { 239 //!< DWORD 15 240 struct 241 { 242 uint32_t VDENC_CMD1_DW15_BIT0 : __CODEGEN_BITFIELD(0, 7); 243 uint32_t VDENC_CMD1_DW15_BIT8 : __CODEGEN_BITFIELD(8, 15); 244 uint32_t VDENC_CMD1_DW15_BIT16 : __CODEGEN_BITFIELD(16, 23); 245 uint32_t VDENC_CMD1_DW15_BIT24 : __CODEGEN_BITFIELD(24, 31); 246 }; 247 uint32_t Value; 248 } DW15; 249 union 250 { 251 //!< DWORD 16 252 struct 253 { 254 uint32_t VDENC_CMD1_DW16_BIT0 : __CODEGEN_BITFIELD(0, 7); 255 uint32_t VDENC_CMD1_DW16_BIT8 : __CODEGEN_BITFIELD(8, 15); 256 uint32_t VDENC_CMD1_DW16_BIT16 : __CODEGEN_BITFIELD(16, 23); 257 uint32_t VDENC_CMD1_DW16_BIT24 : __CODEGEN_BITFIELD(24, 31); 258 }; 259 uint32_t Value; 260 } DW16; 261 union 262 { 263 //!< DWORD 17 264 struct 265 { 266 uint32_t VDENC_CMD1_DW17_BIT0 : __CODEGEN_BITFIELD(0, 7); 267 uint32_t VDENC_CMD1_DW17_BIT8 : __CODEGEN_BITFIELD(8, 15); 268 uint32_t VDENC_CMD1_DW17_BIT16 : __CODEGEN_BITFIELD(16, 23); 269 uint32_t VDENC_CMD1_DW17_BIT24 : __CODEGEN_BITFIELD(24, 31); 270 }; 271 uint32_t Value; 272 } DW17; 273 union 274 { 275 //!< DWORD 18 276 struct 277 { 278 uint32_t VDENC_CMD1_DW18_BIT0 : __CODEGEN_BITFIELD(0, 7); 279 uint32_t VDENC_CMD1_DW18_BIT8 : __CODEGEN_BITFIELD(8, 15); 280 uint32_t VDENC_CMD1_DW18_BIT16 : __CODEGEN_BITFIELD(16, 23); 281 uint32_t VDENC_CMD1_DW18_BIT24 : __CODEGEN_BITFIELD(24, 31); 282 }; 283 uint32_t Value; 284 } DW18; 285 union 286 { 287 //!< DWORD 19 288 struct 289 { 290 uint32_t VDENC_CMD1_DW19_BIT0 : __CODEGEN_BITFIELD(0, 7); 291 uint32_t VDENC_CMD1_DW19_BIT8 : __CODEGEN_BITFIELD(8, 15); 292 uint32_t VDENC_CMD1_DW19_BIT16 : __CODEGEN_BITFIELD(16, 23); 293 uint32_t VDENC_CMD1_DW19_BIT24 : __CODEGEN_BITFIELD(24, 31); 294 }; 295 uint32_t Value; 296 } DW19; 297 union 298 { 299 //!< DWORD 20 300 struct 301 { 302 uint32_t VDENC_CMD1_DW20_BIT0 : __CODEGEN_BITFIELD(0, 7); 303 uint32_t VDENC_CMD1_DW20_BIT8 : __CODEGEN_BITFIELD(8, 15); 304 uint32_t VDENC_CMD1_DW20_BIT16 : __CODEGEN_BITFIELD(16, 23); 305 uint32_t VDENC_CMD1_DW20_BIT24 : __CODEGEN_BITFIELD(24, 31); 306 }; 307 uint32_t Value; 308 } DW20; 309 union 310 { 311 //!< DWORD 21 312 struct 313 { 314 uint32_t VDENC_CMD1_DW21_BIT0 : __CODEGEN_BITFIELD(0, 7); 315 uint32_t VDENC_CMD1_DW21_BIT8 : __CODEGEN_BITFIELD(8, 15); 316 uint32_t VDENC_CMD1_DW21_BIT16 : __CODEGEN_BITFIELD(16, 23); 317 uint32_t VDENC_CMD1_DW21_BIT24 : __CODEGEN_BITFIELD(24, 31); 318 }; 319 uint32_t Value; 320 } DW21; 321 union 322 { 323 //!< DWORD 22 324 struct 325 { 326 uint32_t VDENC_CMD1_DW22_BIT0 : __CODEGEN_BITFIELD(0, 15); 327 uint32_t VDENC_CMD1_DW22_BIT16 : __CODEGEN_BITFIELD(16, 24); 328 uint32_t VDENC_CMD1_DW22_BIT25 : __CODEGEN_BITFIELD(25, 31); 329 }; 330 uint32_t Value; 331 } DW22; 332 union 333 { 334 //!< DWORD 23 335 struct 336 { 337 uint32_t VDENC_CMD1_DW23_BIT0 : __CODEGEN_BITFIELD(0, 7); 338 uint32_t VDENC_CMD1_DW23_BIT8 : __CODEGEN_BITFIELD(8, 15); 339 uint32_t VDENC_CMD1_DW23_BIT16 : __CODEGEN_BITFIELD(16, 23); 340 uint32_t VDENC_CMD1_DW23_BIT24 : __CODEGEN_BITFIELD(24, 31); 341 }; 342 uint32_t Value; 343 } DW23; 344 union 345 { 346 //!< DWORD 24 347 struct 348 { 349 uint32_t VDENC_CMD1_DW24_BIT0 : __CODEGEN_BITFIELD(0, 7); 350 uint32_t VDENC_CMD1_DW24_BIT8 : __CODEGEN_BITFIELD(8, 15); 351 uint32_t VDENC_CMD1_DW24_BIT16 : __CODEGEN_BITFIELD(16, 23); 352 uint32_t VDENC_CMD1_DW24_BIT24 : __CODEGEN_BITFIELD(24, 31); 353 }; 354 uint32_t Value; 355 } DW24; 356 union 357 { 358 //!< DWORD 25 359 struct 360 { 361 uint32_t VDENC_CMD1_DW25_BIT0 : __CODEGEN_BITFIELD(0, 7); 362 uint32_t VDENC_CMD1_DW25_BIT8 : __CODEGEN_BITFIELD(8, 15); 363 uint32_t VDENC_CMD1_DW25_BIT16 : __CODEGEN_BITFIELD(16, 23); 364 uint32_t VDENC_CMD1_DW25_BIT24 : __CODEGEN_BITFIELD(24, 31); 365 }; 366 uint32_t Value; 367 } DW25; 368 union 369 { 370 //!< DWORD 26 371 struct 372 { 373 uint32_t VDENC_CMD1_DW26_BIT0 : __CODEGEN_BITFIELD(0, 7); 374 uint32_t VDENC_CMD1_DW26_BIT8 : __CODEGEN_BITFIELD(8, 15); 375 uint32_t VDENC_CMD1_DW26_BIT16 : __CODEGEN_BITFIELD(16, 23); 376 uint32_t VDENC_CMD1_DW26_BIT24 : __CODEGEN_BITFIELD(24, 31); 377 }; 378 uint32_t Value; 379 } DW26; 380 union 381 { 382 //!< DWORD 27 383 struct 384 { 385 uint32_t VDENC_CMD1_DW27_BIT0 : __CODEGEN_BITFIELD(0, 7); 386 uint32_t VDENC_CMD1_DW27_BIT8 : __CODEGEN_BITFIELD(8, 15); 387 uint32_t VDENC_CMD1_DW27_BIT16 : __CODEGEN_BITFIELD(16, 23); 388 uint32_t VDENC_CMD1_DW27_BIT24 : __CODEGEN_BITFIELD(24, 31); 389 }; 390 uint32_t Value; 391 } DW27; 392 union 393 { 394 //!< DWORD 28 395 struct 396 { 397 uint32_t VDENC_CMD1_DW28_BIT0 : __CODEGEN_BITFIELD(0, 7); 398 uint32_t VDENC_CMD1_DW28_BIT8 : __CODEGEN_BITFIELD(8, 15); 399 uint32_t VDENC_CMD1_DW28_BIT16 : __CODEGEN_BITFIELD(16, 23); 400 uint32_t VDENC_CMD1_DW28_BIT24 : __CODEGEN_BITFIELD(24, 31); 401 }; 402 uint32_t Value; 403 } DW28; 404 union 405 { 406 //!< DWORD 29 407 struct 408 { 409 uint32_t VDENC_CMD1_DW29_BIT0 : __CODEGEN_BITFIELD(0, 7); 410 uint32_t VDENC_CMD1_DW29_BIT8 : __CODEGEN_BITFIELD(8, 15); 411 uint32_t VDENC_CMD1_DW29_BIT16 : __CODEGEN_BITFIELD(16, 23); 412 uint32_t VDENC_CMD1_DW29_BIT24 : __CODEGEN_BITFIELD(24, 31); 413 }; 414 uint32_t Value; 415 } DW29; 416 union 417 { 418 //!< DWORD 30 419 struct 420 { 421 uint32_t VDENC_CMD1_DW30_BIT0 : __CODEGEN_BITFIELD(0, 7); 422 uint32_t VDENC_CMD1_DW30_BIT8 : __CODEGEN_BITFIELD(8, 15); 423 uint32_t VDENC_CMD1_DW30_BIT16 : __CODEGEN_BITFIELD(16, 23); 424 uint32_t VDENC_CMD1_DW30_BIT24 : __CODEGEN_BITFIELD(24, 31); 425 }; 426 uint32_t Value; 427 } DW30; 428 union 429 { 430 struct 431 { 432 uint32_t VDENC_CMD1_DW31_BIT0 : __CODEGEN_BITFIELD(0, 7); 433 uint32_t VDENC_CMD1_DW31_BIT8 : __CODEGEN_BITFIELD(8, 15); 434 uint32_t VDENC_CMD1_DW31_BIT16 : __CODEGEN_BITFIELD(16, 23); 435 uint32_t VDENC_CMD1_DW31_BIT24 : __CODEGEN_BITFIELD(24, 31); 436 }; 437 uint32_t Value; 438 } DW31; 439 union 440 { 441 struct 442 { 443 uint32_t VDENC_CMD1_DW32_BIT0 : __CODEGEN_BITFIELD(0, 7); 444 uint32_t VDENC_CMD1_DW32_BIT8 : __CODEGEN_BITFIELD(8, 15); 445 uint32_t VDENC_CMD1_DW32_BIT16 : __CODEGEN_BITFIELD(16, 23); 446 uint32_t VDENC_CMD1_DW32_BIT24 : __CODEGEN_BITFIELD(24, 31); 447 }; 448 uint32_t Value; 449 } DW32; 450 union 451 { 452 struct 453 { 454 uint32_t VDENC_CMD1_DW33_BIT0 : __CODEGEN_BITFIELD(0, 7); 455 uint32_t VDENC_CMD1_DW33_BIT8 : __CODEGEN_BITFIELD(8, 15); 456 uint32_t VDENC_CMD1_DW33_BIT16 : __CODEGEN_BITFIELD(16, 23); 457 uint32_t VDENC_CMD1_DW33_BIT24 : __CODEGEN_BITFIELD(24, 31); 458 }; 459 uint32_t Value; 460 } DW33; 461 union 462 { 463 struct 464 { 465 uint32_t VDENC_CMD1_DW34_BIT0 : __CODEGEN_BITFIELD(0, 7); 466 uint32_t VDENC_CMD1_DW34_BIT8 : __CODEGEN_BITFIELD(8, 15); 467 uint32_t VDENC_CMD1_DW34_BIT16 : __CODEGEN_BITFIELD(16, 23); 468 uint32_t VDENC_CMD1_DW34_BIT24 : __CODEGEN_BITFIELD(24, 31); 469 }; 470 uint32_t Value; 471 } DW34; 472 union 473 { 474 struct 475 { 476 uint32_t VDENC_CMD1_DW35_BIT0 : __CODEGEN_BITFIELD(0, 7); 477 uint32_t VDENC_CMD1_DW35_BIT8 : __CODEGEN_BITFIELD(8, 15); 478 uint32_t VDENC_CMD1_DW35_BIT16 : __CODEGEN_BITFIELD(16, 23); 479 uint32_t VDENC_CMD1_DW35_BIT24 : __CODEGEN_BITFIELD(24, 31); 480 }; 481 uint32_t Value; 482 } DW35; 483 union 484 { 485 struct 486 { 487 uint32_t VDENC_CMD1_DW36_BIT0 : __CODEGEN_BITFIELD(0, 7); 488 uint32_t VDENC_CMD1_DW36_BIT8 : __CODEGEN_BITFIELD(8, 15); 489 uint32_t VDENC_CMD1_DW36_BIT16 : __CODEGEN_BITFIELD(16, 23); 490 uint32_t VDENC_CMD1_DW36_BIT24 : __CODEGEN_BITFIELD(24, 31); 491 }; 492 uint32_t Value; 493 } DW36; 494 union 495 { 496 struct 497 { 498 uint32_t VDENC_CMD1_DW37_BIT0 : __CODEGEN_BITFIELD(0, 7); 499 uint32_t VDENC_CMD1_DW37_BIT8 : __CODEGEN_BITFIELD(8, 15); 500 uint32_t VDENC_CMD1_DW37_BIT16 : __CODEGEN_BITFIELD(16, 23); 501 uint32_t VDENC_CMD1_DW37_BIT24 : __CODEGEN_BITFIELD(24, 31); 502 }; 503 uint32_t Value; 504 } DW37; 505 union 506 { 507 struct 508 { 509 uint32_t VDENC_CMD1_DW38_BIT0 : __CODEGEN_BITFIELD(0, 7); 510 uint32_t VDENC_CMD1_DW38_BIT8 : __CODEGEN_BITFIELD(8, 15); 511 uint32_t VDENC_CMD1_DW38_BIT16 : __CODEGEN_BITFIELD(16, 23); 512 uint32_t VDENC_CMD1_DW38_BIT24 : __CODEGEN_BITFIELD(24, 31); 513 }; 514 uint32_t Value; 515 } DW38; 516 //! \name Local enumerations 517 518 enum SUBOPB 519 { 520 SUBOPB_VDENCCMD1CMD = 10, //!< No additional details 521 }; 522 523 enum SUBOPA 524 { 525 SUBOPA_UNNAMED0 = 0, //!< No additional details 526 }; 527 528 enum OPCODE 529 { 530 OPCODE_VDENCPIPE = 1, //!< No additional details 531 }; 532 533 enum PIPELINE 534 { 535 PIPELINE_MFXCOMMON = 2, //!< No additional details 536 }; 537 538 enum COMMAND_TYPE 539 { 540 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 541 }; 542 543 //! \name Initializations 544 545 //! \brief Explicit member initialization function _VDENC_CMD1_CMD_VDENC_CMD1_CMD546 _VDENC_CMD1_CMD() 547 { 548 MOS_ZeroMemory(this, sizeof(*this)); 549 550 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 551 DW0.Subopb = SUBOPB_VDENCCMD1CMD; 552 DW0.Subopa = SUBOPA_UNNAMED0; 553 DW0.Opcode = OPCODE_VDENCPIPE; 554 DW0.Pipeline = PIPELINE_MFXCOMMON; 555 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 556 } 557 558 static const size_t dwSize = 39; 559 static const size_t byteSize = 156; 560 }; 561 562 struct _VDENC_CMD3_CMD 563 { 564 union 565 { 566 struct 567 { 568 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 569 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 570 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 571 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 572 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 573 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 574 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 575 }; 576 uint32_t Value; 577 } DW0; 578 union 579 { 580 struct 581 { 582 uint32_t VDENC_CMD3_DW1_BIT0 : __CODEGEN_BITFIELD(0, 7); 583 uint32_t VDENC_CMD3_DW1_BIT8 : __CODEGEN_BITFIELD(8, 15); 584 uint32_t VDENC_CMD3_DW1_BIT16 : __CODEGEN_BITFIELD(16, 23); 585 uint32_t VDENC_CMD3_DW1_BIT24 : __CODEGEN_BITFIELD(24, 31); 586 587 uint32_t VDENC_CMD3_DW2_BIT0 : __CODEGEN_BITFIELD(0, 7); 588 uint32_t VDENC_CMD3_DW2_BIT8 : __CODEGEN_BITFIELD(8, 15); 589 uint32_t VDENC_CMD3_DW2_BIT16 : __CODEGEN_BITFIELD(16, 23); 590 uint32_t VDENC_CMD3_DW2_BIT24 : __CODEGEN_BITFIELD(24, 31); 591 }; 592 uint32_t Value[2]; 593 } DW1_2; 594 uint8_t VDENC_CMD3_DW3_5[12]; 595 uint8_t VDENC_CMD3_DW6_8[12]; 596 union 597 { 598 struct 599 { 600 uint32_t VDENC_CMD3_DW9; 601 }; 602 uint32_t Value; 603 } DW9; 604 union 605 { 606 struct 607 { 608 uint32_t VDENC_CMD3_DW10_BIT0 : __CODEGEN_BITFIELD(0, 15); 609 uint32_t VDENC_CMD3_DW10_BIT16 : __CODEGEN_BITFIELD(16, 23); 610 uint32_t VDENC_CMD3_DW10_BIT24 : __CODEGEN_BITFIELD(24, 31); 611 }; 612 uint32_t Value; 613 } DW10; 614 union 615 { 616 struct 617 { 618 uint32_t VDENC_CMD3_DW11; 619 }; 620 uint32_t Value; 621 } DW11; 622 union 623 { 624 struct 625 { 626 uint32_t VDENC_CMD3_DW12_BIT0 : __CODEGEN_BITFIELD(0, 7); 627 uint32_t VDENC_CMD3_DW12_BIT8 : __CODEGEN_BITFIELD(8, 15); 628 uint32_t VDENC_CMD3_DW12_BIT16 : __CODEGEN_BITFIELD(16, 23); 629 uint32_t VDENC_CMD3_DW12_BIT24 : __CODEGEN_BITFIELD(24, 31); 630 }; 631 uint32_t Value; 632 } DW12; 633 union 634 { 635 struct 636 { 637 uint32_t VDENC_CMD3_DW13_BIT0 : __CODEGEN_BITFIELD(0, 7); 638 uint32_t VDENC_CMD3_DW13_BIT8 : __CODEGEN_BITFIELD(8, 15); 639 uint32_t VDENC_CMD3_DW13_BIT16 : __CODEGEN_BITFIELD(16, 23); 640 uint32_t VDENC_CMD3_DW13_BIT24 : __CODEGEN_BITFIELD(24, 31); 641 }; 642 uint32_t Value; 643 } DW13; 644 union 645 { 646 struct 647 { 648 uint32_t VDENC_CMD3_DW14_BIT0 : __CODEGEN_BITFIELD(0, 7); 649 uint32_t VDENC_CMD3_DW14_BIT8 : __CODEGEN_BITFIELD(8, 15); 650 uint32_t VDENC_CMD3_DW14_BIT16 : __CODEGEN_BITFIELD(16, 23); 651 uint32_t VDENC_CMD3_DW14_BIT24 : __CODEGEN_BITFIELD(24, 31); 652 }; 653 uint32_t Value; 654 } DW14; 655 union 656 { 657 struct 658 { 659 uint32_t VDENC_CMD3_DW15_BIT0 : __CODEGEN_BITFIELD(0, 7); 660 uint32_t VDENC_CMD3_DW15_BIT8 : __CODEGEN_BITFIELD(8, 15); 661 uint32_t VDENC_CMD3_DW15_BIT16 : __CODEGEN_BITFIELD(16, 23); 662 uint32_t VDENC_CMD3_DW15_BIT24 : __CODEGEN_BITFIELD(24, 31); 663 }; 664 uint32_t Value; 665 } DW15; 666 union 667 { 668 struct 669 { 670 uint32_t VDENC_CMD3_DW16_BIT0 : __CODEGEN_BITFIELD(0, 15); 671 uint32_t VDENC_CMD3_DW16_BIT16 : __CODEGEN_BITFIELD(16, 23); 672 uint32_t VDENC_CMD3_DW16_BIT24 : __CODEGEN_BITFIELD(24, 31); 673 }; 674 uint32_t Value; 675 } DW16; 676 union 677 { 678 struct 679 { 680 uint32_t VDENC_CMD3_DW17_BIT0 : __CODEGEN_BITFIELD(0, 7); 681 uint32_t VDENC_CMD3_DW17_BIT8 : __CODEGEN_BITFIELD(8, 15); 682 uint32_t VDENC_CMD3_DW17_BIT16 : __CODEGEN_BITFIELD(16, 23); 683 uint32_t VDENC_CMD3_DW17_BIT24 : __CODEGEN_BITFIELD(24, 31); 684 }; 685 uint32_t Value; 686 } DW17; 687 union 688 { 689 struct 690 { 691 uint32_t VDENC_CMD3_DW18; 692 }; 693 uint32_t Value; 694 } DW18; 695 union 696 { 697 struct 698 { 699 uint32_t VDENC_CMD3_DW19_BIT0 : __CODEGEN_BITFIELD(0, 7); 700 uint32_t VDENC_CMD3_DW19_BIT8 : __CODEGEN_BITFIELD(8, 15); 701 uint32_t VDENC_CMD3_DW19_BIT16 : __CODEGEN_BITFIELD(16, 23); 702 uint32_t VDENC_CMD3_DW19_BIT24 : __CODEGEN_BITFIELD(24, 31); 703 }; 704 uint32_t Value; 705 } DW19; 706 union 707 { 708 struct 709 { 710 uint32_t VDENC_CMD3_DW20_BIT0 : __CODEGEN_BITFIELD(0, 7); 711 uint32_t VDENC_CMD3_DW20_BIT8 : __CODEGEN_BITFIELD(8, 15); 712 uint32_t VDENC_CMD3_DW20_BIT16 : __CODEGEN_BITFIELD(16, 31); 713 }; 714 uint32_t Value; 715 } DW20; 716 union 717 { 718 struct 719 { 720 uint32_t VDENC_CMD3_DW21_BIT0 : __CODEGEN_BITFIELD(0, 7); 721 uint32_t VDENC_CMD3_DW21_BIT8 : __CODEGEN_BITFIELD(8, 15); 722 uint32_t VDENC_CMD3_DW21_BIT16 : __CODEGEN_BITFIELD(16, 31); 723 }; 724 uint32_t Value; 725 } DW21; 726 union 727 { 728 struct 729 { 730 uint32_t VDENC_CMD3_DW22_BIT0 : __CODEGEN_BITFIELD(0, 15); 731 uint32_t VDENC_CMD3_DW22_BIT16 : __CODEGEN_BITFIELD(16, 24); 732 uint32_t VDENC_CMD3_DW22_BIT25 : __CODEGEN_BITFIELD(25, 31); 733 }; 734 uint32_t Value; 735 } DW22; 736 737 //! \name Initializations 738 739 //! \brief Explicit member initialization function _VDENC_CMD3_CMD_VDENC_CMD3_CMD740 _VDENC_CMD3_CMD() 741 { 742 MOS_ZeroMemory(this, sizeof(*this)); 743 744 DW0.Value = 0x708a0015; 745 } 746 747 static const size_t dwSize = 23; 748 static const size_t byteSize = 92; 749 }; 750 751 #ifdef IGFX_VDENC_INTERFACE_EXT_SUPPORT 752 #include "mhw_vdbox_vdenc_hwcmd_xe2_hpm_ext.h" 753 #else 754 struct _VDENC_CMD2_CMD 755 { 756 union 757 { 758 //!< DWORD 0 759 struct 760 { 761 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWord Length 762 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 763 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 764 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 765 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 766 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 767 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 768 }; 769 uint32_t Value; 770 } DW0; 771 union 772 { 773 //!< DWORD 1 774 struct 775 { 776 uint32_t FrameWidthInPixelsMinusOne : __CODEGEN_BITFIELD(0, 15); //!< FrameWidthInPixelsMinusOne 777 uint32_t FrameHeightInPixelsMinusOne : __CODEGEN_BITFIELD(16, 31); //!< FrameHeightInPixelsMinusOne 778 }; 779 uint32_t Value; 780 } DW1; 781 union 782 { 783 //!< DWORD 2 784 struct 785 { 786 uint32_t : __CODEGEN_BITFIELD(0, 19); 787 uint32_t PictureType : __CODEGEN_BITFIELD(20, 21); //!< Picture Type 788 uint32_t TemporalMvpEnableFlag : __CODEGEN_BITFIELD(22, 22); //!< TemporalMvpEnableFlag 789 uint32_t Collocatedfroml0Flag : __CODEGEN_BITFIELD(23, 23); //!< CollocatedFromL0Flag 790 uint32_t LongTermReferenceFlagsL0 : __CODEGEN_BITFIELD(24, 26); //!< LongTermReferenceFlags_L0 791 uint32_t LongTermReferenceFlagsL1 : __CODEGEN_BITFIELD(27, 27); //!< LongTermReferenceFlags_L1 792 uint32_t : __CODEGEN_BITFIELD(28, 29); 793 uint32_t TransformSkip : __CODEGEN_BITFIELD(30, 30); //!< TransformSkip 794 uint32_t ConstrainedIntraPredFlag : __CODEGEN_BITFIELD(31, 31); //!< ConstrainedIntraPredFlag 795 }; 796 uint32_t Value; 797 } DW2; 798 union 799 { 800 //!< DWORD 3 801 struct 802 { 803 uint32_t FwdPocNumberForRefid0InL0 : __CODEGEN_BITFIELD(0, 7); //!< FWD_POC_NUMBER_FOR_REFID_0_IN_L0 804 uint32_t BwdPocNumberForRefid0InL1 : __CODEGEN_BITFIELD(8, 15); //!< BWD_POC_NUMBER_FOR_REFID_0_IN_L1 805 uint32_t PocNumberForRefid1InL0 : __CODEGEN_BITFIELD(16, 23); //!< POC_NUMBER_FOR_REFID_1_IN_L0 806 uint32_t PocNumberForRefid1InL1 : __CODEGEN_BITFIELD(24, 31); //!< POC_NUMBER_FOR_REFID_1_IN_L1 807 }; 808 uint32_t Value; 809 } DW3; 810 union 811 { 812 //!< DWORD 4 813 struct 814 { 815 uint32_t PocNumberForRefid2InL0 : __CODEGEN_BITFIELD(0, 7); //!< FWD_POC_NUMBER_FOR_REFID_2_IN_L0 816 uint32_t PocNumberForRefid2InL1 : __CODEGEN_BITFIELD(8, 15); //!< BWD_POC_NUMBER_FOR_REFID_2_IN_L1 817 uint32_t PocNumberForRefid3InL0 : __CODEGEN_BITFIELD(16, 23); //!< POC_NUMBER_FOR_REFID_3_IN_L0 818 uint32_t PocNumberForRefid3InL1 : __CODEGEN_BITFIELD(24, 31); //!< POC_NUMBER_FOR_REFID_3_IN_L1 819 }; 820 uint32_t Value; 821 } DW4; 822 union 823 { 824 //!< DWORD 5 825 struct 826 { 827 uint32_t : __CODEGEN_BITFIELD(0, 7); 828 uint32_t StreaminRoiEnable : __CODEGEN_BITFIELD(8, 8); //!< StreamIn ROI Enable 829 uint32_t : __CODEGEN_BITFIELD(9, 9); 830 uint32_t SubPelMode : __CODEGEN_BITFIELD(10, 11); //!< SubPelMode 831 uint32_t : __CODEGEN_BITFIELD(12, 23); 832 uint32_t NumRefIdxL0Minus1 : __CODEGEN_BITFIELD(24, 27); //!< NumRefIdxL0_minus1 833 uint32_t NumRefIdxL1Minus1 : __CODEGEN_BITFIELD(28, 31); //!< NumRefIdxL1_minus1 834 }; 835 uint32_t Value; 836 } DW5; 837 union 838 { 839 //!< DWORD 6 840 struct 841 { 842 uint32_t : __CODEGEN_BITFIELD(0, 31); 843 }; 844 uint32_t Value; 845 } DW6; 846 union 847 { 848 //!< DWORD 7 849 struct 850 { 851 uint32_t : __CODEGEN_BITFIELD(0, 3); 852 uint32_t SegmentationEnable : __CODEGEN_BITFIELD(4, 4); //!< Segmentation Enable 853 uint32_t SegmentationMapTemporalPredictionEnable : __CODEGEN_BITFIELD(5, 5); //!< Segmentation map temporal prediction enable 854 uint32_t : __CODEGEN_BITFIELD(6, 6); 855 uint32_t TilingEnable : __CODEGEN_BITFIELD(7, 7); //!< Tiling enable 856 uint32_t : __CODEGEN_BITFIELD(8, 8); 857 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD(9, 9); //!< VDENC Stream IN 858 uint32_t : __CODEGEN_BITFIELD(10, 15); 859 uint32_t PakOnlyMultiPassEnable : __CODEGEN_BITFIELD(16, 16); //!< PAK-Only Multi-Pass Enable 860 uint32_t : __CODEGEN_BITFIELD(17, 31); 861 }; 862 uint32_t Value; 863 } DW7; 864 union 865 { 866 //!< DWORD 8 867 struct 868 { 869 uint32_t : __CODEGEN_BITFIELD(0, 31); 870 }; 871 uint32_t Value; 872 } DW8; 873 union 874 { 875 //!< DWORD 9 876 struct 877 { 878 uint32_t : __CODEGEN_BITFIELD(0, 31); 879 }; 880 uint32_t Value; 881 } DW9; 882 union 883 { 884 //!< DWORD 10 885 struct 886 { 887 uint32_t : __CODEGEN_BITFIELD(0, 31); 888 }; 889 uint32_t Value; 890 } DW10; 891 union 892 { 893 //!< DWORD 11 894 struct 895 { 896 uint32_t FwdRef0RefPic : __CODEGEN_BITFIELD(0, 2); 897 uint32_t : __CODEGEN_BITFIELD(3, 7); 898 uint32_t FwdRef1RefPic : __CODEGEN_BITFIELD(8, 10); 899 uint32_t : __CODEGEN_BITFIELD(11, 15); 900 uint32_t FwdRef2RefPic : __CODEGEN_BITFIELD(16, 18); 901 uint32_t : __CODEGEN_BITFIELD(19, 23); 902 uint32_t BwdRef0RefPic : __CODEGEN_BITFIELD(24, 26); 903 uint32_t : __CODEGEN_BITFIELD(27, 31); 904 }; 905 uint32_t Value; 906 } DW11; 907 union 908 { 909 //!< DWORD 12 910 struct 911 { 912 uint32_t : __CODEGEN_BITFIELD(0, 31); 913 }; 914 uint32_t Value; 915 } DW12; 916 union 917 { 918 //!< DWORD 13 919 struct 920 { 921 uint32_t : __CODEGEN_BITFIELD(0, 31); 922 }; 923 uint32_t Value; 924 } DW13; 925 union 926 { 927 //!< DWORD 14 928 struct 929 { 930 uint32_t : __CODEGEN_BITFIELD(0, 31); 931 }; 932 uint32_t Value; 933 } DW14; 934 union 935 { 936 //!< DWORD 15 937 struct 938 { 939 uint32_t : __CODEGEN_BITFIELD(0, 31); 940 }; 941 uint32_t Value; 942 } DW15; 943 union 944 { 945 //!< DWORD 16 946 struct 947 { 948 uint32_t MinQp : __CODEGEN_BITFIELD(0, 7); //!< MINQP 949 uint32_t MaxQp : __CODEGEN_BITFIELD(8, 15); //!< MAXQP 950 uint32_t : __CODEGEN_BITFIELD(16, 31); 951 }; 952 uint32_t Value; 953 } DW16; 954 union 955 { 956 //!< DWORD 17 957 struct 958 { 959 uint32_t : __CODEGEN_BITFIELD(0, 19); 960 uint32_t TemporalMVEnableForIntegerSearch : __CODEGEN_BITFIELD(20, 20); //!< Setting this bit enables Temporal MV Enable for Integer search 961 uint32_t : __CODEGEN_BITFIELD(21, 31); 962 }; 963 uint32_t Value; 964 } DW17; 965 union 966 { 967 //!< DWORD 18 968 struct 969 { 970 uint32_t : __CODEGEN_BITFIELD(0, 31); 971 }; 972 uint32_t Value; 973 } DW18; 974 union 975 { 976 //!< DWORD 19 977 struct 978 { 979 uint32_t : __CODEGEN_BITFIELD(0, 31); 980 }; 981 uint32_t Value; 982 } DW19; 983 union 984 { 985 //!< DWORD 20 986 struct 987 { 988 uint32_t : __CODEGEN_BITFIELD(0, 31); 989 }; 990 uint32_t Value; 991 } DW20; 992 union 993 { 994 //!< DWORD 21 995 struct 996 { 997 uint32_t IntraRefreshPos : __CODEGEN_BITFIELD(0, 8); //!< IntraRefreshPos 998 uint32_t : __CODEGEN_BITFIELD(9, 15); 999 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD(16, 23); //!< IntraRefreshMBSizeMinusOne 1000 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(24, 24); //!< IntraRefreshMode 1001 uint32_t IntraRefreshEnable : __CODEGEN_BITFIELD(25, 25); //!< IntraRefreshEnable (Rolling I Enable) 1002 uint32_t : __CODEGEN_BITFIELD(26, 27); 1003 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(28, 31); //!< QP_ADJUSTMENT_FOR_ROLLING_I 1004 }; 1005 uint32_t Value; 1006 } DW21; 1007 union 1008 { 1009 //!< DWORD 22 1010 struct 1011 { 1012 uint32_t : __CODEGEN_BITFIELD(0, 31); 1013 }; 1014 uint32_t Value; 1015 } DW22; 1016 union 1017 { 1018 //!< DWORD 23 1019 struct 1020 { 1021 uint32_t : __CODEGEN_BITFIELD(0, 31); 1022 }; 1023 uint32_t Value; 1024 } DW23; 1025 union 1026 { 1027 //!< DWORD 24 1028 struct 1029 { 1030 uint32_t QpForSeg0 : __CODEGEN_BITFIELD(0, 7); //!< QP for Seg0 1031 uint32_t QpForSeg1 : __CODEGEN_BITFIELD(8, 15); //!< QP for Seg1 1032 uint32_t QpForSeg2 : __CODEGEN_BITFIELD(16, 23); //!< QP for Seg2 1033 uint32_t QpForSeg3 : __CODEGEN_BITFIELD(24, 31); //!< QP for Seg3 1034 }; 1035 uint32_t Value; 1036 } DW24; 1037 union 1038 { 1039 //!< DWORD 25 1040 struct 1041 { 1042 uint32_t QpForSeg4 : __CODEGEN_BITFIELD(0, 7); //!< QP for Seg4 1043 uint32_t QpForSeg5 : __CODEGEN_BITFIELD(8, 15); //!< QP for Seg5 1044 uint32_t QpForSeg6 : __CODEGEN_BITFIELD(16, 23); //!< QP for Seg6 1045 uint32_t QpForSeg7 : __CODEGEN_BITFIELD(24, 31); //!< QP for Seg7 1046 }; 1047 uint32_t Value; 1048 } DW25; 1049 union 1050 { 1051 //!< DWORD 26 1052 struct 1053 { 1054 uint32_t : __CODEGEN_BITFIELD(0, 24); 1055 uint32_t Vp9DynamicSliceEnable : __CODEGEN_BITFIELD(25, 25); //!< VP9 Dynamic slice enable 1056 uint32_t : __CODEGEN_BITFIELD(26, 31); 1057 }; 1058 uint32_t Value; 1059 } DW26; 1060 union 1061 { 1062 //!< DWORD 27 1063 struct 1064 { 1065 uint32_t QpPrimeYDc : __CODEGEN_BITFIELD(0, 7); //!< QPPRIMEY_DC 1066 uint32_t QpPrimeYAc : __CODEGEN_BITFIELD(8, 15); //!< QPPRIMEY_AC 1067 uint32_t : __CODEGEN_BITFIELD(16, 31); 1068 }; 1069 uint32_t Value; 1070 } DW27; 1071 union 1072 { 1073 //!< DWORD 28 1074 struct 1075 { 1076 uint32_t : __CODEGEN_BITFIELD(0, 31); 1077 }; 1078 uint32_t Value; 1079 } DW28; 1080 union 1081 { 1082 //!< DWORD 29 1083 struct 1084 { 1085 uint32_t : __CODEGEN_BITFIELD(0, 31); 1086 }; 1087 uint32_t Value; 1088 } DW29; 1089 union 1090 { 1091 //!< DWORD 30 1092 struct 1093 { 1094 uint32_t : __CODEGEN_BITFIELD(0, 31); 1095 }; 1096 uint32_t Value; 1097 } DW30; 1098 union 1099 { 1100 //!< DWORD 31 1101 struct 1102 { 1103 uint32_t : __CODEGEN_BITFIELD(0, 31); 1104 }; 1105 uint32_t Value; 1106 } DW31; 1107 union 1108 { 1109 //!< DWORD 32 1110 struct 1111 { 1112 uint32_t : __CODEGEN_BITFIELD(0, 31); 1113 }; 1114 uint32_t Value; 1115 } DW32; 1116 union 1117 { 1118 //!< DWORD 33 1119 struct 1120 { 1121 uint32_t : __CODEGEN_BITFIELD(0, 31); 1122 }; 1123 uint32_t Value; 1124 } DW33; 1125 union 1126 { 1127 //!< DWORD 34 1128 struct 1129 { 1130 uint32_t : __CODEGEN_BITFIELD(0, 31); 1131 }; 1132 uint32_t Value; 1133 } DW34; 1134 union 1135 { 1136 //!< DWORD 35 1137 struct 1138 { 1139 uint32_t : __CODEGEN_BITFIELD(0, 31); 1140 }; 1141 uint32_t Value; 1142 } DW35; 1143 union 1144 { 1145 //!< DWORD 36 1146 struct 1147 { 1148 uint32_t IntraRefreshBoundaryRef0 : __CODEGEN_BITFIELD(0, 8); //!< IntraRefreshBoundary Ref0 1149 uint32_t : __CODEGEN_BITFIELD(9, 9); 1150 uint32_t IntraRefreshBoundaryRef1 : __CODEGEN_BITFIELD(10, 18); //!< IntraRefreshBoundary Ref1 1151 uint32_t : __CODEGEN_BITFIELD(19, 19); 1152 uint32_t IntraRefreshBoundaryRef2 : __CODEGEN_BITFIELD(20, 28); //!< IntraRefreshBoundary Ref2 1153 uint32_t : __CODEGEN_BITFIELD(29, 31); 1154 }; 1155 uint32_t Value; 1156 } DW36; 1157 union 1158 { 1159 struct 1160 { 1161 uint32_t : __CODEGEN_BITFIELD(0, 31); 1162 }; 1163 uint32_t Value; 1164 } DW37; 1165 union 1166 { 1167 //!< DWORD 38 1168 struct 1169 { 1170 uint32_t : __CODEGEN_BITFIELD(0, 31); 1171 }; 1172 uint32_t Value; 1173 } DW38; 1174 union 1175 { 1176 //!< DWORD 39 1177 struct 1178 { 1179 uint32_t : __CODEGEN_BITFIELD(0, 31); 1180 }; 1181 uint32_t Value; 1182 } DW39; 1183 union 1184 { 1185 //!< DWORD 40 1186 struct 1187 { 1188 uint32_t : __CODEGEN_BITFIELD(0, 31); 1189 }; 1190 uint32_t Value; 1191 } DW40; 1192 union 1193 { 1194 //!< DWORD 41 1195 struct 1196 { 1197 uint32_t : __CODEGEN_BITFIELD(0, 31); 1198 }; 1199 uint32_t Value; 1200 } DW41; 1201 union 1202 { 1203 //!< DWORD 42 1204 struct 1205 { 1206 uint32_t : __CODEGEN_BITFIELD(0, 31); 1207 }; 1208 uint32_t Value; 1209 } DW42; 1210 union 1211 { 1212 //!< DWORD 43 1213 struct 1214 { 1215 uint32_t : __CODEGEN_BITFIELD(0, 31); 1216 }; 1217 uint32_t Value; 1218 } DW43; 1219 union 1220 { 1221 //!< DWORD 44 1222 struct 1223 { 1224 uint32_t : __CODEGEN_BITFIELD(0, 31); 1225 }; 1226 uint32_t Value; 1227 } DW44; 1228 union 1229 { 1230 //!< DWORD 45 1231 struct 1232 { 1233 uint32_t : __CODEGEN_BITFIELD(0, 31); 1234 }; 1235 uint32_t Value; 1236 } DW45; 1237 union 1238 { 1239 //!< DWORD 46 1240 struct 1241 { 1242 uint32_t : __CODEGEN_BITFIELD(0, 31); 1243 }; 1244 uint32_t Value; 1245 } DW46; 1246 union 1247 { 1248 //!< DWORD 47 1249 struct 1250 { 1251 uint32_t : __CODEGEN_BITFIELD(0, 31); 1252 }; 1253 uint32_t Value; 1254 } DW47; 1255 union 1256 { 1257 //!< DWORD 48 1258 struct 1259 { 1260 uint32_t : __CODEGEN_BITFIELD(0, 31); 1261 }; 1262 uint32_t Value; 1263 } DW48; 1264 union 1265 { 1266 //!< DWORD 49 1267 struct 1268 { 1269 uint32_t : __CODEGEN_BITFIELD(0, 31); 1270 }; 1271 uint32_t Value; 1272 } DW49; 1273 union 1274 { 1275 //!< DWORD 50 1276 struct 1277 { 1278 uint32_t : __CODEGEN_BITFIELD(0, 31); 1279 }; 1280 uint32_t Value; 1281 } DW50; 1282 union 1283 { 1284 //!< DWORD 51 1285 struct 1286 { 1287 uint32_t : __CODEGEN_BITFIELD(0, 31); 1288 }; 1289 uint32_t Value; 1290 } DW51; 1291 union 1292 { 1293 //!< DWORD 52 1294 struct 1295 { 1296 uint32_t : __CODEGEN_BITFIELD(0, 31); 1297 }; 1298 uint32_t Value; 1299 } DW52; 1300 union 1301 { 1302 //!< DWORD 53 1303 struct 1304 { 1305 uint32_t : __CODEGEN_BITFIELD(0, 31); 1306 }; 1307 uint32_t Value; 1308 } DW53; 1309 union 1310 { 1311 //!< DWORD 54 1312 struct 1313 { 1314 uint32_t : __CODEGEN_BITFIELD(0, 31); 1315 }; 1316 uint32_t Value; 1317 } DW54; 1318 union 1319 { 1320 //!< DWORD 55 1321 struct 1322 { 1323 uint32_t : __CODEGEN_BITFIELD(0, 31); 1324 }; 1325 uint32_t Value; 1326 } DW55; 1327 union 1328 { 1329 //!< DWORD 56 1330 struct 1331 { 1332 uint32_t : __CODEGEN_BITFIELD(0, 31); 1333 }; 1334 uint32_t Value; 1335 } DW56; 1336 union 1337 { 1338 //!< DWORD 57 1339 struct 1340 { 1341 uint32_t : __CODEGEN_BITFIELD(0, 31); 1342 }; 1343 uint32_t Value; 1344 } DW57; 1345 union 1346 { 1347 //!< DWORD 58 1348 struct 1349 { 1350 uint32_t : __CODEGEN_BITFIELD(0, 31); 1351 }; 1352 uint32_t Value; 1353 } DW58; 1354 union 1355 { 1356 //!< DWORD 59 1357 struct 1358 { 1359 uint32_t : __CODEGEN_BITFIELD(0, 31); 1360 }; 1361 uint32_t Value; 1362 } DW59; 1363 union 1364 { 1365 //!< DWORD 60 1366 struct 1367 { 1368 uint32_t : __CODEGEN_BITFIELD(0, 31); 1369 }; 1370 uint32_t Value; 1371 } DW60; 1372 union 1373 { 1374 //!< DWORD 61 1375 struct 1376 { 1377 uint32_t Av1L0RefID0 : __CODEGEN_BITFIELD(0, 3); 1378 uint32_t Av1L1RefID0 : __CODEGEN_BITFIELD(4, 7); 1379 uint32_t Av1L0RefID1 : __CODEGEN_BITFIELD(8, 11); 1380 uint32_t Av1L1RefID1 : __CODEGEN_BITFIELD(12, 15); 1381 uint32_t Av1L0RefID2 : __CODEGEN_BITFIELD(16, 19); 1382 uint32_t Av1L1RefID2 : __CODEGEN_BITFIELD(20, 23); 1383 uint32_t Av1L0RefID3 : __CODEGEN_BITFIELD(24, 27); 1384 uint32_t Av1L1RefID3 : __CODEGEN_BITFIELD(28, 31); 1385 }; 1386 uint32_t Value; 1387 } DW61; 1388 //! \name Local enumerations 1389 1390 enum SUBOPB 1391 { 1392 SUBOPB_VDENCCMD2CMD = 9, //!< No additional details 1393 }; 1394 1395 enum SUBOPA 1396 { 1397 SUBOPA_UNNAMED0 = 0, //!< No additional details 1398 }; 1399 1400 enum OPCODE 1401 { 1402 OPCODE_VDENCPIPE = 1, //!< No additional details 1403 }; 1404 1405 enum PIPELINE 1406 { 1407 PIPELINE_MFXCOMMON = 2, //!< No additional details 1408 }; 1409 1410 enum COMMAND_TYPE 1411 { 1412 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1413 }; 1414 1415 //! \name Initializations 1416 1417 //! \brief Explicit member initialization function _VDENC_CMD2_CMD_VDENC_CMD2_CMD1418 _VDENC_CMD2_CMD() 1419 { 1420 MOS_ZeroMemory(this, sizeof(*this)); 1421 1422 DW0.Value = 0; 1423 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 1424 DW0.Subopb = SUBOPB_VDENCCMD2CMD; 1425 DW0.Subopa = SUBOPA_UNNAMED0; 1426 DW0.Opcode = OPCODE_VDENCPIPE; 1427 DW0.Pipeline = PIPELINE_MFXCOMMON; 1428 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 1429 } 1430 1431 static const size_t dwSize = 62; 1432 static const size_t byteSize = 248; 1433 }; 1434 struct _VDENC_AVC_IMG_STATE_CMD 1435 { 1436 union 1437 { 1438 struct 1439 { 1440 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1441 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1442 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 1443 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 1444 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 1445 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1446 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1447 }; 1448 uint32_t Value; 1449 } DW0; 1450 union 1451 { 1452 struct 1453 { 1454 uint32_t : __CODEGEN_BITFIELD(0, 1); 1455 uint32_t PictureType : __CODEGEN_BITFIELD(2, 3); 1456 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD(4, 4); 1457 uint32_t colloc_mv_wr_en : __CODEGEN_BITFIELD(5, 5); 1458 uint32_t SubpelMode : __CODEGEN_BITFIELD(6, 7); 1459 uint32_t : __CODEGEN_BITFIELD(8, 31); 1460 }; 1461 uint32_t Value; 1462 } DW1; 1463 union 1464 { 1465 struct 1466 { 1467 uint32_t : __CODEGEN_BITFIELD(0, 12); 1468 uint32_t colloc_mv_rd_en : __CODEGEN_BITFIELD(13, 13); 1469 uint32_t : __CODEGEN_BITFIELD(14, 17); 1470 uint32_t BidirectionalWeight : __CODEGEN_BITFIELD(18, 23); 1471 uint32_t : __CODEGEN_BITFIELD(24, 31); 1472 }; 1473 uint32_t Value; 1474 } DW2; 1475 union 1476 { 1477 struct 1478 { 1479 uint32_t PictureHeightMinusOne : __CODEGEN_BITFIELD(0, 7); 1480 uint32_t : __CODEGEN_BITFIELD(8, 15); 1481 uint32_t PictureWidth : __CODEGEN_BITFIELD(16, 24); 1482 uint32_t : __CODEGEN_BITFIELD(25, 31); 1483 }; 1484 uint32_t Value; 1485 } DW3; 1486 union 1487 { 1488 struct 1489 { 1490 uint32_t : __CODEGEN_BITFIELD(0, 31); 1491 }; 1492 uint32_t Value; 1493 } DW4; 1494 union 1495 { 1496 struct 1497 { 1498 uint32_t FwdRefIdx0ReferencePicture : __CODEGEN_BITFIELD(0, 3); 1499 uint32_t BwdRefIdx0ReferencePicture : __CODEGEN_BITFIELD(4, 7); 1500 uint32_t FwdRefIdx1ReferencePicture : __CODEGEN_BITFIELD(8, 11); 1501 uint32_t : __CODEGEN_BITFIELD(12, 15); 1502 uint32_t FwdRefIdx2ReferencePicture : __CODEGEN_BITFIELD(16, 19); 1503 uint32_t NumberOfL0ReferencesMinusOne : __CODEGEN_BITFIELD(20, 23); 1504 uint32_t NumberOfL1ReferencesMinusOne : __CODEGEN_BITFIELD(24, 26); 1505 uint32_t : __CODEGEN_BITFIELD(27, 31); 1506 }; 1507 uint32_t Value; 1508 } DW5; 1509 union 1510 { 1511 struct 1512 { 1513 uint32_t IntraRefreshMbPos : __CODEGEN_BITFIELD(0, 7); 1514 uint32_t IntraRefreshMbSizeMinusOne : __CODEGEN_BITFIELD(8, 15); 1515 uint32_t IntraRefreshEnableRollingIEnable : __CODEGEN_BITFIELD(16, 16); 1516 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(17, 17); 1517 uint32_t : __CODEGEN_BITFIELD(18, 23); 1518 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(24, 31); 1519 }; 1520 uint32_t Value; 1521 } DW6; 1522 union 1523 { 1524 struct 1525 { 1526 uint32_t : __CODEGEN_BITFIELD(0, 31); 1527 }; 1528 uint32_t Value; 1529 } DW7; 1530 union 1531 { 1532 struct 1533 { 1534 uint32_t : __CODEGEN_BITFIELD(0, 31); 1535 }; 1536 uint32_t Value; 1537 } DW8; 1538 union 1539 { 1540 struct 1541 { 1542 uint32_t RoiQpAdjustmentForZone0 : __CODEGEN_BITFIELD(0, 3); 1543 uint32_t RoiQpAdjustmentForZone1 : __CODEGEN_BITFIELD(4, 7); 1544 uint32_t RoiQpAdjustmentForZone2 : __CODEGEN_BITFIELD(8, 11); 1545 uint32_t RoiQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15); 1546 uint32_t : __CODEGEN_BITFIELD(16, 31); 1547 }; 1548 uint32_t Value; 1549 } DW9; 1550 union 1551 { 1552 struct 1553 { 1554 uint32_t : __CODEGEN_BITFIELD(0, 31); 1555 }; 1556 uint32_t Value; 1557 } DW10; 1558 union 1559 { 1560 struct 1561 { 1562 uint32_t : __CODEGEN_BITFIELD(0, 31); 1563 }; 1564 uint32_t Value; 1565 } DW11; 1566 union 1567 { 1568 struct 1569 { 1570 uint32_t MinQp : __CODEGEN_BITFIELD(0, 7); 1571 uint32_t MaxQp : __CODEGEN_BITFIELD(8, 15); 1572 uint32_t : __CODEGEN_BITFIELD(16, 28); 1573 uint32_t NumBframesBetweenFwdAndBwd : __CODEGEN_BITFIELD(29, 30); 1574 uint32_t : __CODEGEN_BITFIELD(31, 31); 1575 }; 1576 uint32_t Value; 1577 } DW12; 1578 union 1579 { 1580 struct 1581 { 1582 uint32_t RoiEnable : __CODEGEN_BITFIELD(0, 0); 1583 uint32_t : __CODEGEN_BITFIELD(1, 2); 1584 uint32_t MbLevelQpEnable : __CODEGEN_BITFIELD(3, 3); 1585 uint32_t : __CODEGEN_BITFIELD(4, 4); 1586 uint32_t MbLevelDeltaQpEnable : __CODEGEN_BITFIELD(5, 5); 1587 uint32_t : __CODEGEN_BITFIELD(6, 9); 1588 uint32_t LongtermReferenceFrameBwdRef0Indicator : __CODEGEN_BITFIELD(10, 10); 1589 uint32_t : __CODEGEN_BITFIELD(11, 31); 1590 }; 1591 uint32_t Value; 1592 } DW13; 1593 union 1594 { 1595 struct 1596 { 1597 uint32_t QpPrimeY : __CODEGEN_BITFIELD(0, 7); 1598 uint32_t : __CODEGEN_BITFIELD(8, 18); 1599 uint32_t TrellisQuantEn : __CODEGEN_BITFIELD(19, 19); 1600 uint32_t : __CODEGEN_BITFIELD(20, 31); 1601 }; 1602 uint32_t Value; 1603 } DW14; 1604 union 1605 { 1606 struct 1607 { 1608 uint32_t : __CODEGEN_BITFIELD(0, 7); 1609 uint32_t PocNumberForCurrentPicture : __CODEGEN_BITFIELD(8, 15); 1610 uint32_t : __CODEGEN_BITFIELD(16, 31); 1611 }; 1612 uint32_t Value; 1613 } DW15; 1614 union 1615 { 1616 struct 1617 { 1618 uint32_t : __CODEGEN_BITFIELD(0, 7); 1619 uint32_t PocNumberForFwdRef0 : __CODEGEN_BITFIELD(8, 15); 1620 uint32_t : __CODEGEN_BITFIELD(16, 31); 1621 }; 1622 uint32_t Value; 1623 } DW16; 1624 union 1625 { 1626 struct 1627 { 1628 uint32_t : __CODEGEN_BITFIELD(0, 7); 1629 uint32_t PocNumberForFwdRef1 : __CODEGEN_BITFIELD(8, 15); 1630 uint32_t : __CODEGEN_BITFIELD(16, 31); 1631 }; 1632 uint32_t Value; 1633 } DW17; 1634 union 1635 { 1636 struct 1637 { 1638 uint32_t : __CODEGEN_BITFIELD(0, 7); 1639 uint32_t PocNumberForFwdRef2 : __CODEGEN_BITFIELD(8, 15); 1640 uint32_t : __CODEGEN_BITFIELD(16, 31); 1641 }; 1642 uint32_t Value; 1643 } DW18; 1644 union 1645 { 1646 struct 1647 { 1648 uint32_t : __CODEGEN_BITFIELD(0, 7); 1649 uint32_t PocNumberForBwdRef0 : __CODEGEN_BITFIELD(8, 15); 1650 uint32_t : __CODEGEN_BITFIELD(16, 31); 1651 }; 1652 uint32_t Value; 1653 } DW19; 1654 union 1655 { 1656 struct 1657 { 1658 uint32_t : __CODEGEN_BITFIELD(0, 31); 1659 }; 1660 uint32_t Value; 1661 } DW20; 1662 union 1663 { 1664 struct 1665 { 1666 uint32_t : __CODEGEN_BITFIELD(0, 31); 1667 }; 1668 uint32_t Value; 1669 } DW21; 1670 union 1671 { 1672 struct 1673 { 1674 uint32_t : __CODEGEN_BITFIELD(0, 31); 1675 }; 1676 uint32_t Value; 1677 } DW22; 1678 union 1679 { 1680 struct 1681 { 1682 uint32_t : __CODEGEN_BITFIELD(0, 31); 1683 }; 1684 uint32_t Value; 1685 } DW23; 1686 union 1687 { 1688 struct 1689 { 1690 uint32_t : __CODEGEN_BITFIELD(0, 31); 1691 }; 1692 uint32_t Value; 1693 } DW24; 1694 union 1695 { 1696 struct 1697 { 1698 uint32_t : __CODEGEN_BITFIELD(0, 31); 1699 }; 1700 uint32_t Value; 1701 } DW25; 1702 1703 //! \name Initializations 1704 1705 //! \brief Explicit member initialization function _VDENC_AVC_IMG_STATE_CMD_VDENC_AVC_IMG_STATE_CMD1706 _VDENC_AVC_IMG_STATE_CMD() 1707 { 1708 MOS_ZeroMemory(this, sizeof(*this)); 1709 DW0.Value = 0x70850018; 1710 DW22.Value = 0x33000000; 1711 } 1712 1713 static const size_t dwSize = 26; 1714 static const size_t byteSize = 104; 1715 }; 1716 #endif 1717 1718 struct Cmd 1719 { 1720 public: 1721 //! 1722 //! \brief VDENC_64B_Aligned_Lower_Address 1723 //! \details 1724 //! 1725 //! 1726 struct VDENC_64B_Aligned_Lower_Address_CMD 1727 { 1728 union 1729 { 1730 //!< DWORD 0 1731 struct 1732 { 1733 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1734 uint32_t Address : __CODEGEN_BITFIELD(6, 31); //!< Address 1735 }; 1736 uint32_t Value; 1737 } DW0; 1738 1739 //! \name Local enumerations 1740 1741 //! \name Initializations 1742 1743 //! \brief Explicit member initialization function VDENC_64B_Aligned_Lower_Address_CMDCmd::VDENC_64B_Aligned_Lower_Address_CMD1744 VDENC_64B_Aligned_Lower_Address_CMD() 1745 { 1746 DW0.Value = 0; 1747 } 1748 1749 static const size_t dwSize = 1; 1750 static const size_t byteSize = 4; 1751 }; 1752 1753 //! 1754 //! \brief VDENC_64B_Aligned_Upper_Address 1755 //! \details 1756 //! 1757 //! 1758 struct VDENC_64B_Aligned_Upper_Address_CMD 1759 { 1760 union 1761 { 1762 //!< DWORD 0 1763 struct 1764 { 1765 uint32_t AddressUpperDword : __CODEGEN_BITFIELD(0, 15); //!< Address Upper DWord 1766 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1767 }; 1768 uint32_t Value; 1769 } DW0; 1770 1771 //! \name Local enumerations 1772 1773 //! \name Initializations 1774 1775 //! \brief Explicit member initialization function VDENC_64B_Aligned_Upper_Address_CMDCmd::VDENC_64B_Aligned_Upper_Address_CMD1776 VDENC_64B_Aligned_Upper_Address_CMD() 1777 { 1778 DW0.Value = 0; 1779 } 1780 1781 static const size_t dwSize = 1; 1782 static const size_t byteSize = 4; 1783 }; 1784 1785 //! 1786 //! \brief VDENC_Surface_Control_Bits 1787 //! \details 1788 //! 1789 //! 1790 struct VDENC_Surface_Control_Bits_CMD 1791 { 1792 union 1793 { 1794 //!< DWORD 0 1795 struct 1796 { 1797 uint32_t VDENC_Surface_Control_Bits_DW0_BIT0 : __CODEGEN_BITFIELD(0, 0); 1798 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD(1, 6); //!< Index to Memory Object Control State (MOCS) Tables: 1799 uint32_t ArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< ARBITRATION_PRIORITY_CONTROL 1800 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); 1801 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10); //!< Compression Type 1802 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 1803 uint32_t CacheSelect : __CODEGEN_BITFIELD(12, 12); //!< CACHE_SELECT 1804 uint32_t Reserved13 : __CODEGEN_BITFIELD(13, 14); //!< Reserved 1805 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 1806 uint32_t CompressionFormat : __CODEGEN_BITFIELD(16, 19); //!< Compression Format 1807 uint32_t Reserved20 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 1808 }; 1809 uint32_t Value; 1810 } DW0; 1811 1812 //! \name Local enumerations 1813 1814 //! \brief ARBITRATION_PRIORITY_CONTROL 1815 //! \details 1816 //! This field controls the priority of arbitration used in the GAC/GAM 1817 //! pipeline for this surface. 1818 enum ARBITRATION_PRIORITY_CONTROL 1819 { 1820 ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1821 ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1822 ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1823 ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1824 }; 1825 1826 //! \brief MEMORY_COMPRESSION_ENABLE 1827 //! \details 1828 //! Memory compression will be attempted for this surface. 1829 enum MEMORY_COMPRESSION_ENABLE 1830 { 1831 MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 1832 MEMORY_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 1833 }; 1834 1835 //! \brief MEMORY_COMPRESSION_MODE 1836 //! \details 1837 //! Distinguishes Vertical from Horizontal compression. Please refer to 1838 //! vol1a <b>Memory Data</b>. 1839 enum MEMORY_COMPRESSION_MODE 1840 { 1841 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 1842 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 1843 }; 1844 1845 //! \brief CACHE_SELECT 1846 //! \details 1847 //! This field controls if the Row Store is going to store inside Media 1848 //! Cache (rowstore cache) or to LLC. 1849 enum CACHE_SELECT 1850 { 1851 CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 1852 CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 1853 }; 1854 1855 //! \brief TILED_RESOURCE_MODE 1856 //! \details 1857 //! <b>For Media Surfaces</b>: This field specifies the tiled resource mode. 1858 enum TILED_RESOURCE_MODE 1859 { 1860 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource. 1861 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1862 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1863 }; 1864 1865 //! \name Initializations 1866 1867 //! \brief Explicit member initialization function VDENC_Surface_Control_Bits_CMDCmd::VDENC_Surface_Control_Bits_CMD1868 VDENC_Surface_Control_Bits_CMD() 1869 { 1870 DW0.Value = 0; 1871 DW0.ArbitrationPriorityControl = ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY; 1872 DW0.MemoryCompressionEnable = MEMORY_COMPRESSION_ENABLE_DISABLE; 1873 DW0.CacheSelect = CACHE_SELECT_UNNAMED0; 1874 } 1875 1876 static const size_t dwSize = 1; 1877 static const size_t byteSize = 4; 1878 }; 1879 1880 //! 1881 //! \brief VDENC_Sub_Mb_Pred_Mode 1882 //! \details 1883 //! 1884 //! 1885 struct VDENC_Sub_Mb_Pred_Mode_CMD 1886 { 1887 union 1888 { 1889 //!< WORD 0 1890 struct 1891 { 1892 uint8_t Submbpredmode0 : __CODEGEN_BITFIELD(0, 1); //!< SubMbPredMode[0] 1893 uint8_t Submbpredmode1 : __CODEGEN_BITFIELD(2, 3); //!< SubMbPredMode[1] 1894 uint8_t Submbpredmode2 : __CODEGEN_BITFIELD(4, 5); //!< SubMbPredMode[2] 1895 uint8_t Submbpredmode3 : __CODEGEN_BITFIELD(6, 7); //!< SubMbPredMode[3] 1896 }; 1897 uint8_t Value; 1898 } DW0; 1899 1900 //! \name Local enumerations 1901 1902 //! \name Initializations 1903 1904 //! \brief Explicit member initialization function VDENC_Sub_Mb_Pred_Mode_CMDCmd::VDENC_Sub_Mb_Pred_Mode_CMD1905 VDENC_Sub_Mb_Pred_Mode_CMD() 1906 { 1907 DW0.Value = 0; 1908 } 1909 1910 static const size_t dwSize = 0; 1911 static const size_t byteSize = 1; 1912 }; 1913 1914 //! 1915 //! \brief VDENC_Block_8x8_4 1916 //! \details 1917 //! 1918 //! 1919 struct VDENC_Block_8x8_4_CMD 1920 { 1921 union 1922 { 1923 //!< WORD 0 1924 struct 1925 { 1926 uint16_t Block8X80 : __CODEGEN_BITFIELD(0, 3); //!< Block8x8[0] 1927 uint16_t Block8X81 : __CODEGEN_BITFIELD(4, 7); //!< Block8x8[1] 1928 uint16_t Block8X82 : __CODEGEN_BITFIELD(8, 11); //!< Block8x8[2] 1929 uint16_t Block8X83 : __CODEGEN_BITFIELD(12, 15); //!< Block8x8[3] 1930 }; 1931 uint16_t Value; 1932 } DW0; 1933 1934 //! \name Local enumerations 1935 1936 //! \name Initializations 1937 1938 //! \brief Explicit member initialization function VDENC_Block_8x8_4_CMDCmd::VDENC_Block_8x8_4_CMD1939 VDENC_Block_8x8_4_CMD() 1940 { 1941 DW0.Value = 0; 1942 } 1943 1944 static const size_t dwSize = 0; 1945 static const size_t byteSize = 2; 1946 }; 1947 1948 //! 1949 //! \brief VDENC_Delta_MV_XY 1950 //! \details 1951 //! 1952 //! 1953 //! Calculates the difference between the actual MV for the Sub Macroblock 1954 //! and the predicted MV based on the availability of the neighbors. 1955 //! 1956 //! This is calculated and populated for Inter frames only. In case of an 1957 //! Intra MB in Inter frames, this value should be 0. 1958 //! 1959 struct VDENC_Delta_MV_XY_CMD 1960 { 1961 union 1962 { 1963 //!< DWORD 0 1964 struct 1965 { 1966 uint32_t X0 : __CODEGEN_BITFIELD(0, 15); //!< X0 1967 uint32_t Y0 : __CODEGEN_BITFIELD(16, 31); //!< Y0 1968 }; 1969 uint32_t Value; 1970 } DW0; 1971 union 1972 { 1973 //!< DWORD 1 1974 struct 1975 { 1976 uint32_t X1 : __CODEGEN_BITFIELD(0, 15); //!< X1 1977 uint32_t Y1 : __CODEGEN_BITFIELD(16, 31); //!< Y1 1978 }; 1979 uint32_t Value; 1980 } DW1; 1981 union 1982 { 1983 //!< DWORD 2 1984 struct 1985 { 1986 uint32_t X2 : __CODEGEN_BITFIELD(0, 15); //!< X2 1987 uint32_t Y2 : __CODEGEN_BITFIELD(16, 31); //!< Y2 1988 }; 1989 uint32_t Value; 1990 } DW2; 1991 union 1992 { 1993 //!< DWORD 3 1994 struct 1995 { 1996 uint32_t X3 : __CODEGEN_BITFIELD(0, 15); //!< X3 1997 uint32_t Y3 : __CODEGEN_BITFIELD(16, 31); //!< Y3 1998 }; 1999 uint32_t Value; 2000 } DW3; 2001 2002 //! \name Local enumerations 2003 2004 //! \brief X0 2005 //! \details 2006 enum X0 2007 { 2008 X0_UNNAMED0 = 0, //!< No additional details 2009 }; 2010 2011 //! \brief Y0 2012 //! \details 2013 enum Y0 2014 { 2015 Y0_UNNAMED0 = 0, //!< No additional details 2016 }; 2017 2018 //! \brief X1 2019 //! \details 2020 enum X1 2021 { 2022 X1_UNNAMED0 = 0, //!< No additional details 2023 }; 2024 2025 //! \brief Y1 2026 //! \details 2027 enum Y1 2028 { 2029 Y1_UNNAMED0 = 0, //!< No additional details 2030 }; 2031 2032 //! \brief X2 2033 //! \details 2034 enum X2 2035 { 2036 X2_UNNAMED0 = 0, //!< No additional details 2037 }; 2038 2039 //! \brief Y2 2040 //! \details 2041 enum Y2 2042 { 2043 Y2_UNNAMED0 = 0, //!< No additional details 2044 }; 2045 2046 //! \brief X3 2047 //! \details 2048 enum X3 2049 { 2050 X3_UNNAMED0 = 0, //!< No additional details 2051 }; 2052 2053 //! \brief Y3 2054 //! \details 2055 enum Y3 2056 { 2057 Y3_UNNAMED0 = 0, //!< No additional details 2058 }; 2059 2060 //! \name Initializations 2061 2062 //! \brief Explicit member initialization function VDENC_Delta_MV_XY_CMDCmd::VDENC_Delta_MV_XY_CMD2063 VDENC_Delta_MV_XY_CMD() 2064 { 2065 MOS_ZeroMemory(this, sizeof(*this)); 2066 2067 DW0.X0 = X0_UNNAMED0; 2068 DW0.Y0 = Y0_UNNAMED0; 2069 2070 DW1.X1 = X1_UNNAMED0; 2071 DW1.Y1 = Y1_UNNAMED0; 2072 2073 DW2.X2 = X2_UNNAMED0; 2074 DW2.Y2 = Y2_UNNAMED0; 2075 2076 DW3.X3 = X3_UNNAMED0; 2077 DW3.Y3 = Y3_UNNAMED0; 2078 } 2079 2080 static const size_t dwSize = 4; 2081 static const size_t byteSize = 16; 2082 }; 2083 2084 //! 2085 //! \brief VDENC_Colocated_MV_Picture 2086 //! \details 2087 //! 2088 //! 2089 struct VDENC_Colocated_MV_Picture_CMD 2090 { 2091 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2092 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2093 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2094 2095 //! \name Local enumerations 2096 2097 //! \name Initializations 2098 2099 //! \brief Explicit member initialization function VDENC_Colocated_MV_Picture_CMDCmd::VDENC_Colocated_MV_Picture_CMD2100 VDENC_Colocated_MV_Picture_CMD() 2101 { 2102 MOS_ZeroMemory(this, sizeof(*this)); 2103 } 2104 2105 static const size_t dwSize = 3; 2106 static const size_t byteSize = 12; 2107 }; 2108 2109 //! 2110 //! \brief VDENC_Down_Scaled_Reference_Picture 2111 //! \details 2112 //! 2113 //! 2114 struct VDENC_Down_Scaled_Reference_Picture_CMD 2115 { 2116 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2117 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2118 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2119 2120 //! \name Local enumerations 2121 2122 //! \name Initializations 2123 2124 //! \brief Explicit member initialization function VDENC_Down_Scaled_Reference_Picture_CMDCmd::VDENC_Down_Scaled_Reference_Picture_CMD2125 VDENC_Down_Scaled_Reference_Picture_CMD() 2126 { 2127 MOS_ZeroMemory(this, sizeof(*this)); 2128 } 2129 2130 static const size_t dwSize = 3; 2131 static const size_t byteSize = 12; 2132 }; 2133 2134 //! 2135 //! \brief VDENC_FRAME_BASED_STATISTICS_STREAMOUT 2136 //! \details 2137 //! 2138 //! 2139 struct VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD 2140 { 2141 union 2142 { 2143 //!< DWORD 0 2144 struct 2145 { 2146 uint32_t SumSadHaarForBestMbChoice; //!< Sum sad\haar for best MB choice 2147 }; 2148 uint32_t Value; 2149 } DW0; 2150 union 2151 { 2152 //!< DWORD 1 2153 struct 2154 { 2155 uint32_t IntraIso16X16MbCount : __CODEGEN_BITFIELD(0, 15); //!< Intra iso 16x16 MB count 2156 uint32_t IntraMbCount : __CODEGEN_BITFIELD(16, 31); //!< Intra MB count 2157 }; 2158 uint32_t Value; 2159 } DW1; 2160 union 2161 { 2162 //!< DWORD 2 2163 struct 2164 { 2165 uint32_t IntraIso4X4MbCount : __CODEGEN_BITFIELD(0, 15); //!< Intra iso 4x4 MB count 2166 uint32_t IntraIso8X8MbCount : __CODEGEN_BITFIELD(16, 31); //!< Intra iso 8x8 MB count 2167 }; 2168 uint32_t Value; 2169 } DW2; 2170 union 2171 { 2172 //!< DWORD 3 2173 struct 2174 { 2175 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD(0, 15); //!< segment map count 0 2176 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(16, 31); //!< segment map count 1 2177 }; 2178 uint32_t Value; 2179 } DW3; 2180 union 2181 { 2182 //!< DWORD 4 2183 struct 2184 { 2185 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD(0, 15); //!< segment map count 2 2186 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(16, 31); //!< segment map count 3 2187 }; 2188 uint32_t Value; 2189 } DW4; 2190 2191 uint32_t Reserved160[12]; //!< Reserved 2192 2193 union 2194 { 2195 //!< DWORD 17 2196 struct 2197 { 2198 uint32_t SumSadHaarForBestMbChoiceBottomHalfPopulation; //!< Sum sad\haar for best MB choice bottom half population 2199 }; 2200 uint32_t Value; 2201 } DW17; 2202 union 2203 { 2204 //!< DWORD 18 2205 struct 2206 { 2207 uint32_t SumSadHaarForBestMbChoiceTopHalfPopulation; //!< Sum sad\haar for best MB choice top half population 2208 }; 2209 uint32_t Value; 2210 } DW18; 2211 union 2212 { 2213 //!< DWORD 19 2214 struct 2215 { 2216 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD(0, 15); //!< Sum top half population occurrences 2217 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31); //!< Sum bottom half population occurrences 2218 }; 2219 uint32_t Value; 2220 } DW19; 2221 2222 //! \name Local enumerations 2223 2224 //! \name Initializations 2225 2226 //! \brief Explicit member initialization function VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMDCmd::VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD2227 VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD() 2228 { 2229 MOS_ZeroMemory(this, sizeof(*this)); 2230 } 2231 2232 static const size_t dwSize = 20; 2233 static const size_t byteSize = 80; 2234 }; 2235 2236 //! 2237 //! \brief VDENC_Mode_StreamOut_Data 2238 //! \details 2239 //! 2240 //! 2241 struct VDENC_Mode_StreamOut_Data_CMD 2242 { 2243 union 2244 { 2245 //!< DWORD 0 2246 struct 2247 { 2248 uint32_t MbX : __CODEGEN_BITFIELD(0, 7); //!< MB.X 2249 uint32_t MbY : __CODEGEN_BITFIELD(8, 15); //!< MB.Y 2250 uint32_t MinimalDistortion : __CODEGEN_BITFIELD(16, 31); //!< Minimal Distortion 2251 }; 2252 uint32_t Value; 2253 } DW0; 2254 union 2255 { 2256 //!< DWORD 1 2257 struct 2258 { 2259 uint32_t Skiprawdistortion : __CODEGEN_BITFIELD(0, 15); //!< SkipRawDistortion 2260 uint32_t Interrawdistortion : __CODEGEN_BITFIELD(16, 31); //!< InterRawDistortion 2261 }; 2262 uint32_t Value; 2263 } DW1; 2264 union 2265 { 2266 //!< DWORD 2 2267 struct 2268 { 2269 uint32_t Bestintrarawdistortion : __CODEGEN_BITFIELD(0, 15); //!< BestIntraRawDistortion 2270 uint32_t IntermbmodeChromaPredictionMode : __CODEGEN_BITFIELD(16, 17); //!< INTERMBMODECHROMA_PREDICTION_MODE 2271 uint32_t Intrambmode : __CODEGEN_BITFIELD(18, 19); //!< INTRAMBMODE 2272 uint32_t Intrambflag : __CODEGEN_BITFIELD(20, 20); //!< INTRAMBFLAG 2273 uint32_t Lastmbflag : __CODEGEN_BITFIELD(21, 21); //!< LASTMBFLAG 2274 uint32_t CoefficientClampOccurred : __CODEGEN_BITFIELD(22, 22); //!< Coefficient Clamp Occurred 2275 uint32_t ConformanceViolation : __CODEGEN_BITFIELD(23, 23); //!< Conformance Violation 2276 uint32_t Submbpredmode : __CODEGEN_BITFIELD(24, 31); //!< SubMbPredMode 2277 }; 2278 uint32_t Value; 2279 } DW2; 2280 union 2281 { 2282 //!< DWORD 3 2283 struct 2284 { 2285 uint32_t Lumaintramode0 : __CODEGEN_BITFIELD(0, 15); //!< LumaIntraMode[0] 2286 uint32_t Lumaintramode1 : __CODEGEN_BITFIELD(16, 31); //!< LumaIntraMode[1] 2287 }; 2288 uint32_t Value; 2289 } DW3; 2290 union 2291 { 2292 //!< DWORD 4 2293 struct 2294 { 2295 uint32_t Lumaintramode2 : __CODEGEN_BITFIELD(0, 15); //!< LumaIntraMode[2] 2296 uint32_t Lumaintramode3 : __CODEGEN_BITFIELD(16, 31); //!< LumaIntraMode[3] 2297 }; 2298 uint32_t Value; 2299 } DW4; 2300 VDENC_Delta_MV_XY_CMD DeltaMv0; //!< Delta MV0 2301 VDENC_Delta_MV_XY_CMD DeltaMv1; //!< Delta MV1 2302 union 2303 { 2304 //!< DWORD 13 2305 struct 2306 { 2307 uint32_t FwdRefids : __CODEGEN_BITFIELD(0, 15); //!< FWD REFIDs 2308 uint32_t BwdRefids : __CODEGEN_BITFIELD(16, 31); //!< BWD REFIDs 2309 }; 2310 uint32_t Value; 2311 } DW13; 2312 union 2313 { 2314 //!< DWORD 14 2315 struct 2316 { 2317 uint32_t QpY : __CODEGEN_BITFIELD(0, 5); //!< QP_y 2318 uint32_t MbBitCount : __CODEGEN_BITFIELD(6, 18); //!< MB_Bit_Count 2319 uint32_t MbHeaderCount : __CODEGEN_BITFIELD(19, 31); //!< MB_Header_Count 2320 }; 2321 uint32_t Value; 2322 } DW14; 2323 union 2324 { 2325 //!< DWORD 15 2326 struct 2327 { 2328 uint32_t MbType : __CODEGEN_BITFIELD(0, 4); //!< MB Type 2329 uint32_t BlockCbp : __CODEGEN_BITFIELD(5, 30); //!< Block CBP 2330 uint32_t Skipmbflag : __CODEGEN_BITFIELD(31, 31); //!< SkipMbFlag 2331 }; 2332 uint32_t Value; 2333 } DW15; 2334 2335 //! \name Local enumerations 2336 2337 //! \brief INTERMBMODECHROMA_PREDICTION_MODE 2338 //! \details 2339 //! This field indicates the InterMB Parition type for Inter MB. 2340 //! <br>OR</br> 2341 //! This field indicates Chroma Prediction Mode for Intra MB. 2342 enum INTERMBMODECHROMA_PREDICTION_MODE 2343 { 2344 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0 = 0, //!< 16x16 2345 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED1 = 1, //!< 16x8 2346 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED2 = 2, //!< 8x16 2347 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED3 = 3, //!< 8x8 2348 }; 2349 2350 //! \brief INTRAMBMODE 2351 //! \details 2352 //! This field indicates the Best Intra Partition. 2353 enum INTRAMBMODE 2354 { 2355 INTRAMBMODE_UNNAMED0 = 0, //!< 16x16 2356 INTRAMBMODE_UNNAMED1 = 1, //!< 8x8 2357 INTRAMBMODE_UNNAMED2 = 2, //!< 4x4 2358 }; 2359 2360 //! \brief INTRAMBFLAG 2361 //! \details 2362 //! This field specifies whether the current macroblock is an Intra (I) 2363 //! macroblock. 2364 enum INTRAMBFLAG 2365 { 2366 INTRAMBFLAG_INTER = 0, //!< inter macroblock 2367 INTRAMBFLAG_INTRA = 1, //!< intra macroblock 2368 }; 2369 2370 enum LASTMBFLAG 2371 { 2372 LASTMBFLAG_NOTLAST = 0, //!< The current MB is not the last MB in the current Slice. 2373 LASTMBFLAG_LAST = 1, //!< The current MB is the last MB in the current Slice. 2374 }; 2375 2376 //! \name Initializations 2377 2378 //! \brief Explicit member initialization function VDENC_Mode_StreamOut_Data_CMDCmd::VDENC_Mode_StreamOut_Data_CMD2379 VDENC_Mode_StreamOut_Data_CMD() 2380 { 2381 MOS_ZeroMemory(this, sizeof(*this)); 2382 2383 DW2.IntermbmodeChromaPredictionMode = INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0; 2384 DW2.Intrambmode = INTRAMBMODE_UNNAMED0; 2385 DW2.Intrambflag = INTRAMBFLAG_INTER; 2386 DW2.Lastmbflag = LASTMBFLAG_NOTLAST; 2387 } 2388 2389 static const size_t dwSize = 16; 2390 static const size_t byteSize = 64; 2391 }; 2392 2393 //! 2394 //! \brief VDENC_Original_Uncompressed_Picture 2395 //! \details 2396 //! 2397 //! 2398 struct VDENC_Original_Uncompressed_Picture_CMD 2399 { 2400 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2401 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2402 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2403 2404 //! \name Local enumerations 2405 2406 //! \name Initializations 2407 2408 //! \brief Explicit member initialization function VDENC_Original_Uncompressed_Picture_CMDCmd::VDENC_Original_Uncompressed_Picture_CMD2409 VDENC_Original_Uncompressed_Picture_CMD() 2410 { 2411 MOS_ZeroMemory(this, sizeof(*this)); 2412 } 2413 2414 static const size_t dwSize = 3; 2415 static const size_t byteSize = 12; 2416 }; 2417 2418 //! 2419 //! \brief VDENC_Reference_Picture 2420 //! \details 2421 //! 2422 //! 2423 struct VDENC_Reference_Picture_CMD 2424 { 2425 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2426 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2427 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2428 2429 //! \name Local enumerations 2430 2431 //! \name Initializations 2432 2433 //! \brief Explicit member initialization function VDENC_Reference_Picture_CMDCmd::VDENC_Reference_Picture_CMD2434 VDENC_Reference_Picture_CMD() 2435 { 2436 MOS_ZeroMemory(this, sizeof(*this)); 2437 } 2438 2439 static const size_t dwSize = 3; 2440 static const size_t byteSize = 12; 2441 }; 2442 2443 //! 2444 //! \brief VDENC_Row_Store_Scratch_Buffer_Picture 2445 //! \details 2446 //! 2447 //! 2448 struct VDENC_Row_Store_Scratch_Buffer_Picture_CMD 2449 { 2450 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2451 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2452 VDENC_Surface_Control_Bits_CMD BufferPictureFields; //!< Buffer Picture Fields 2453 2454 //! \name Local enumerations 2455 2456 //! \name Initializations 2457 2458 //! \brief Explicit member initialization function VDENC_Row_Store_Scratch_Buffer_Picture_CMDCmd::VDENC_Row_Store_Scratch_Buffer_Picture_CMD2459 VDENC_Row_Store_Scratch_Buffer_Picture_CMD() 2460 { 2461 MOS_ZeroMemory(this, sizeof(*this)); 2462 } 2463 2464 static const size_t dwSize = 3; 2465 static const size_t byteSize = 12; 2466 }; 2467 2468 //! 2469 //! \brief VDENC_Statistics_Streamout 2470 //! \details 2471 //! 2472 //! 2473 struct VDENC_Statistics_Streamout_CMD 2474 { 2475 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2476 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2477 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2478 2479 //! \name Local enumerations 2480 2481 //! \name Initializations 2482 2483 //! \brief Explicit member initialization function VDENC_Statistics_Streamout_CMDCmd::VDENC_Statistics_Streamout_CMD2484 VDENC_Statistics_Streamout_CMD() 2485 { 2486 MOS_ZeroMemory(this, sizeof(*this)); 2487 } 2488 2489 static const size_t dwSize = 3; 2490 static const size_t byteSize = 12; 2491 }; 2492 2493 //! 2494 //! \brief VDENC_Streamin_Data_Picture 2495 //! \details 2496 //! 2497 //! 2498 struct VDENC_Streamin_Data_Picture_CMD 2499 { 2500 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2501 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2502 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2503 2504 //! \name Local enumerations 2505 2506 //! \name Initializations 2507 2508 //! \brief Explicit member initialization function VDENC_Streamin_Data_Picture_CMDCmd::VDENC_Streamin_Data_Picture_CMD2509 VDENC_Streamin_Data_Picture_CMD() 2510 { 2511 MOS_ZeroMemory(this, sizeof(*this)); 2512 } 2513 2514 static const size_t dwSize = 3; 2515 static const size_t byteSize = 12; 2516 }; 2517 2518 //! 2519 //! \brief VDENC_STREAMIN_STATE 2520 //! \details 2521 //! 2522 //! 2523 struct VDENC_STREAMIN_STATE_CMD 2524 { 2525 union 2526 { 2527 //!< DWORD 0 2528 struct 2529 { 2530 uint32_t RegionOfInterestRoiSelection : __CODEGEN_BITFIELD(0, 7); //!< Region of Interest (ROI) Selection 2531 uint32_t Forceintra : __CODEGEN_BITFIELD(8, 8); //!< FORCEINTRA 2532 uint32_t Forceskip : __CODEGEN_BITFIELD(9, 9); //!< FORCESKIP 2533 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 31); //!< Reserved 2534 }; 2535 uint32_t Value; 2536 } DW0; 2537 union 2538 { 2539 //!< DWORD 1 2540 struct 2541 { 2542 uint32_t Qpprimey : __CODEGEN_BITFIELD(0, 7); //!< QPPRIMEY 2543 uint32_t Targetsizeinword : __CODEGEN_BITFIELD(8, 15); //!< TargetSizeInWord 2544 uint32_t Maxsizeinword : __CODEGEN_BITFIELD(16, 23); //!< MaxSizeInWord 2545 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 2546 }; 2547 uint32_t Value; 2548 } DW1; 2549 union 2550 { 2551 //!< DWORD 2 2552 struct 2553 { 2554 uint32_t FwdPredictorX : __CODEGEN_BITFIELD(0, 15); //!< Fwd Predictor.X 2555 uint32_t FwdPredictorY : __CODEGEN_BITFIELD(16, 31); //!< Fwd Predictor.Y 2556 }; 2557 uint32_t Value; 2558 } DW2; 2559 union 2560 { 2561 //!< DWORD 3 2562 struct 2563 { 2564 uint32_t BwdPredictorX : __CODEGEN_BITFIELD(0, 15); //!< Bwd Predictor.X 2565 uint32_t BwdPredictorY : __CODEGEN_BITFIELD(16, 31); //!< Bwd Predictor.Y 2566 }; 2567 uint32_t Value; 2568 } DW3; 2569 union 2570 { 2571 //!< DWORD 4 2572 struct 2573 { 2574 uint32_t FwdRefid0 : __CODEGEN_BITFIELD(0, 3); //!< Fwd RefID0 2575 uint32_t BwdRefid0 : __CODEGEN_BITFIELD(4, 7); //!< Bwd RefID0 2576 uint32_t Reserved136 : __CODEGEN_BITFIELD(8, 31); //!< Reserved 2577 }; 2578 uint32_t Value; 2579 } DW4; 2580 2581 uint32_t Reserved160[11]; //!< Reserved 2582 2583 //! \name Local enumerations 2584 2585 //! \brief FORCEINTRA 2586 //! \details 2587 //! This field specifies whether current macroblock should be coded as an 2588 //! intra macroblock. 2589 //! It is illegal to enable both ForceSkip and ForceIntra for 2590 //! the same macroblock. 2591 //! This should be disabled if Rolling-I is enabled in the 2592 //! VDEnc Image State. 2593 enum FORCEINTRA 2594 { 2595 FORCEINTRA_DISABLE = 0, //!< VDEnc determined macroblock type 2596 FORCEINTRA_ENABLE = 1, //!< Force to be coded as an intra macroblock 2597 }; 2598 2599 //! \brief FORCESKIP 2600 //! \details 2601 //! This field specifies whether current macroblock should be coded as a 2602 //! skipped macroblock. 2603 //! It is illegal to enable both ForceSkip and ForceIntra for 2604 //! the same macroblock. 2605 //! This should be disabled if Rolling-I is enabled in the 2606 //! VDEnc Image State. 2607 //! It is illegal to enable ForceSkip for I-Frames. 2608 enum FORCESKIP 2609 { 2610 FORCESKIP_DISABLE = 0, //!< VDEnc determined macroblock type 2611 FORCESKIP_ENABLE = 1, //!< Force to be coded as a skipped macroblock 2612 }; 2613 2614 //! \brief QPPRIMEY 2615 //! \details 2616 //! Quantization parameter for Y. 2617 enum QPPRIMEY 2618 { 2619 QPPRIMEY_UNNAMED0 = 0, //!< No additional details 2620 QPPRIMEY_UNNAMED51 = 51, //!< No additional details 2621 }; 2622 2623 //! \name Initializations 2624 2625 //! \brief Explicit member initialization function VDENC_STREAMIN_STATE_CMDCmd::VDENC_STREAMIN_STATE_CMD2626 VDENC_STREAMIN_STATE_CMD() 2627 { 2628 MOS_ZeroMemory(this, sizeof(*this)); 2629 2630 DW0.Forceintra = FORCEINTRA_DISABLE; 2631 DW0.Forceskip = FORCESKIP_DISABLE; 2632 2633 DW1.Qpprimey = QPPRIMEY_UNNAMED0; 2634 } 2635 2636 static const size_t dwSize = 16; 2637 static const size_t byteSize = 64; 2638 }; 2639 2640 //! 2641 //! \brief VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT 2642 //! \details 2643 //! 2644 //! 2645 struct VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD 2646 { 2647 union 2648 { 2649 //!< DWORD 0 2650 struct 2651 { 2652 uint32_t SumSadHaarForBestModeDecision; //!< Sum sad\haar for best mode decision 2653 }; 2654 uint32_t Value; 2655 } DW0; 2656 union 2657 { 2658 //!< DWORD 1 2659 struct 2660 { 2661 uint32_t IntraCuCountNormalized : __CODEGEN_BITFIELD(0, 19); //!< Intra CU count normalized 2662 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2663 }; 2664 uint32_t Value; 2665 } DW1; 2666 union 2667 { 2668 //!< DWORD 2 2669 struct 2670 { 2671 uint32_t NonSkipInterCuCountNormalized : __CODEGEN_BITFIELD(0, 19); //!< Non-skip Inter CU count normalized 2672 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2673 }; 2674 uint32_t Value; 2675 } DW2; 2676 union 2677 { 2678 //!< DWORD 3 2679 struct 2680 { 2681 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD(0, 19); //!< segment map count 0 2682 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2683 }; 2684 uint32_t Value; 2685 } DW3; 2686 union 2687 { 2688 //!< DWORD 4 2689 struct 2690 { 2691 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(0, 19); //!< segment map count 1 2692 uint32_t Reserved148 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2693 }; 2694 uint32_t Value; 2695 } DW4; 2696 union 2697 { 2698 //!< DWORD 5 2699 struct 2700 { 2701 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD(0, 19); //!< segment map count 2 2702 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2703 }; 2704 uint32_t Value; 2705 } DW5; 2706 union 2707 { 2708 //!< DWORD 6 2709 struct 2710 { 2711 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(0, 19); //!< segment map count 3 2712 uint32_t Reserved212 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2713 }; 2714 uint32_t Value; 2715 } DW6; 2716 union 2717 { 2718 //!< DWORD 7 2719 struct 2720 { 2721 uint32_t MvXGlobalMeSample025X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 0 (.25x,.25x) 2722 uint32_t MvYGlobalMeSample025X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 0 (.25x,.25x) 2723 }; 2724 uint32_t Value; 2725 } DW7; 2726 union 2727 { 2728 //!< DWORD 8 2729 struct 2730 { 2731 uint32_t MvXGlobalMeSample125X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 1 (.25x,.25x) 2732 uint32_t MvYGlobalMeSample125X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 1 (.25x,.25x) 2733 }; 2734 uint32_t Value; 2735 } DW8; 2736 union 2737 { 2738 //!< DWORD 9 2739 struct 2740 { 2741 uint32_t MvXGlobalMeSample225X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 2 (.25x,.25x) 2742 uint32_t MvYGlobalMeSample225X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 2 (.25x,.25x) 2743 }; 2744 uint32_t Value; 2745 } DW9; 2746 union 2747 { 2748 //!< DWORD 10 2749 struct 2750 { 2751 uint32_t MvXGlobalMeSample325X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 3 (.25x,.25x) 2752 uint32_t MvYGlobalMeSample325X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 3 (.25x,.25x) 2753 }; 2754 uint32_t Value; 2755 } DW10; 2756 union 2757 { 2758 //!< DWORD 11 2759 struct 2760 { 2761 uint32_t MvXGlobalMeSample425X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 4 (.25x,.25x) 2762 uint32_t MvYGlobalMeSample425X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 4 (.25x,.25x) 2763 }; 2764 uint32_t Value; 2765 } DW11; 2766 union 2767 { 2768 //!< DWORD 12 2769 struct 2770 { 2771 uint32_t MvXGlobalMeSample525X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 5 (.25x,.25x) 2772 uint32_t MvYGlobalMeSample525X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 5 (.25x,.25x) 2773 }; 2774 uint32_t Value; 2775 } DW12; 2776 union 2777 { 2778 //!< DWORD 13 2779 struct 2780 { 2781 uint32_t MvXGlobalMeSample625X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 6 (.25x,.25x) 2782 uint32_t MvYGlobalMeSample625X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 6 (.25x,.25x) 2783 }; 2784 uint32_t Value; 2785 } DW13; 2786 union 2787 { 2788 //!< DWORD 14 2789 struct 2790 { 2791 uint32_t MvXGlobalMeSample725X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 7 (.25x,.25x) 2792 uint32_t MvYGlobalMeSample725X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 7 (.25x,.25x) 2793 }; 2794 uint32_t Value; 2795 } DW14; 2796 union 2797 { 2798 //!< DWORD 15 2799 struct 2800 { 2801 uint32_t MvXGlobalMeSample825X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 8 (.25x,.25x) 2802 uint32_t MvYGlobalMeSample825X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 8 (.25x,.25x) 2803 }; 2804 uint32_t Value; 2805 } DW15; 2806 union 2807 { 2808 //!< DWORD 16 2809 struct 2810 { 2811 uint32_t RefidForGlobalmeSample0 : __CODEGEN_BITFIELD(0, 1); //!< RefID for GlobalME sample 0 2812 uint32_t RefidForGlobalmeSample18 : __CODEGEN_BITFIELD(2, 17); //!< RefID for GlobalME sample 1-8 2813 uint32_t Reserved530 : __CODEGEN_BITFIELD(18, 31); //!< Reserved 2814 }; 2815 uint32_t Value; 2816 } DW16; 2817 union 2818 { 2819 //!< DWORD 17 2820 struct 2821 { 2822 uint32_t PaletteCuCountNormalized : __CODEGEN_BITFIELD(0, 19); //!< Palette CU Count Normalized 2823 uint32_t Reserved564 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2824 }; 2825 uint32_t Value; 2826 } DW17; 2827 union 2828 { 2829 //!< DWORD 18 2830 struct 2831 { 2832 uint32_t IbcCuCountNormalized : __CODEGEN_BITFIELD(0, 19); //!< IBC CU Count Normalized 2833 uint32_t Reserved596 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2834 }; 2835 uint32_t Value; 2836 } DW18; 2837 union 2838 { 2839 //!< DWORD 19 2840 struct 2841 { 2842 uint32_t Reserved; 2843 }; 2844 uint32_t Value; 2845 } DW19; 2846 union 2847 { 2848 //!< DWORD 20 2849 struct 2850 { 2851 uint32_t Reserved656; //!< Reserved 2852 }; 2853 uint32_t Value; 2854 } DW20; 2855 union 2856 { 2857 //!< DWORD 21 2858 struct 2859 { 2860 uint32_t Reserved672; //!< Reserved 2861 }; 2862 uint32_t Value; 2863 } DW21; 2864 union 2865 { 2866 //!< DWORD 22 2867 struct 2868 { 2869 uint32_t PositionOfTimerExpiration : __CODEGEN_BITFIELD(0, 15); //!< Position of Timer expiration 2870 uint32_t TimerExpireStatus : __CODEGEN_BITFIELD(16, 16); //!< Timer Expire status 2871 uint32_t Reserved721 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 2872 }; 2873 uint32_t Value; 2874 } DW22; 2875 union 2876 { 2877 //!< DWORD 23 2878 struct 2879 { 2880 uint32_t LocationOfPanic : __CODEGEN_BITFIELD(0, 15); //!< Location of panic 2881 uint32_t PanicDetected : __CODEGEN_BITFIELD(16, 16); //!< Panic detected 2882 uint32_t Reserved753 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 2883 }; 2884 uint32_t Value; 2885 } DW23; 2886 2887 uint32_t Reserved768[5]; //!< Reserved 2888 2889 union 2890 { 2891 //!< DWORD 29 2892 struct 2893 { 2894 uint32_t SumSadHaarForBestModeDecisionBottomHalfPopulation; //!< Sum sad\haar for best mode decision bottom half population 2895 }; 2896 uint32_t Value; 2897 } DW29; 2898 union 2899 { 2900 //!< DWORD 30 2901 struct 2902 { 2903 uint32_t SumSadHaarForBestModeDecisionTopHalfPopulation; //!< Sum sad\haar for best mode decision top half population 2904 }; 2905 uint32_t Value; 2906 } DW30; 2907 union 2908 { 2909 //!< DWORD 31 2910 struct 2911 { 2912 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD(0, 15); //!< Sum top half population occurrences 2913 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31); //!< Sum bottom half population occurrences 2914 }; 2915 uint32_t Value; 2916 } DW31; 2917 union 2918 { 2919 struct 2920 { 2921 uint32_t ReadRequestBank0 : __CODEGEN_BITFIELD( 0, 23) ; //!< Read Request Bank 0 2922 uint32_t Reserved1048 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2923 }; 2924 uint32_t Value; 2925 } DW32; 2926 union 2927 { 2928 struct 2929 { 2930 uint32_t CacheMissCountBank0 : __CODEGEN_BITFIELD( 0, 23) ; //!< Cache Miss count Bank 0 2931 uint32_t Reserved1080 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2932 }; 2933 uint32_t Value; 2934 } DW33; 2935 union 2936 { 2937 struct 2938 { 2939 uint32_t ReadRequestBank1 : __CODEGEN_BITFIELD( 0, 23) ; //!< Read Request Bank 1 2940 uint32_t Reserved1112 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2941 }; 2942 uint32_t Value; 2943 } DW34; 2944 union 2945 { 2946 struct 2947 { 2948 uint32_t CacheMissCountBank1 : __CODEGEN_BITFIELD( 0, 23) ; //!< Cache Miss count Bank 1 2949 uint32_t Reserved1144 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2950 }; 2951 uint32_t Value; 2952 } DW35; 2953 union 2954 { 2955 struct 2956 { 2957 uint32_t ReadRequestBank2 : __CODEGEN_BITFIELD( 0, 23) ; //!< Read Request Bank 2 2958 uint32_t Reserved1176 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2959 }; 2960 uint32_t Value; 2961 } DW36; 2962 union 2963 { 2964 struct 2965 { 2966 uint32_t CacheMissCountBank2 : __CODEGEN_BITFIELD( 0, 23) ; //!< Cache Miss count Bank 2 2967 uint32_t Reserved1208 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2968 }; 2969 uint32_t Value; 2970 } DW37; 2971 union 2972 { 2973 struct 2974 { 2975 uint32_t ReadRequestBank3 : __CODEGEN_BITFIELD( 0, 23) ; //!< Read Request Bank 3 2976 uint32_t Reserved1240 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2977 }; 2978 uint32_t Value; 2979 } DW38; 2980 union 2981 { 2982 struct 2983 { 2984 uint32_t CacheMissCountBank3 : __CODEGEN_BITFIELD( 0, 23) ; //!< Cache Miss count Bank 3 2985 uint32_t Reserved1272 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2986 }; 2987 uint32_t Value; 2988 } DW39; 2989 union 2990 { 2991 struct 2992 { 2993 uint32_t ReadRequestBank4 : __CODEGEN_BITFIELD( 0, 23) ; //!< Read Request Bank 4 2994 uint32_t Reserved1304 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2995 }; 2996 uint32_t Value; 2997 } DW40; 2998 union 2999 { 3000 struct 3001 { 3002 uint32_t CacheMissCountBank4 : __CODEGEN_BITFIELD( 0, 23) ; //!< Cache Miss count Bank 4 3003 uint32_t Reserved1336 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 3004 }; 3005 uint32_t Value; 3006 } DW41; 3007 union 3008 { 3009 struct 3010 { 3011 uint32_t HimeRequestCount : __CODEGEN_BITFIELD( 0, 23) ; //!< HIME request count 3012 uint32_t Reserved1368 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 3013 }; 3014 uint32_t Value; 3015 } DW42; 3016 union 3017 { 3018 struct 3019 { 3020 uint32_t HimeRequestArbitraionLostCycleCount : __CODEGEN_BITFIELD( 0, 23) ; //!< HIME request arbitraion lost cycle count 3021 uint32_t Reserved1400 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 3022 }; 3023 uint32_t Value; 3024 } DW43; 3025 union 3026 { 3027 struct 3028 { 3029 uint32_t HimeRequestStallCount : __CODEGEN_BITFIELD( 0, 23) ; //!< HIME Request Stall count 3030 uint32_t Reserved1432 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 3031 }; 3032 uint32_t Value; 3033 } DW44; 3034 union 3035 { 3036 struct 3037 { 3038 uint64_t Reserved1440 ; //!< Reserved 3039 }; 3040 uint32_t Value[2]; 3041 } DW45_46; 3042 union 3043 { 3044 struct 3045 { 3046 uint32_t TotalReferenceReadCount ; //!< Total Reference Read count 3047 }; 3048 uint32_t Value; 3049 } DW47; 3050 uint32_t NumberofpixelsLumaCbCrValues150Each[256]; //!< NumberOfPixels Luma/Cb/Cr values [15:0] each 3051 3052 //! \name Local enumerations 3053 3054 //! \name Initializations 3055 3056 //! \brief Explicit member initialization function VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMDCmd::VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD3057 VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD() 3058 { 3059 MOS_ZeroMemory(this, sizeof(*this)); 3060 } 3061 3062 static const size_t dwSize = 48; 3063 static const size_t byteSize = 192; 3064 }; 3065 3066 //! 3067 //! \brief VDENC_HEVC_VP9_STREAMIN_STATE 3068 //! \details 3069 //! For the NumMergeCandidate paramaters [64x64/32x32/16x16/8x8], only the 3070 //! following configurations are valid. 3071 //! Normal Mode without force mv or force intra: 4321 [64x64 --> 16x16]. 3072 //! Speed Mode without force mv or force intra: 2220, 2110, 1210, 2200, 1110 3073 //! [64x64 --> 16x16]. 3074 //! 3075 struct VDENC_HEVC_VP9_STREAMIN_STATE_CMD 3076 { 3077 union 3078 { 3079 //!< DWORD 0 3080 struct 3081 { 3082 uint32_t Roi32X32016X1603 : __CODEGEN_BITFIELD(0, 7); //!< ROI 32x32_0 16x16_03 3083 uint32_t Maxtusize : __CODEGEN_BITFIELD(8, 9); //!< MaxTUSize 3084 uint32_t Maxcusize : __CODEGEN_BITFIELD(10, 11); //!< MaxCUSize 3085 uint32_t Numimepredictors : __CODEGEN_BITFIELD(12, 15); //!< NUMIMEPREDICTORS 3086 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 20); 3087 uint32_t Reserved21 : __CODEGEN_BITFIELD(21, 21); 3088 uint32_t PaletteDisable : __CODEGEN_BITFIELD(22, 22); 3089 uint32_t Reserved23 : __CODEGEN_BITFIELD(23, 23); 3090 uint32_t PuType32X32016X1603 : __CODEGEN_BITFIELD(24, 31); //!< PU Type 32x32_0 16x16_03 3091 }; 3092 uint32_t Value; 3093 } DW0; 3094 union 3095 { 3096 //!< DWORD 1 3097 struct 3098 { 3099 uint32_t ForceMvX32X32016X160 : __CODEGEN_BITFIELD(0, 15); //!< force_mv.x 32x32_0 16x16_0 3100 uint32_t ForceMvY32X32016X160 : __CODEGEN_BITFIELD(16, 31); //!< force_mv.y 32x32_0 16x16_0 3101 }; 3102 uint32_t Value; 3103 } DW1; 3104 union 3105 { 3106 //!< DWORD 2 3107 struct 3108 { 3109 uint32_t ForceMvX32X32016X161 : __CODEGEN_BITFIELD(0, 15); //!< force_mv.x 32x32_0 16x16_1 3110 uint32_t ForceMvY32X32016X161 : __CODEGEN_BITFIELD(16, 31); //!< force_mv.y 32x32_0 16x16_1 3111 }; 3112 uint32_t Value; 3113 } DW2; 3114 union 3115 { 3116 //!< DWORD 3 3117 struct 3118 { 3119 uint32_t ForceMvX32X32016X162 : __CODEGEN_BITFIELD(0, 15); //!< force_mv.x 32x32_0 16x16_2 3120 uint32_t ForceMvY32X32016X162 : __CODEGEN_BITFIELD(16, 31); //!< force_mv.y 32x32_0 16x16_2 3121 }; 3122 uint32_t Value; 3123 } DW3; 3124 union 3125 { 3126 //!< DWORD 4 3127 struct 3128 { 3129 uint32_t ForceMvX32X32016X163 : __CODEGEN_BITFIELD(0, 15); //!< force_mv.x 32x32_0 16x16_3 3130 uint32_t ForceMvY32X32016X163 : __CODEGEN_BITFIELD(16, 31); //!< force_mv.y 32x32_0 16x16_3 3131 }; 3132 uint32_t Value; 3133 } DW4; 3134 union 3135 { 3136 //!< DWORD 5 3137 struct 3138 { 3139 uint32_t Reserved160; //!< Reserved 3140 }; 3141 uint32_t Value; 3142 } DW5; 3143 union 3144 { 3145 //!< DWORD 6 3146 struct 3147 { 3148 uint32_t ForceMvRefidx32X32016X160 : __CODEGEN_BITFIELD(0, 3); //!< force_mv refidx 32x32_0 16x16_0 3149 uint32_t ForceMvRefidx32X32016X1613 : __CODEGEN_BITFIELD(4, 15); //!< force_mv refidx 32x32_0 16x16_1-3 3150 uint32_t Nummergecandidatecu8X8 : __CODEGEN_BITFIELD(16, 19); //!< NumMergeCandidateCU8x8 3151 uint32_t Nummergecandidatecu16X16 : __CODEGEN_BITFIELD(20, 23); //!< NumMergeCandidateCU16x16 3152 uint32_t Nummergecandidatecu32X32 : __CODEGEN_BITFIELD(24, 27); //!< NumMergeCandidateCU32x32 3153 uint32_t Nummergecandidatecu64X64 : __CODEGEN_BITFIELD(28, 31); //!< NumMergeCandidateCU64x64 3154 }; 3155 uint32_t Value; 3156 } DW6; 3157 union 3158 { 3159 //!< DWORD 7 3160 struct 3161 { 3162 uint32_t Segid32X32016X1603Vp9Only : __CODEGEN_BITFIELD(0, 15); //!< SegID 32x32_0 16x16_03 (VP9 only) 3163 uint32_t QpEn32X32016X1603 : __CODEGEN_BITFIELD(16, 19); //!< QP_En 32x32_0 16x16_03 3164 uint32_t SegidEnable : __CODEGEN_BITFIELD(20, 20); //!< SegID Enable 3165 uint32_t Reserved245 : __CODEGEN_BITFIELD(21, 22); //!< Reserved 3166 uint32_t ForceRefidEnable32X320 : __CODEGEN_BITFIELD(23, 23); //!< Force Refid Enable (32x32_0) 3167 uint32_t ImePredictorRefidSelect0332X320 : __CODEGEN_BITFIELD(24, 31); //!< IME predictor/refid Select0-3 32x32_0 3168 }; 3169 uint32_t Value; 3170 } DW7; 3171 union 3172 { 3173 //!< DWORD 8 3174 struct 3175 { 3176 uint32_t ImePredictor0X32X320 : __CODEGEN_BITFIELD(0, 15); //!< ime_predictor0.x 32x32_0 3177 uint32_t ImePredictor0Y32X320 : __CODEGEN_BITFIELD(16, 31); //!< ime_predictor0.y 32x32_0 3178 }; 3179 uint32_t Value; 3180 } DW8; 3181 union 3182 { 3183 //!< DWORD 9 3184 struct 3185 { 3186 uint32_t ImePredictor0X32X321 : __CODEGEN_BITFIELD(0, 15); //!< ime_predictor0.x 32x32_1 3187 uint32_t ImePredictor0Y32X321 : __CODEGEN_BITFIELD(16, 31); //!< ime_predictor0.y 32x32_1 3188 }; 3189 uint32_t Value; 3190 } DW9; 3191 union 3192 { 3193 //!< DWORD 10 3194 struct 3195 { 3196 uint32_t ImePredictor0X32X322 : __CODEGEN_BITFIELD(0, 15); //!< ime_predictor0.x 32x32_2 3197 uint32_t ImePredictor0Y32X322 : __CODEGEN_BITFIELD(16, 31); //!< ime_predictor0.y 32x32_2 3198 }; 3199 uint32_t Value; 3200 } DW10; 3201 union 3202 { 3203 //!< DWORD 11 3204 struct 3205 { 3206 uint32_t ImePredictor0X32X323 : __CODEGEN_BITFIELD(0, 15); //!< ime_predictor0.x 32x32_3 3207 uint32_t ImePredictor0Y32X323 : __CODEGEN_BITFIELD(16, 31); //!< ime_predictor0.y 32x32_3 3208 }; 3209 uint32_t Value; 3210 } DW11; 3211 union 3212 { 3213 //!< DWORD 12 3214 struct 3215 { 3216 uint32_t ImePredictor0Refidx32X320 : __CODEGEN_BITFIELD(0, 3); //!< ime_predictor0 refidx 32x32_0 3217 uint32_t ImePredictor13Refidx32X3213 : __CODEGEN_BITFIELD(4, 15); //!< ime_predictor1-3 refidx 32x32_1-3 3218 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 3219 }; 3220 uint32_t Value; 3221 } DW12; 3222 union 3223 { 3224 //!< DWORD 13 3225 struct 3226 { 3227 uint32_t Panicmodelcuthreshold : __CODEGEN_BITFIELD(0, 15); //!< PanicModeLCUThreshold 3228 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 3229 }; 3230 uint32_t Value; 3231 } DW13; 3232 union 3233 { 3234 //!< DWORD 14 3235 struct 3236 { 3237 uint32_t ForceQpValue16X160 : __CODEGEN_BITFIELD(0, 7); //!< Force QP Value 16x16_0 3238 uint32_t ForceQpValue16X161 : __CODEGEN_BITFIELD(8, 15); //!< Force QP Value 16x16_1 3239 uint32_t ForceQpValue16X162 : __CODEGEN_BITFIELD(16, 23); //!< Force QP Value 16x16_2 3240 uint32_t ForceQpValue16X163 : __CODEGEN_BITFIELD(24, 31); //!< Force QP Value 16x16_3 3241 }; 3242 uint32_t Value; 3243 } DW14; 3244 union 3245 { 3246 //!< DWORD 15 3247 struct 3248 { 3249 uint32_t Reserved480; //!< Reserved 3250 }; 3251 uint32_t Value; 3252 } DW15; 3253 3254 //! \name Local enumerations 3255 3256 //! \brief NUMIMEPREDICTORS 3257 //! \details 3258 //! <p>This parameter specifes the number of IME predictors to be processed 3259 //! in stage3 IME.</p> 3260 //! <p></p> 3261 enum NUMIMEPREDICTORS 3262 { 3263 NUMIMEPREDICTORS_UNNAMED0 = 0, //!< No additional details 3264 NUMIMEPREDICTORS_UNNAMED4 = 4, //!< No additional details 3265 NUMIMEPREDICTORS_UNNAMED8 = 8, //!< No additional details 3266 NUMIMEPREDICTORS_UNNAMED12 = 12, //!< No additional details 3267 }; 3268 3269 //! \name Initializations 3270 3271 //! \brief Explicit member initialization function VDENC_HEVC_VP9_STREAMIN_STATE_CMDCmd::VDENC_HEVC_VP9_STREAMIN_STATE_CMD3272 VDENC_HEVC_VP9_STREAMIN_STATE_CMD() 3273 { 3274 MOS_ZeroMemory(this, sizeof(*this)); 3275 3276 DW0.Numimepredictors = NUMIMEPREDICTORS_UNNAMED0; 3277 } 3278 3279 static const size_t dwSize = 16; 3280 static const size_t byteSize = 64; 3281 }; 3282 3283 //! 3284 //! \brief VDENC_Surface_State_Fields 3285 //! \details 3286 //! 3287 //! 3288 struct VDENC_Surface_State_Fields_CMD 3289 { 3290 union 3291 { 3292 //!< DWORD 0 3293 struct 3294 { 3295 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD(0, 1); //!< Cr(V)/Cb(U) Pixel Offset V Direction 3296 uint32_t SurfaceFormatByteSwizzle : __CODEGEN_BITFIELD(2, 2); //!< Surface Format Byte Swizzle 3297 uint32_t ColorSpaceSelection : __CODEGEN_BITFIELD(3, 3); //!< Color space selection 3298 uint32_t Width : __CODEGEN_BITFIELD(4, 17); //!< Width 3299 uint32_t Height : __CODEGEN_BITFIELD(18, 31); //!< Height 3300 }; 3301 uint32_t Value; 3302 } DW0; 3303 union 3304 { 3305 //!< DWORD 1 3306 struct 3307 { 3308 uint32_t TileMode : __CODEGEN_BITFIELD(0, 1); //!< TILE_MODE 3309 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD(2, 2); //!< HALF_PITCH_FOR_CHROMA 3310 uint32_t SurfacePitch : __CODEGEN_BITFIELD(3, 19); //!< Surface Pitch 3311 uint32_t ChromaDownsampleFilterControl : __CODEGEN_BITFIELD(20, 22); //!< Chroma Downsample Filter Control 3312 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 26); //!< Reserved 3313 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31); //!< Surface Format 3314 }; 3315 uint32_t Value; 3316 } DW1; 3317 union 3318 { 3319 //!< DWORD 2 3320 struct 3321 { 3322 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD(0, 14); //!< Y Offset for U(Cb) 3323 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 3324 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30); //!< X Offset for U(Cb) 3325 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 3326 }; 3327 uint32_t Value; 3328 } DW2; 3329 union 3330 { 3331 //!< DWORD 3 3332 struct 3333 { 3334 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(0, 15); //!< Y Offset for V(Cr) 3335 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28); //!< X Offset for V(Cr) 3336 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 3337 }; 3338 uint32_t Value; 3339 } DW3; 3340 3341 //! \name Local enumerations 3342 3343 //! \brief TILE_MODE 3344 enum TILE_MODE 3345 { 3346 TILE_LINEAR = 0, //!< Linear 3347 TILE_S = 1, //!< TileS(64K) 3348 TILE_X = 2, //!< Tile X 3349 TILE_F = 3, //!< Tile F 3350 }; 3351 3352 //! \brief HALF_PITCH_FOR_CHROMA 3353 //! \details 3354 //! (This field must be set to Disable.) This field indicates that the 3355 //! chroma plane(s) will use a pitch equal 3356 //! to half the value specified in the Surface Pitch field. This field 3357 //! is only used for PLANAR surface formats. 3358 //! This field is igored by VDEnc (unless we support YV12). 3359 enum HALF_PITCH_FOR_CHROMA 3360 { 3361 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< No additional details 3362 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< No additional details 3363 }; 3364 3365 //! \brief SURFACE_FORMAT 3366 //! \details 3367 //! Specifies the format of the surface. 3368 enum SURFACE_FORMAT 3369 { 3370 SURFACE_FORMAT_YUV422 = 0, //!< YUYV/YUY2 (8:8:8:8 MSB V0 Y1 U0 Y0) 3371 SURFACE_FORMAT_RGBA4444 = 1, //!< RGBA 32-bit 4:4:4:4 packed (8:8:8:8 MSB-X:B:G:R) 3372 SURFACE_FORMAT_YUV444 = 2, //!< YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-A:Y:U:V) 3373 SURFACE_FORMAT_Y8UNORM = 3, //!< No additional details 3374 SURFACE_FORMAT_PLANAR_420_8 = 4, //!< (NV12, IMC1,2,3,4, YV12) 3375 SURFACE_FORMAT_YCRCB_SWAPY_422 = 5, //!< UYVY (8:8:8:8 MSB Y1 V0 Y0 U0) 3376 SURFACE_FORMAT_YCRCB_SWAPUV_422 = 6, //!< YVYU (8:8:8:8 MSB U0 Y1 V0 Y0) 3377 SURFACE_FORMAT_YCRCB_SWAPUVY_422 = 7, //!< VYUY (8:8:8:8 MSB Y1 U0 Y0 V0) 3378 SURFACE_FORMAT_P010 = 8, //!< 10 - bit planar 420 (Tile - Y / Linear / Tile - X) 3379 SURFACE_FORMAT_RGBA_10_10_10_2 = 9, //!< Need to convert to YUV. 2 bits Alpha, 10 bits R 10 bits G 10 bits B 3380 SURFACE_FORMAT_Y410 = 10, //!< 10 bit 4:4:4 packed 3381 SURFACE_FORMAT_NV21 = 11, //!< 8-bit, same as NV12 but UV interleave is reversed 3382 SURFACE_FORMAT_P010_VARIANT = 12, //!< >8 bit planar 420 with MSB together and LSB at an offset in x direction 3383 }; 3384 3385 //! \name Initializations 3386 3387 //! \brief Explicit member initialization function VDENC_Surface_State_Fields_CMDCmd::VDENC_Surface_State_Fields_CMD3388 VDENC_Surface_State_Fields_CMD() 3389 { 3390 MOS_ZeroMemory(this, sizeof(*this)); 3391 3392 DW1.TileMode = TILE_F; 3393 DW1.HalfPitchForChroma = HALF_PITCH_FOR_CHROMA_DISABLE; 3394 } 3395 3396 static const size_t dwSize = 4; 3397 static const size_t byteSize = 16; 3398 }; 3399 3400 //! 3401 //! \brief VD_PIPELINE_FLUSH 3402 //! \details 3403 //! 3404 //! 3405 struct VD_PIPELINE_FLUSH_CMD 3406 { 3407 union 3408 { 3409 //!< DWORD 0 3410 struct 3411 { 3412 uint32_t DwordCountN : __CODEGEN_BITFIELD(0, 11); //!< DWORD_COUNT_N 3413 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3414 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 3415 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22); //!< SUBOPCODEA 3416 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_COMMAND_OPCODE 3417 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3418 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3419 }; 3420 uint32_t Value; 3421 } DW0; 3422 union 3423 { 3424 //!< DWORD 1 3425 struct 3426 { 3427 uint32_t HevcPipelineDone : __CODEGEN_BITFIELD(0, 0); //!< HEVC pipeline Done 3428 uint32_t VdencPipelineDone : __CODEGEN_BITFIELD(1, 1); //!< VD-ENC pipeline Done 3429 uint32_t MflPipelineDone : __CODEGEN_BITFIELD(2, 2); //!< MFL pipeline Done 3430 uint32_t MfxPipelineDone : __CODEGEN_BITFIELD(3, 3); //!< MFX pipeline Done 3431 uint32_t VdCommandMessageParserDone : __CODEGEN_BITFIELD(4, 4); //!< VD command/message parser Done 3432 uint32_t HucPipelineDone : __CODEGEN_BITFIELD(5, 5); //!< HUC pipeline Done 3433 uint32_t AvpPipelineDone : __CODEGEN_BITFIELD(6, 6); //!< AVP pipeline Done 3434 uint32_t VdaqmPipelineDone : __CODEGEN_BITFIELD(7, 7); 3435 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 3436 uint32_t HevcPipelineCommandFlush : __CODEGEN_BITFIELD(16, 16); //!< HEVC pipeline command flush 3437 uint32_t VdencPipelineCommandFlush : __CODEGEN_BITFIELD(17, 17); //!< VD-ENC pipeline command flush 3438 uint32_t MflPipelineCommandFlush : __CODEGEN_BITFIELD(18, 18); //!< MFL pipeline command flush 3439 uint32_t MfxPipelineCommandFlush : __CODEGEN_BITFIELD(19, 19); //!< MFX pipeline command flush 3440 uint32_t HucPipelineCommandFlush : __CODEGEN_BITFIELD(20, 20); //!< HUC pipeline command flush 3441 uint32_t AvpPipelineCommandFlush : __CODEGEN_BITFIELD(21, 21); //!< AVP pipeline command flush 3442 uint32_t VdaqmPipelineCommandFlush : __CODEGEN_BITFIELD(22, 22); 3443 uint32_t Reserved54 : __CODEGEN_BITFIELD(23, 31); //!< Reserved 3444 }; 3445 uint32_t Value; 3446 } DW1; 3447 3448 //! \name Local enumerations 3449 3450 //! \brief DWORD_COUNT_N 3451 //! \details 3452 //! Total Length - 2 3453 enum DWORD_COUNT_N 3454 { 3455 DWORD_COUNT_N_EXCLUDESDWORD_0 = 0, //!< No additional details 3456 }; 3457 3458 enum SUBOPCODEB 3459 { 3460 SUBOPCODEB_UNNAMED0 = 0, //!< No additional details 3461 }; 3462 3463 enum SUBOPCODEA 3464 { 3465 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 3466 }; 3467 3468 enum MEDIA_COMMAND_OPCODE 3469 { 3470 MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND = 15, //!< No additional details 3471 }; 3472 3473 enum PIPELINE 3474 { 3475 PIPELINE_MEDIA = 2, //!< No additional details 3476 }; 3477 3478 enum COMMAND_TYPE 3479 { 3480 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3481 }; 3482 3483 //! \name Initializations 3484 3485 //! \brief Explicit member initialization function VD_PIPELINE_FLUSH_CMDCmd::VD_PIPELINE_FLUSH_CMD3486 VD_PIPELINE_FLUSH_CMD() 3487 { 3488 MOS_ZeroMemory(this, sizeof(*this)); 3489 3490 DW0.DwordCountN = __CODEGEN_OP_LENGTH(dwSize); 3491 DW0.Subopcodeb = SUBOPCODEB_UNNAMED0; 3492 DW0.Subopcodea = SUBOPCODEA_UNNAMED0; 3493 DW0.MediaCommandOpcode = MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND; 3494 DW0.Pipeline = PIPELINE_MEDIA; 3495 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3496 } 3497 3498 static const size_t dwSize = 2; 3499 static const size_t byteSize = 8; 3500 }; 3501 3502 //! 3503 //! \brief VDENC_WEIGHTSOFFSETS_STATE 3504 //! \details 3505 //! 3506 //! 3507 struct VDENC_WEIGHTSOFFSETS_STATE_CMD 3508 { 3509 union 3510 { 3511 //!< DWORD 0 3512 struct 3513 { 3514 uint32_t DwLength : __CODEGEN_BITFIELD(0, 11); //!< DW_LENGTH 3515 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3516 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3517 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3518 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3519 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3520 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3521 }; 3522 uint32_t Value; 3523 } DW0; 3524 union 3525 { 3526 //!< DWORD 1 3527 struct 3528 { 3529 uint32_t WeightsForwardReference0 : __CODEGEN_BITFIELD(0, 7); //!< Weights Forward Reference0 3530 uint32_t OffsetForwardReference0 : __CODEGEN_BITFIELD(8, 15); //!< Offset Forward Reference0 3531 uint32_t WeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23); //!< Weights Forward Reference1 3532 uint32_t OffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31); //!< Offset Forward Reference1 3533 }; 3534 uint32_t Value; 3535 } DW1; 3536 union 3537 { 3538 //!< DWORD 2 3539 struct 3540 { 3541 uint32_t WeightsForwardReference2 : __CODEGEN_BITFIELD(0, 7); //!< Weights Forward Reference2 3542 uint32_t OffsetForwardReference2 : __CODEGEN_BITFIELD(8, 15); //!< Offset Forward Reference2 3543 uint32_t WeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23); //!< Weights Backward Reference0 3544 uint32_t OffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31); //!< Offset Backward Reference0 3545 }; 3546 uint32_t Value; 3547 } DW2; 3548 union 3549 { 3550 //!< DWORD 3 3551 struct 3552 { 3553 uint32_t CbWeightsForwardReference0 : __CODEGEN_BITFIELD(0, 7); //!< Cb Weights Forward Reference0 3554 uint32_t CbOffsetForwardReference0 : __CODEGEN_BITFIELD(8, 15); //!< Cb Offset Forward Reference0 3555 uint32_t CbWeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23); //!< Cb Weights Forward Reference1 3556 uint32_t CbOffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31); //!< Cb Offset Forward Reference1 3557 }; 3558 uint32_t Value; 3559 } DW3; 3560 union 3561 { 3562 //!< DWORD 4 3563 struct 3564 { 3565 uint32_t CbWeightsForwardReference2 : __CODEGEN_BITFIELD(0, 7); //!< Cb Weights Forward Reference2 3566 uint32_t CbOffsetForwardReference2 : __CODEGEN_BITFIELD(8, 15); //!< Cb Offset Forward Reference2 3567 uint32_t CbWeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23); //!< Cb Weights Backward Reference0 3568 uint32_t CbOffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31); //!< Cb Offset Backward Reference0 3569 }; 3570 uint32_t Value; 3571 } DW4; 3572 union 3573 { 3574 //!< DWORD 5 3575 struct 3576 { 3577 uint32_t CrWeightsForwardReference0 : __CODEGEN_BITFIELD(0, 7); //!< Cr Weights Forward Reference0 3578 uint32_t CrOffsetForwardReference0 : __CODEGEN_BITFIELD(8, 15); //!< Cr Offset Forward Reference0 3579 uint32_t CrWeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23); //!< Cr Weights Forward Reference1 3580 uint32_t CrOffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31); //!< Cr Offset Forward Reference1 3581 }; 3582 uint32_t Value; 3583 } DW5; 3584 union 3585 { 3586 //!< DWORD 6 3587 struct 3588 { 3589 uint32_t CrWeightsForwardReference2 : __CODEGEN_BITFIELD(0, 7); //!< Cr Weights Forward Reference2 3590 uint32_t CrOffsetForwardReference2 : __CODEGEN_BITFIELD(8, 15); //!< Cr Offset Forward Reference2 3591 uint32_t CrWeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23); //!< Cr Weights Backward Reference0 3592 uint32_t CrOffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31); //!< Cr Offset Backward Reference0 3593 }; 3594 uint32_t Value; 3595 } DW6; 3596 3597 //! \name Local enumerations 3598 3599 //! \brief DW_LENGTH 3600 //! \details 3601 //! Total Length - 2 3602 enum DW_LENGTH 3603 { 3604 DW_LENGTH_DWORDCOUNTN = 5, //!< Excludes DWord (0,1) 3605 }; 3606 3607 enum SUBOPB 3608 { 3609 SUBOPB_VDENCAVCWEIGHTSOFFSETSTATE = 8, //!< No additional details 3610 }; 3611 3612 enum SUBOPA 3613 { 3614 SUBOPA_UNNAMED0 = 0, //!< No additional details 3615 }; 3616 3617 enum OPCODE 3618 { 3619 OPCODE_VDENCPIPE = 1, //!< No additional details 3620 }; 3621 3622 enum PIPELINE 3623 { 3624 PIPELINE_MFXCOMMON = 2, //!< No additional details 3625 }; 3626 3627 enum COMMAND_TYPE 3628 { 3629 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3630 }; 3631 3632 //! \name Initializations 3633 3634 //! \brief Explicit member initialization function VDENC_WEIGHTSOFFSETS_STATE_CMDCmd::VDENC_WEIGHTSOFFSETS_STATE_CMD3635 VDENC_WEIGHTSOFFSETS_STATE_CMD() 3636 { 3637 MOS_ZeroMemory(this, sizeof(*this)); 3638 3639 DW0.DwLength = __CODEGEN_OP_LENGTH(dwSize); 3640 DW0.Subopb = SUBOPB_VDENCAVCWEIGHTSOFFSETSTATE; 3641 DW0.Subopa = SUBOPA_UNNAMED0; 3642 DW0.Opcode = OPCODE_VDENCPIPE; 3643 DW0.Pipeline = PIPELINE_MFXCOMMON; 3644 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3645 3646 DW1.WeightsForwardReference0 = 1; 3647 DW1.OffsetForwardReference0 = 0; 3648 DW1.WeightsForwardReference1 = 1; 3649 DW1.OffsetForwardReference1 = 0; 3650 3651 DW2.WeightsForwardReference2 = 1; 3652 DW2.OffsetForwardReference2 = 0; 3653 DW2.WeightsBackwardReference0 = 1; 3654 DW2.OffsetBackwardReference0 = 0; 3655 } 3656 3657 static const size_t dwSize = 7; 3658 static const size_t byteSize = 28; 3659 }; 3660 3661 //! 3662 //! \brief VDENC_DS_REF_SURFACE_STATE 3663 //! \details 3664 //! This command specifies the surface state parameters for the downscaled 3665 //! reference surfaces. 3666 //! 3667 struct VDENC_DS_REF_SURFACE_STATE_CMD 3668 { 3669 union 3670 { 3671 //!< DWORD 0 3672 struct 3673 { 3674 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3675 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3676 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3677 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3678 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3679 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3680 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3681 }; 3682 uint32_t Value; 3683 } DW0; 3684 union 3685 { 3686 //!< DWORD 1 3687 struct 3688 { 3689 uint32_t Reserved32; //!< Reserved 3690 }; 3691 uint32_t Value; 3692 } DW1; 3693 VDENC_Surface_State_Fields_CMD Dwords25; //!< Dwords 2..5 3694 VDENC_Surface_State_Fields_CMD Dwords69; //!< Dwords 6..9 3695 3696 //! \name Local enumerations 3697 3698 enum SUBOPB 3699 { 3700 SUBOPB_VDENCDSREFSURFACESTATE = 3, //!< No additional details 3701 }; 3702 3703 enum SUBOPA 3704 { 3705 SUBOPA_UNNAMED0 = 0, //!< No additional details 3706 }; 3707 3708 enum OPCODE 3709 { 3710 OPCODE_VDENCPIPE = 1, //!< No additional details 3711 }; 3712 3713 enum PIPELINE 3714 { 3715 PIPELINE_MFXCOMMON = 2, //!< No additional details 3716 }; 3717 3718 enum COMMAND_TYPE 3719 { 3720 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3721 }; 3722 3723 //! \name Initializations 3724 3725 //! \brief Explicit member initialization function VDENC_DS_REF_SURFACE_STATE_CMDCmd::VDENC_DS_REF_SURFACE_STATE_CMD3726 VDENC_DS_REF_SURFACE_STATE_CMD() 3727 { 3728 MOS_ZeroMemory(this, sizeof(*this)); 3729 3730 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 3731 DW0.Subopb = SUBOPB_VDENCDSREFSURFACESTATE; 3732 DW0.Subopa = SUBOPA_UNNAMED0; 3733 DW0.Opcode = OPCODE_VDENCPIPE; 3734 DW0.Pipeline = PIPELINE_MFXCOMMON; 3735 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3736 } 3737 3738 static const size_t dwSize = 10; 3739 static const size_t byteSize = 40; 3740 }; 3741 3742 //! 3743 //! \brief VDENC_PIPE_BUF_ADDR_STATE 3744 //! \details 3745 //! This state command provides the memory base addresses for all row 3746 //! stores, Streamin/StreamOut, DMV buffer along with the uncompressed 3747 //! source, reference pictures and downscaled reference pictures required by 3748 //! the VDENC pipeline. All reference pixel surfaces in the Encoder are 3749 //! programmed with the same surface state (NV12 and TileY format), except 3750 //! each has its own frame buffer base address. Same holds true for the 3751 //! down-scaled reference pictures too. In the tile format, there is no need 3752 //! to provide buffer offset for each slice; since from each MB address, the 3753 //! hardware can calculated the corresponding memory location within the 3754 //! frame buffer directly. VDEnc supports 3 Downscaled reference frames ( 2 3755 //! fwd, 1 bwd) and 4 normal reference frames ( 3 fwd, 1 bwd). The driver 3756 //! will sort out the base address from the DPB table and populate the base 3757 //! addresses that map to the corresponding reference index for both DS 3758 //! references and normal reference frames. Each of the individual DS ref/ 3759 //! Normal ref frames have their own MOCS DW that corresponds to the 3760 //! respective base address. The only thing that is different in the MOCS DW 3761 //! amongst the DS reference frames is the MMCD controls (specified in bits 3762 //! [10:9] of the MOCS DW). Driver needs to ensure that the other bits need 3763 //! to be the same across the different DS ref frames. The same is 3764 //! applicable for the normal reference frames. 3765 //! 3766 struct VDENC_PIPE_BUF_ADDR_STATE_CMD 3767 { 3768 union 3769 { 3770 //!< DWORD 0 3771 struct 3772 { 3773 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3774 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3775 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3776 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3777 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3778 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3779 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3780 }; 3781 uint32_t Value; 3782 } DW0; 3783 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef0; //!< DS FWD REF0 3784 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef1; //!< DS FWD REF1 3785 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef0; //!< DS BWD REF0 3786 VDENC_Original_Uncompressed_Picture_CMD OriginalUncompressedPicture; //!< Original Uncompressed Picture 3787 VDENC_Streamin_Data_Picture_CMD StreaminDataPicture; //!< Streamin Data Picture 3788 VDENC_Row_Store_Scratch_Buffer_Picture_CMD RowStoreScratchBuffer; //!< Row Store Scratch Buffer 3789 VDENC_Colocated_MV_Picture_CMD ColocatedMv; //!< Colocated MV 3790 VDENC_Reference_Picture_CMD FwdRef0; //!< FWD REF0 3791 VDENC_Reference_Picture_CMD FwdRef1; //!< FWD REF1 3792 VDENC_Reference_Picture_CMD FwdRef2; //!< FWD REF2 3793 VDENC_Reference_Picture_CMD BwdRef0; //!< BWD REF0 3794 VDENC_Statistics_Streamout_CMD VdencStatisticsStreamout; //!< VDEnc Statistics Streamout 3795 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef04X; //!< DS FWD REF0 4X 3796 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef14X; //!< DS FWD REF1 4X 3797 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef04X; //!< DS BWD REF1 4X 3798 VDENC_Statistics_Streamout_CMD VdencLcuPakObjCmdBuffer; //!< VDEnc LCU PAK OBJ CMD Buffer 3799 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurfaceStage1; //!< Scaled Reference Surface (8X for HEVC/VP9, 4X for AVC) 3800 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurfaceStage2; //!< Scaled Reference Surface (8X for HEVC/VP9, not used for AVC) 3801 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreaminBuffer; //!< VP9 Segmentation Map Streamin Buffer 3802 VDENC_Statistics_Streamout_CMD Vp9SegmentationMapStreamoutBuffer; //!< VP9 Segmentation Map Streamout Buffer 3803 union 3804 { 3805 //!< DWORD 61 3806 struct 3807 { 3808 uint32_t WeightsHistogramStreamoutOffset; //!< Weights Histogram Streamout offset 3809 }; 3810 uint32_t Value; 3811 } DW61; 3812 VDENC_Row_Store_Scratch_Buffer_Picture_CMD VdencTileRowStoreBuffer; //!< VDENC Tile Row store Buffer 3813 VDENC_Statistics_Streamout_CMD VdencCumulativeCuCountStreamoutSurface; //!< VDENC Cumulative CU count streamout surface 3814 VDENC_Statistics_Streamout_CMD VdencPaletteModeStreamoutSurface; //!< VDENC Palette Mode streamout surface 3815 VDENC_Statistics_Streamout_CMD VDENC_PIPE_BUF_ADDR_STATE_DW71_73; 3816 VDENC_Statistics_Streamout_CMD VDENC_PIPE_BUF_ADDR_STATE_DW74_76; 3817 VDENC_Row_Store_Scratch_Buffer_Picture_CMD IntraPredictionRowstoreBaseAddress; //!< Intra Prediction RowStore Base Address 3818 VDENC_Statistics_Streamout_CMD VDENC_PIPE_BUF_ADDR_STATE_DW80_82; 3819 VDENC_Colocated_MV_Picture_CMD ColocatedMvAvcWriteBuffer; //!< DW83..85, Colocated MV AVC Write Buffer 3820 VDENC_Down_Scaled_Reference_Picture_CMD Additional4xDsFwdRef; //!< DW86..88, Additional x4 DS FWD REF 3821 3822 //! \name Local enumerations 3823 3824 enum SUBOPB 3825 { 3826 SUBOPB_VDENCPIPEBUFADDRSTATE = 4, //!< No additional details 3827 }; 3828 3829 enum SUBOPA 3830 { 3831 SUBOPA_UNNAMED0 = 0, //!< No additional details 3832 }; 3833 3834 enum OPCODE 3835 { 3836 OPCODE_VDENCPIPE = 1, //!< No additional details 3837 }; 3838 3839 enum PIPELINE 3840 { 3841 PIPELINE_MFXCOMMON = 2, //!< No additional details 3842 }; 3843 3844 enum COMMAND_TYPE 3845 { 3846 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3847 }; 3848 3849 //! \name Initializations 3850 3851 //! \brief Explicit member initialization function VDENC_PIPE_BUF_ADDR_STATE_CMDCmd::VDENC_PIPE_BUF_ADDR_STATE_CMD3852 VDENC_PIPE_BUF_ADDR_STATE_CMD() 3853 { 3854 MOS_ZeroMemory(this, sizeof(*this)); 3855 3856 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 3857 DW0.Subopb = SUBOPB_VDENCPIPEBUFADDRSTATE; 3858 DW0.Subopa = SUBOPA_UNNAMED0; 3859 DW0.Opcode = OPCODE_VDENCPIPE; 3860 DW0.Pipeline = PIPELINE_MFXCOMMON; 3861 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3862 } 3863 3864 static const size_t dwSize = 89; 3865 static const size_t byteSize = 356; 3866 }; 3867 3868 //! 3869 //! \brief VDENC_PIPE_MODE_SELECT 3870 //! \details 3871 //! Specifies which codec and hardware module is being used to encode/decode 3872 //! the video data, on a per-frame basis. The VDENC_PIPE_MODE_SELECT command 3873 //! specifies which codec and hardware module is being used to encode/decode 3874 //! the video data, on a per-frame basis. It also configures the hardware 3875 //! pipeline according to the active encoder/decoder operating mode for 3876 //! encoding/decoding the current picture. 3877 //! 3878 struct VDENC_PIPE_MODE_SELECT_CMD 3879 { 3880 union 3881 { 3882 //!< DWORD 0 3883 struct 3884 { 3885 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3886 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3887 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3888 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3889 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3890 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3891 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3892 }; 3893 uint32_t Value; 3894 } DW0; 3895 union 3896 { 3897 //!< DWORD 1 3898 struct 3899 { 3900 uint32_t StandardSelect : __CODEGEN_BITFIELD(0, 3); //!< STANDARD_SELECT 3901 uint32_t ScalabilityMode : __CODEGEN_BITFIELD(4, 4); //!< Scalability Mode 3902 uint32_t FrameStatisticsStreamOutEnable : __CODEGEN_BITFIELD(5, 5); //!< FRAME_STATISTICS_STREAM_OUT_ENABLE 3903 uint32_t VdencPakObjCmdStreamOutEnable : __CODEGEN_BITFIELD(6, 6); //!< VDEnc PAK_OBJ_CMD Stream-Out Enable 3904 uint32_t TlbPrefetchEnable : __CODEGEN_BITFIELD(7, 7); //!< TLB_PREFETCH_ENABLE 3905 uint32_t PakThresholdCheckEnable : __CODEGEN_BITFIELD(8, 8); //!< PAK_THRESHOLD_CHECK_ENABLE 3906 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD(9, 9); //!< VDENC_STREAM_IN_ENABLE 3907 uint32_t Downscaled8XWriteDisable : __CODEGEN_BITFIELD(10, 10); //!< DownScaled 8x write Disable 3908 uint32_t Downscaled4XWriteDisable : __CODEGEN_BITFIELD(11, 11); //!< DownScaled 4x write Disable 3909 uint32_t BitDepth : __CODEGEN_BITFIELD(12, 14); //!< BIT_DEPTH 3910 uint32_t PakChromaSubSamplingType : __CODEGEN_BITFIELD(15, 16); //!< PAK_CHROMA_SUB_SAMPLING_TYPE 3911 uint32_t OutputRangeControlAfterColorSpaceConversion : __CODEGEN_BITFIELD(17, 17); //!< output range control after color space conversion 3912 uint32_t IsRandomAccess : __CODEGEN_BITFIELD(18, 18); //!< Is random access B frame or not 3913 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 19); //!< Reserved 3914 uint32_t RgbEncodingEnable : __CODEGEN_BITFIELD(20, 20); //!< RGB encoding enable 3915 uint32_t PrimaryChannelSelectionForRgbEncoding : __CODEGEN_BITFIELD(21, 22); //!< PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3916 uint32_t FirstSecondaryChannelSelectionForRgbEncoding : __CODEGEN_BITFIELD(23, 24); //!< FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3917 uint32_t TileReplayEnable : __CODEGEN_BITFIELD(25, 25); //!< Tile replay enable 3918 uint32_t StreamingBufferConfig : __CODEGEN_BITFIELD(26, 27); //!< Streaming buffer config 3919 uint32_t Reserved58 : __CODEGEN_BITFIELD(28, 30); //!< Reserved 3920 uint32_t DisableSpeedModeFetchOptimization : __CODEGEN_BITFIELD(31, 31); //!< Disable Speed Mode fetch optimization 3921 }; 3922 uint32_t Value; 3923 } DW1; 3924 union 3925 { 3926 //!< DWORD 2 3927 struct 3928 { 3929 uint32_t HmeRegionPreFetchenable : __CODEGEN_BITFIELD(0, 0); //!< HME_REGION_PRE_FETCHENABLE 3930 uint32_t Topprefetchenablemode : __CODEGEN_BITFIELD(1, 2); //!< TOPPREFETCHENABLEMODE 3931 uint32_t LeftpreFetchatwraparound : __CODEGEN_BITFIELD(3, 3); //!< LEFTPRE_FETCHATWRAPAROUND 3932 uint32_t Verticalshift32Minus1 : __CODEGEN_BITFIELD(4, 7); //!< VERTICALSHIFT32MINUS1 3933 uint32_t Hzshift32Minus1 : __CODEGEN_BITFIELD(8, 11); //!< HZSHIFT32MINUS1 3934 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3935 uint32_t NumVerticalReqMinus1 : __CODEGEN_BITFIELD(16, 19); //!< NUMVERTICALREQMINUS1 3936 uint32_t Numhzreqminus1 : __CODEGEN_BITFIELD(20, 23); //!< NUMHZREQMINUS1 3937 uint32_t PreFetchOffsetForReferenceIn16PixelIncrement : __CODEGEN_BITFIELD(24, 27); //!< PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT 3938 uint32_t Reserved92 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 3939 }; 3940 uint32_t Value; 3941 } DW2; 3942 union 3943 { 3944 //!< DWORD 3 3945 struct 3946 { 3947 uint32_t SourceLumaPackedDataTlbPreFetchenable : __CODEGEN_BITFIELD(0, 0); //!< SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 3948 uint32_t SourceChromaTlbPreFetchenable : __CODEGEN_BITFIELD(1, 1); //!< SOURCE_CHROMA_TLB_PRE_FETCHENABLE 3949 uint32_t Reserved98 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 3950 uint32_t Verticalshift32Minus1Src : __CODEGEN_BITFIELD(4, 7); //!< VERTICALSHIFT32MINUS1SRC 3951 uint32_t Hzshift32Minus1Src : __CODEGEN_BITFIELD(8, 11); //!< HZSHIFT32MINUS1SRC 3952 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3953 uint32_t Numverticalreqminus1Src : __CODEGEN_BITFIELD(16, 19); //!< NUMVERTICALREQMINUS1SRC 3954 uint32_t Numhzreqminus1Src : __CODEGEN_BITFIELD(20, 23); //!< NUMHZREQMINUS1SRC 3955 uint32_t PreFetchoffsetforsource : __CODEGEN_BITFIELD(24, 27); //!< PRE_FETCHOFFSETFORSOURCE 3956 uint32_t VDENC_PIPE_MODE_SELECT_DW3_BIT28 : __CODEGEN_BITFIELD(28, 31); 3957 }; 3958 uint32_t Value; 3959 } DW3; 3960 union 3961 { 3962 struct 3963 { 3964 uint32_t Debugtilepassnum : __CODEGEN_BITFIELD(0, 3); //!< DebugTilePassNum 3965 uint32_t Debugtilenum : __CODEGEN_BITFIELD(4, 11); //!< DebugTileNum 3966 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT12 : __CODEGEN_BITFIELD(12, 14); 3967 uint32_t Reserved_143 : __CODEGEN_BITFIELD(15, 15); 3968 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT16 : __CODEGEN_BITFIELD(16, 17); 3969 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT18 : __CODEGEN_BITFIELD(18, 19); 3970 uint32_t Reserved_148 : __CODEGEN_BITFIELD(20, 20); 3971 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT21 : __CODEGEN_BITFIELD(21, 21); 3972 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT22 : __CODEGEN_BITFIELD(22, 23); 3973 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT24 : __CODEGEN_BITFIELD(24, 25); 3974 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT26 : __CODEGEN_BITFIELD(26, 27); 3975 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT28 : __CODEGEN_BITFIELD(28, 29); 3976 uint32_t Reserved_158 : __CODEGEN_BITFIELD(30, 31); 3977 }; 3978 uint32_t Value; 3979 } DW4; 3980 union 3981 { 3982 struct 3983 { 3984 uint32_t FrameNumber : __CODEGEN_BITFIELD(0, 3); //!< Frame Number 3985 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT4 : __CODEGEN_BITFIELD(4, 5); 3986 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT6 : __CODEGEN_BITFIELD(6, 7); 3987 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT8 : __CODEGEN_BITFIELD(8, 8); 3988 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT9 : __CODEGEN_BITFIELD(9, 9); 3989 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT10 : __CODEGEN_BITFIELD(10, 10); 3990 uint32_t CaptureMode : __CODEGEN_BITFIELD(11, 12); //!< CAPTURE_MODE 3991 uint32_t ParallelCaptureAndEncodeSessionId : __CODEGEN_BITFIELD(13, 15); //!< PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID 3992 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT16 : __CODEGEN_BITFIELD(16, 16); 3993 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT17 : __CODEGEN_BITFIELD(17, 17); 3994 uint32_t Reserved185 : __CODEGEN_BITFIELD(18, 23); //!< Reserved 3995 uint32_t TailPointerReadFrequency : __CODEGEN_BITFIELD(24, 31); //!< Tail pointer read frequency 3996 }; 3997 uint32_t Value; 3998 } DW5; 3999 union 4000 { 4001 struct 4002 { 4003 uint32_t FastPassEn : __CODEGEN_BITFIELD(0, 0); 4004 uint32_t FastPassScale : __CODEGEN_BITFIELD(1, 1); 4005 uint32_t DownScaleType : __CODEGEN_BITFIELD(2, 2); 4006 uint32_t Researved186 : __CODEGEN_BITFIELD(3, 31); 4007 }; 4008 uint32_t Value; 4009 } DW6; 4010 4011 //! \name Local enumerations 4012 4013 enum SUBOPB 4014 { 4015 SUBOPB_VDENCPIPEMODESELECT = 0, //!< No additional details 4016 }; 4017 4018 enum SUBOPA 4019 { 4020 SUBOPA_UNNAMED0 = 0, //!< No additional details 4021 }; 4022 4023 enum OPCODE 4024 { 4025 OPCODE_VDENCPIPE = 1, //!< No additional details 4026 }; 4027 4028 enum PIPELINE 4029 { 4030 PIPELINE_MFXCOMMON = 2, //!< No additional details 4031 }; 4032 4033 enum COMMAND_TYPE 4034 { 4035 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4036 }; 4037 4038 enum STANDARD_SELECT 4039 { 4040 STANDARD_SELECT_AVC = 2, //!< No additional details 4041 }; 4042 4043 //! \brief FRAME_STATISTICS_STREAM_OUT_ENABLE 4044 //! \details 4045 //! This field controls whether the frame statistics stream-out is enabled. 4046 enum FRAME_STATISTICS_STREAM_OUT_ENABLE 4047 { 4048 FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 4049 FRAME_STATISTICS_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 4050 }; 4051 4052 //! \brief TLB_PREFETCH_ENABLE 4053 //! \details 4054 //! This field controls whether TLB prefetching is enabled. 4055 enum TLB_PREFETCH_ENABLE 4056 { 4057 TLB_PREFETCH_ENABLE_DISABLE = 0, //!< No additional details 4058 TLB_PREFETCH_ENABLE_ENABLE = 1, //!< No additional details 4059 }; 4060 4061 //! \brief PAK_THRESHOLD_CHECK_ENABLE 4062 //! \details 4063 //! For AVC standard: This field controls whether VDEnc will check the 4064 //! PAK indicator for bits overflow and terminates the slice. This mode is 4065 //! called Dynamic Slice Mode. When this field is disabled, VDEnc is in 4066 //! Static Slice Mode. It uses the driver programmed Slice Macroblock Height 4067 //! Minus One to terminate the slice. This feature is also referred to as 4068 //! slice size conformance. 4069 //! For HEVC standard: This bit is used to enable dynamic slice size 4070 //! control. 4071 enum PAK_THRESHOLD_CHECK_ENABLE 4072 { 4073 PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE = 0, //!< No additional details 4074 PAK_THRESHOLD_CHECK_ENABLE_ENABLEDYNAMICSLICEMODE = 1, //!< No additional details 4075 }; 4076 4077 //! \brief VDENC_STREAM_IN_ENABLE 4078 //! \details 4079 //! This field controls whether VDEnc will read the stream-in surface 4080 //! that is programmed. Currently the stream-in surface has MB level QP, 4081 //! ROI, predictors and MaxSize/TargetSizeinWordsMB parameters. The 4082 //! individual enables for each of the fields is programmed in the 4083 //! VDENC_IMG_STATE. 4084 //! (ROI_Enable, Fwd/Predictor0 MV Enable, Bwd/Predictor1 MV Enable, MB 4085 //! Level QP Enable, TargetSizeinWordsMB/MaxSizeinWordsMB Enable). 4086 //! This bit is valid only in AVC mode. In HEVC / VP9 mode this bit is 4087 //! reserved and should be set to zero. 4088 enum VDENC_STREAM_IN_ENABLE 4089 { 4090 VDENC_STREAM_IN_ENABLE_DISABLE = 0, //!< No additional details 4091 VDENC_STREAM_IN_ENABLE_ENABLE = 1, //!< No additional details 4092 }; 4093 4094 //! \brief BIT_DEPTH 4095 //! \details 4096 //! This parameter indicates the PAK bit depth. The valid values for this 4097 //! are 0 / 2 in HEVC / VP9 standard. In AVC standard this field should be 4098 //! set to 0. 4099 enum BIT_DEPTH 4100 { 4101 BIT_DEPTH_8BIT = 0, //!< No additional details 4102 BIT_DEPTH_10BIT = 2, //!< No additional details 4103 BIT_DEPTH_12BIT = 3, //!< No additional details 4104 }; 4105 4106 //! \brief PAK_CHROMA_SUB_SAMPLING_TYPE 4107 //! \details 4108 //! This field is applicable only in HEVC and VP9. In AVC, this field is ignored. 4109 enum PAK_CHROMA_SUB_SAMPLING_TYPE 4110 { 4111 PAK_CHROMA_SUB_SAMPLING_TYPE_420 = 1, //!< Used for Main8 and Main10 HEVC, VP9 profile0, AVC. 4112 PAK_CHROMA_SUB_SAMPLING_TYPE_4_4_4 = 3, //!< HEVC RExt 444, VP9 444 profiles. 4113 }; 4114 4115 //! \brief PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 4116 //! \details 4117 //! In RGB encoding, any one of the channel could be primary. This field is 4118 //! used for selcting primary channel 4119 enum PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 4120 { 4121 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED0 = 0, //!< Channel R is primary channel 4122 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1 = 1, //!< Channel G is primary channel. 4123 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2 = 2, //!< Channel B is primary channel 4124 }; 4125 4126 //! \brief FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 4127 //! \details 4128 //! In RGB encoding, any one of the channel could be primary. This field is 4129 //! used for selcting primary channel 4130 enum FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 4131 { 4132 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED0 = 0, //!< Channel R is first secondary channel 4133 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1 = 1, //!< Channel G is first secondary channel 4134 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2 = 2, //!< Channel B is first secondary channel. 4135 }; 4136 4137 //! \brief HME_REGION_PRE_FETCHENABLE 4138 //! \details 4139 //! When this bit is set, for all reference frames HME region pages are pre-fetched. 4140 enum HME_REGION_PRE_FETCHENABLE 4141 { 4142 HME_REGION_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 4143 HME_REGION_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 4144 }; 4145 4146 //! \brief TOPPREFETCHENABLEMODE 4147 //! \details 4148 //! Top Pre-fetch enable Mode 4149 enum TOPPREFETCHENABLEMODE 4150 { 4151 TOPPREFETCHENABLEMODE_UNNAMED0 = 0, //!< No additional details 4152 TOPPREFETCHENABLEMODE_UNNAMED1 = 1, //!< No additional details 4153 }; 4154 4155 //! \brief LEFTPRE_FETCHATWRAPAROUND 4156 //! \details 4157 //! Left pre-fetch enabled on wraparound 4158 enum LEFTPRE_FETCHATWRAPAROUND 4159 { 4160 LEFTPRE_FETCHATWRAPAROUND_UNNAMED1 = 1, //!< No additional details 4161 }; 4162 4163 enum VERTICALSHIFT32MINUS1 4164 { 4165 VERTICALSHIFT32MINUS1_UNNAMED0 = 0, //!< No additional details 4166 }; 4167 4168 //! \brief HZSHIFT32MINUS1 4169 //! \details 4170 //! Horizontal_shift >= LCU_size and Horizontal_shift prefetch_offset 4171 enum HZSHIFT32MINUS1 4172 { 4173 HZSHIFT32MINUS1_UNNAMED3 = 3, //!< No additional details 4174 }; 4175 4176 //! \brief NUMHZREQMINUS1 4177 //! \details 4178 //! Number of Vertical requests in each region for a constant horizontal position. 4179 enum NUMVERTICALREQMINUS1 4180 { 4181 NUMVERTICALREQMINUS1_UNNAMED11 = 11, //!< No additional details 4182 }; 4183 4184 //! \brief NUMHZREQMINUS1 4185 //! \details 4186 //! Number of Horizontal Requests minus 1 at row begining. 4187 enum NUMHZREQMINUS1 4188 { 4189 NUMHZREQMINUS1_UNNAMED2 = 2, //!< No additional details 4190 }; 4191 4192 enum PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT 4193 { 4194 PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT_UNNAMED0 = 0, //!< No additional details 4195 }; 4196 4197 //! \brief SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 4198 //! \details 4199 //! When this bit is set, Source Luma / Packed data TLB pre-fetches are 4200 //! performed. 4201 enum SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 4202 { 4203 SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 4204 SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 4205 }; 4206 4207 //! \brief SOURCE_CHROMA_TLB_PRE_FETCHENABLE 4208 //! \details 4209 //! When this bit is set, Source Chroma TLB pre-fetches are performed. 4210 enum SOURCE_CHROMA_TLB_PRE_FETCHENABLE 4211 { 4212 SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 4213 SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 4214 }; 4215 4216 enum VERTICALSHIFT32MINUS1SRC 4217 { 4218 VERTICALSHIFT32MINUS1SRC_UNNAMED0 = 0, //!< No additional details 4219 }; 4220 4221 //! \brief HZSHIFT32MINUS1SRC 4222 //! \details 4223 //! Horizontal_shift >= LCU_size and Horizontal_shift prefetch_offset 4224 enum HZSHIFT32MINUS1SRC 4225 { 4226 HZSHIFT32MINUS1SRC_UNNAMED0 = 0, //!< No additional details 4227 HZSHIFT32MINUS1SRC_UNNAMED3 = 3, //!< No additional details 4228 }; 4229 4230 //! \brief NUMVERTICALREQMINUS1SRC 4231 //! \details 4232 //! Number of Horizontal requests Minus 1 for source 4233 enum NUMVERTICALREQMINUS1SRC 4234 { 4235 NUMVERTICALREQMINUS1SRC_UNNAMED0 = 0, //!< This is the valid for AVC 4236 NUMVERTICALREQMINUS1SRC_UNNAMED1 = 1, //!< This is the valid value for HEVC 4237 }; 4238 4239 //! \brief NUMHZREQMINUS1SRC 4240 //! \details 4241 //! Number of Horizontal requests Minus 1 for source 4242 enum NUMHZREQMINUS1SRC 4243 { 4244 NUMHZREQMINUS1SRC_UNNAMED0 = 0, //!< No additional details 4245 }; 4246 4247 //! \brief PRE_FETCHOFFSETFORSOURCE 4248 //! \details 4249 //! Pre-fetch offset for Reference in 16 pixel increment. 4250 enum PRE_FETCHOFFSETFORSOURCE 4251 { 4252 PRE_FETCHOFFSETFORSOURCE_UNNAMED0 = 0, //!< No additional details 4253 PRE_FETCHOFFSETFORSOURCE_UNNAMED_4 = 4, //!< This value is applicable in HEVC mode 4254 PRE_FETCHOFFSETFORSOURCE_UNNAMED7 = 7, //!< This Value is applicable in AVC mode 4255 }; 4256 4257 enum CAPTURE_MODE 4258 { 4259 CAPTURE_MODE_UNNAMED0 = 0, //!< No Parallel capture 4260 CAPTURE_MODE_UNNAMED1 = 1, //!< Parallel encode from Display overlay 4261 CAPTURE_MODE_CAMERA = 2, //!< Parallel encode from Camera Pipe 4262 CAPTURE_MODE_UNNAMED3 = 3, //!< Reserved 4263 }; 4264 4265 enum STREAMING_BUFFER_CONFIG 4266 { 4267 STREAMING_BUFFER_UNSUPPORTED = 0, 4268 STREAMING_BUFFER_64 = 1, 4269 STREAMING_BUFFER_128 = 2, 4270 STREAMING_BUFFER_256 = 3, 4271 }; 4272 4273 enum PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID 4274 { 4275 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED0 = 0, //!< Display tailpointer address location 00ED0h-00ED3h 4276 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED1 = 1, //!< Display tailpointer address location 00ED4h-00ED7h 4277 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED2 = 2, //!< Display tailpointer address location 00ED8h-00EDBh 4278 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED3 = 3, //!< Display tailpointer address location 00EDCh-00EDFh 4279 }; 4280 4281 //! \name Initializations 4282 4283 //! \brief Explicit member initialization function VDENC_PIPE_MODE_SELECT_CMDCmd::VDENC_PIPE_MODE_SELECT_CMD4284 VDENC_PIPE_MODE_SELECT_CMD() 4285 { 4286 MOS_ZeroMemory(this, sizeof(*this)); 4287 4288 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 4289 DW0.Subopb = SUBOPB_VDENCPIPEMODESELECT; 4290 DW0.Subopa = SUBOPA_UNNAMED0; 4291 DW0.Opcode = OPCODE_VDENCPIPE; 4292 DW0.Pipeline = PIPELINE_MFXCOMMON; 4293 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4294 4295 DW1.FrameStatisticsStreamOutEnable = FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE; 4296 DW1.TlbPrefetchEnable = TLB_PREFETCH_ENABLE_DISABLE; 4297 DW1.PakThresholdCheckEnable = PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE; 4298 DW1.VdencStreamInEnable = VDENC_STREAM_IN_ENABLE_DISABLE; 4299 DW1.BitDepth = BIT_DEPTH_8BIT; 4300 DW1.PrimaryChannelSelectionForRgbEncoding = PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1; 4301 DW1.FirstSecondaryChannelSelectionForRgbEncoding = FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2; 4302 DW1.StreamingBufferConfig = STREAMING_BUFFER_UNSUPPORTED; 4303 4304 DW2.HmeRegionPreFetchenable = HME_REGION_PRE_FETCHENABLE_UNNAMED1; 4305 DW2.Topprefetchenablemode = TOPPREFETCHENABLEMODE_UNNAMED0; 4306 DW2.LeftpreFetchatwraparound = LEFTPRE_FETCHATWRAPAROUND_UNNAMED1; 4307 DW2.Verticalshift32Minus1 = VERTICALSHIFT32MINUS1_UNNAMED0; 4308 DW2.Hzshift32Minus1 = HZSHIFT32MINUS1_UNNAMED3; 4309 DW2.NumVerticalReqMinus1 = NUMVERTICALREQMINUS1_UNNAMED11; 4310 DW2.Numhzreqminus1 = NUMHZREQMINUS1_UNNAMED2; 4311 DW2.PreFetchOffsetForReferenceIn16PixelIncrement = PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT_UNNAMED0; 4312 4313 DW3.SourceLumaPackedDataTlbPreFetchenable = SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED0; 4314 DW3.SourceChromaTlbPreFetchenable = SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED0; 4315 DW3.Verticalshift32Minus1Src = VERTICALSHIFT32MINUS1SRC_UNNAMED0; 4316 DW3.Hzshift32Minus1Src = HZSHIFT32MINUS1SRC_UNNAMED0; 4317 DW3.Numverticalreqminus1Src = NUMVERTICALREQMINUS1SRC_UNNAMED0; 4318 DW3.Numhzreqminus1Src = NUMHZREQMINUS1SRC_UNNAMED0; 4319 DW3.PreFetchoffsetforsource = PRE_FETCHOFFSETFORSOURCE_UNNAMED0; 4320 4321 DW5.CaptureMode = CAPTURE_MODE_UNNAMED0; 4322 DW5.ParallelCaptureAndEncodeSessionId = PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED0; 4323 } 4324 4325 static const size_t dwSize = 7; 4326 static const size_t byteSize = 28; 4327 }; 4328 4329 //! 4330 //! \brief VDENC_REF_SURFACE_STATE 4331 //! \details 4332 //! This command specifies the surface state parameters for the normal 4333 //! reference surfaces. 4334 //! 4335 struct VDENC_REF_SURFACE_STATE_CMD 4336 { 4337 union 4338 { 4339 //!< DWORD 0 4340 struct 4341 { 4342 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4343 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4344 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4345 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4346 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4347 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4348 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4349 }; 4350 uint32_t Value; 4351 } DW0; 4352 union 4353 { 4354 //!< DWORD 1 4355 struct 4356 { 4357 uint32_t SurfaceId : __CODEGEN_BITFIELD(0, 2); //!< Surface ID 4358 uint32_t Reserved : __CODEGEN_BITFIELD(3, 31); //!< Reserved 4359 }; 4360 uint32_t Value; 4361 } DW1; 4362 VDENC_Surface_State_Fields_CMD Dwords25; //!< Dwords 2..5 4363 4364 //! \name Local enumerations 4365 4366 enum SUBOPB 4367 { 4368 SUBOPB_VDENCREFSURFACESTATE = 2, //!< No additional details 4369 }; 4370 4371 enum SUBOPA 4372 { 4373 SUBOPA_UNNAMED0 = 0, //!< No additional details 4374 }; 4375 4376 enum OPCODE 4377 { 4378 OPCODE_VDENCPIPE = 1, //!< No additional details 4379 }; 4380 4381 enum PIPELINE 4382 { 4383 PIPELINE_MFXCOMMON = 2, //!< No additional details 4384 }; 4385 4386 enum COMMAND_TYPE 4387 { 4388 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4389 }; 4390 4391 //! \name Initializations 4392 4393 //! \brief Explicit member initialization function VDENC_REF_SURFACE_STATE_CMDCmd::VDENC_REF_SURFACE_STATE_CMD4394 VDENC_REF_SURFACE_STATE_CMD() 4395 { 4396 MOS_ZeroMemory(this, sizeof(*this)); 4397 4398 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 4399 DW0.Subopb = SUBOPB_VDENCREFSURFACESTATE; 4400 DW0.Subopa = SUBOPA_UNNAMED0; 4401 DW0.Opcode = OPCODE_VDENCPIPE; 4402 DW0.Pipeline = PIPELINE_MFXCOMMON; 4403 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4404 } 4405 4406 static const size_t dwSize = 6; 4407 static const size_t byteSize = 24; 4408 }; 4409 4410 //! 4411 //! \brief VDENC_SRC_SURFACE_STATE 4412 //! \details 4413 //! This command specifies the uncompressed original input picture to be 4414 //! encoded. The actual base address is defined in the 4415 //! VDENC_PIPE_BUF_ADDR_STATE. Pitch can be wider than the Picture Width in 4416 //! pixels and garbage will be there at the end of each line. The following 4417 //! describes all the different formats that are supported in WLV+ VDEnc: 4418 //! NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V offset is set to 4419 //! 0 (the only format supported for video codec); vertical UV offset is MB 4420 //! aligned; UV xoffsets = 0. 4421 //! This surface state here is identical to the Surface State for 4422 //! deinterlace and sample_8x8 messages described in the Shared Function 4423 //! Volume and Sampler Chapter. For non pixel data, such as row stores, DMV 4424 //! and streamin/out, a linear buffer is employed. For row stores, the H/W 4425 //! is designed to guarantee legal memory accesses (read and write). For the 4426 //! remaining cases, indirect object base address, indirect object address 4427 //! upper bound, object data start address (offset) and object data length 4428 //! are used to fully specified their corresponding buffer. This mechanism 4429 //! is chosen over the pixel surface type because of their variable record 4430 //! sizes. All row store surfaces are linear surface. Their addresses are 4431 //! programmed in VDEnc_Pipe_Buf_Base_State. 4432 //! 4433 struct VDENC_SRC_SURFACE_STATE_CMD 4434 { 4435 union 4436 { 4437 //!< DWORD 0 4438 struct 4439 { 4440 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4441 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4442 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4443 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4444 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4445 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4446 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4447 }; 4448 uint32_t Value; 4449 } DW0; 4450 union 4451 { 4452 //!< DWORD 1 4453 struct 4454 { 4455 uint32_t Reserved32; //!< Reserved 4456 }; 4457 uint32_t Value; 4458 } DW1; 4459 VDENC_Surface_State_Fields_CMD Dwords25; //!< Dwords 2..5 4460 4461 //! \name Local enumerations 4462 4463 enum SUBOPB 4464 { 4465 SUBOPB_VDENCSRCSURFACESTATE = 1, //!< No additional details 4466 }; 4467 4468 enum SUBOPA 4469 { 4470 SUBOPA_UNNAMED0 = 0, //!< No additional details 4471 }; 4472 4473 enum OPCODE 4474 { 4475 OPCODE_VDENCPIPE = 1, //!< No additional details 4476 }; 4477 4478 enum PIPELINE 4479 { 4480 PIPELINE_MFXCOMMON = 2, //!< No additional details 4481 }; 4482 4483 enum COMMAND_TYPE 4484 { 4485 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4486 }; 4487 4488 //! \name Initializations 4489 4490 //! \brief Explicit member initialization function VDENC_SRC_SURFACE_STATE_CMDCmd::VDENC_SRC_SURFACE_STATE_CMD4491 VDENC_SRC_SURFACE_STATE_CMD() 4492 { 4493 MOS_ZeroMemory(this, sizeof(*this)); 4494 4495 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 4496 DW0.Subopb = SUBOPB_VDENCSRCSURFACESTATE; 4497 DW0.Subopa = SUBOPA_UNNAMED0; 4498 DW0.Opcode = OPCODE_VDENCPIPE; 4499 DW0.Pipeline = PIPELINE_MFXCOMMON; 4500 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4501 } 4502 4503 static const size_t dwSize = 6; 4504 static const size_t byteSize = 24; 4505 }; 4506 4507 //! 4508 //! \brief VDENC_WALKER_STATE 4509 //! \details 4510 //! 4511 //! 4512 struct VDENC_WALKER_STATE_CMD 4513 { 4514 union 4515 { 4516 struct 4517 { 4518 uint32_t Length : __CODEGEN_BITFIELD(0, 11); //!< LENGTH 4519 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4520 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4521 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4522 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4523 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4524 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4525 }; 4526 uint32_t Value; 4527 } DW0; 4528 union 4529 { 4530 struct 4531 { 4532 uint32_t MbLcuStartYPosition : __CODEGEN_BITFIELD(0, 8); //!< MB/LCU Start Y Position 4533 uint32_t Reserved41 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 4534 uint32_t MbLcuStartXPosition : __CODEGEN_BITFIELD(16, 24); //!< MB/LCU Start X Position 4535 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 27); //!< Reserved 4536 uint32_t FirstSuperSlice : __CODEGEN_BITFIELD(28, 28); //!< First Super Slice 4537 uint32_t Reserved61 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4538 }; 4539 uint32_t Value; 4540 } DW1; 4541 union 4542 { 4543 struct 4544 { 4545 uint32_t NextsliceMbStartYPosition : __CODEGEN_BITFIELD(0, 9); //!< NextSlice MB Start Y Position 4546 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15); //!< Reserved 4547 uint32_t NextsliceMbLcuStartXPosition : __CODEGEN_BITFIELD(16, 25); //!< NextSlice MB/LCU Start X Position 4548 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 4549 }; 4550 uint32_t Value; 4551 } DW2; 4552 4553 //! \name Local enumerations 4554 4555 enum LENGTH 4556 { 4557 LENGTH_UNNAMED1 = 1, //!< No additional details 4558 }; 4559 4560 enum SUBOPB 4561 { 4562 SUBOPB_VDENCWALKERSTATE = 7, //!< No additional details 4563 }; 4564 4565 enum SUBOPA 4566 { 4567 SUBOPA_UNNAMED0 = 0, //!< No additional details 4568 }; 4569 4570 enum OPCODE 4571 { 4572 OPCODE_VDENCPIPE = 1, //!< No additional details 4573 }; 4574 4575 enum PIPELINE 4576 { 4577 PIPELINE_MFXCOMMON = 2, //!< No additional details 4578 }; 4579 4580 enum COMMAND_TYPE 4581 { 4582 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4583 }; 4584 4585 //! \name Initializations 4586 4587 //! \brief Explicit member initialization function VDENC_WALKER_STATE_CMDCmd::VDENC_WALKER_STATE_CMD4588 VDENC_WALKER_STATE_CMD() 4589 { 4590 MOS_ZeroMemory(this, sizeof(*this)); 4591 4592 DW0.Length = LENGTH_UNNAMED1; 4593 DW0.Subopb = SUBOPB_VDENCWALKERSTATE; 4594 DW0.Subopa = SUBOPA_UNNAMED0; 4595 DW0.Opcode = OPCODE_VDENCPIPE; 4596 DW0.Pipeline = PIPELINE_MFXCOMMON; 4597 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4598 } 4599 4600 static const size_t dwSize = 3; 4601 static const size_t byteSize = 12; 4602 }; 4603 4604 //! 4605 //! \brief VDENC_CONTROL_STATE 4606 //! \details 4607 //! 4608 //! 4609 struct VDENC_CONTROL_STATE_CMD 4610 { 4611 union 4612 { 4613 //!< DWORD 0 4614 struct 4615 { 4616 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< Dword Length 4617 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4618 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< Media Instruction Command 4619 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< Media Instruction Opcode 4620 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< Pipeline Type 4621 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< Command Type 4622 }; 4623 uint32_t Value; 4624 } DW0; 4625 union 4626 { 4627 //!< DWORD 1 4628 struct 4629 { 4630 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 4631 uint32_t VdencInitialization : __CODEGEN_BITFIELD(1, 1); //!< VDenc Initialization 4632 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved 4633 }; 4634 uint32_t Value; 4635 } DW1; 4636 4637 //! \name Local enumerations 4638 4639 //! \name Initializations 4640 4641 //! \brief Explicit member initialization function VDENC_CONTROL_STATE_CMDCmd::VDENC_CONTROL_STATE_CMD4642 VDENC_CONTROL_STATE_CMD() 4643 { 4644 MOS_ZeroMemory(this, sizeof(*this)); 4645 4646 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 4647 DW0.MediaInstructionCommand = 0xB; 4648 DW0.MediaInstructionOpcode = 0x1; 4649 DW0.PipelineType = 0x2; 4650 DW0.CommandType = 0x3; 4651 } 4652 4653 static const size_t dwSize = 2; 4654 static const size_t byteSize = 8; 4655 }; 4656 4657 //! 4658 //! \brief VDENC_AVC_SLICE_STATE 4659 //! \details 4660 //! 4661 //! 4662 struct VDENC_AVC_SLICE_STATE_CMD 4663 { 4664 union 4665 { 4666 struct 4667 { 4668 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4669 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4670 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4671 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4672 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4673 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4674 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4675 }; 4676 uint32_t Value; 4677 } DW0; 4678 union 4679 { 4680 struct 4681 { 4682 uint32_t RoundIntra : __CODEGEN_BITFIELD(0, 2); //!< RoundIntra 4683 uint32_t RoundIntraEnable : __CODEGEN_BITFIELD(3, 3); //!< RoundIntraEnable 4684 uint32_t RoundInter : __CODEGEN_BITFIELD(4, 6); //!< RoundInter 4685 uint32_t RoundInterEnable : __CODEGEN_BITFIELD(7, 7); //!< RoundInterEnable 4686 uint32_t Reserved32 : __CODEGEN_BITFIELD(8, 31); //!< Reserved 4687 }; 4688 uint32_t Value; 4689 } DW1; 4690 union 4691 { 4692 struct 4693 { 4694 uint32_t Reserved64; //!< Reserved 4695 }; 4696 uint32_t Value; 4697 } DW2; 4698 union 4699 { 4700 struct 4701 { 4702 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD(0, 2); //!< Log 2 Weight Denom Luma 4703 uint32_t Reserved99 : __CODEGEN_BITFIELD(3, 31); //!< Reserved 4704 }; 4705 uint32_t Value; 4706 } DW3; 4707 4708 //! \name Local enumerations 4709 4710 enum SUBOPB 4711 { 4712 SUBOPB_VDENCAVCSLICESTATE = 12, //!< No additional details 4713 }; 4714 4715 enum SUBOPA 4716 { 4717 SUBOPA_UNNAMED0 = 0, //!< No additional details 4718 }; 4719 4720 enum OPCODE 4721 { 4722 OPCODE_VDENCPIPE = 1, //!< No additional details 4723 }; 4724 4725 enum PIPELINE 4726 { 4727 PIPELINE_MFXCOMMON = 2, //!< No additional details 4728 }; 4729 4730 enum COMMAND_TYPE 4731 { 4732 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4733 }; 4734 4735 //! \name Initializations 4736 4737 //! \brief Explicit member initialization function VDENC_AVC_SLICE_STATE_CMDCmd::VDENC_AVC_SLICE_STATE_CMD4738 VDENC_AVC_SLICE_STATE_CMD() 4739 { 4740 MOS_ZeroMemory(this, sizeof(*this)); 4741 4742 DW0.Value = 0x708c0002; 4743 } 4744 4745 static const size_t dwSize = 4; 4746 static const size_t byteSize = 16; 4747 }; 4748 4749 struct VDENC_HEVC_VP9_TILE_SLICE_STATE_CMD 4750 { 4751 union 4752 { 4753 struct 4754 { 4755 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4756 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4757 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4758 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4759 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4760 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4761 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4762 }; 4763 uint32_t Value; 4764 } DW0; 4765 union 4766 { 4767 struct 4768 { 4769 uint32_t Reserved32; //!< Reserved 4770 }; 4771 uint32_t Value; 4772 } DW1; 4773 union 4774 { 4775 struct 4776 { 4777 uint32_t Reserved64; //!< Reserved 4778 }; 4779 uint32_t Value; 4780 } DW2; 4781 union 4782 { 4783 struct 4784 { 4785 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD(0, 2); //!< Log 2 Weight Denom Luma 4786 uint32_t Reserved99 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 4787 uint32_t HevcVp9Log2WeightDenomLuma : __CODEGEN_BITFIELD(4, 6); //!< HEVC/VP9 Log 2 Weight Denom Luma 4788 uint32_t Reserved103 : __CODEGEN_BITFIELD(7, 8); //!< Reserved 4789 uint32_t NumParEngine : __CODEGEN_BITFIELD(9, 10); //!< NUM_PAR_ENGINE 4790 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15); //!< Reserved 4791 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD(16, 16); //!< Tile Row store Select 4792 uint32_t Log2WeightDenomChroma : __CODEGEN_BITFIELD(17, 19); //!< Log 2 Weight Denom Chroma 4793 uint32_t Reserved113 : __CODEGEN_BITFIELD(20, 23); //!< Reserved 4794 uint32_t TileNumber : __CODEGEN_BITFIELD(24, 31); //!< Tile number 4795 }; 4796 uint32_t Value; 4797 } DW3; 4798 union 4799 { 4800 struct 4801 { 4802 uint32_t TileStartCtbY : __CODEGEN_BITFIELD(0, 15); //!< Tile Start CTB-Y 4803 uint32_t TileStartCtbX : __CODEGEN_BITFIELD(16, 31); //!< Tile Start CTB-X 4804 }; 4805 uint32_t Value; 4806 } DW4; 4807 union 4808 { 4809 struct 4810 { 4811 uint32_t TileWidth : __CODEGEN_BITFIELD(0, 15); //!< Tile Width 4812 uint32_t TileHeight : __CODEGEN_BITFIELD(16, 31); //!< Tile Height 4813 }; 4814 uint32_t Value; 4815 } DW5; 4816 union 4817 { 4818 struct 4819 { 4820 uint32_t StreaminOffsetEnable : __CODEGEN_BITFIELD(0, 0); //!< Streamin Offset enable 4821 uint32_t Reserved193 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4822 uint32_t TileStreaminOffset : __CODEGEN_BITFIELD(6, 31); //!< Tile Streamin Offset 4823 }; 4824 uint32_t Value; 4825 } DW6; 4826 union 4827 { 4828 struct 4829 { 4830 uint32_t RowStoreOffsetEnable : __CODEGEN_BITFIELD(0, 0); //!< Row store Offset enable 4831 uint32_t Reserved225 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4832 uint32_t TileRowstoreOffset : __CODEGEN_BITFIELD(6, 31); //!< Tile Rowstore Offset 4833 }; 4834 uint32_t Value; 4835 } DW7; 4836 union 4837 { 4838 struct 4839 { 4840 uint32_t TileStreamoutOffsetEnable : __CODEGEN_BITFIELD(0, 0); //!< Tile streamout offset enable 4841 uint32_t Reserved257 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4842 uint32_t TileStreamoutOffset : __CODEGEN_BITFIELD(6, 31); //!< Tile streamout offset 4843 }; 4844 uint32_t Value; 4845 } DW8; 4846 union 4847 { 4848 struct 4849 { 4850 uint32_t LcuStreamOutOffsetEnable : __CODEGEN_BITFIELD(0, 0); //!< LCU stream out offset enable 4851 uint32_t Reserved289 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4852 uint32_t TileLcuStreamOutOffset : __CODEGEN_BITFIELD(6, 31); //!< Tile LCU stream out offset 4853 }; 4854 uint32_t Value; 4855 } DW9; 4856 union 4857 { 4858 struct 4859 { 4860 uint32_t Reserved320; //!< Reserved 4861 }; 4862 uint32_t Value; 4863 } DW10; 4864 union 4865 { 4866 struct 4867 { 4868 uint32_t DeltaQp : __CODEGEN_BITFIELD(0, 7); //!< DELTA_QP 4869 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW11_BIT8 : __CODEGEN_BITFIELD(8, 17); 4870 uint32_t Reserved370 : __CODEGEN_BITFIELD(18, 23); //!< Reserved 4871 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW11_BIT24 : __CODEGEN_BITFIELD(24, 31); 4872 }; 4873 uint32_t Value; 4874 } DW11; 4875 union 4876 { 4877 struct 4878 { 4879 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT0 : __CODEGEN_BITFIELD(0, 2); 4880 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT3 : __CODEGEN_BITFIELD(3, 3); 4881 uint32_t Reserved387 : __CODEGEN_BITFIELD(4, 7); //!< Reserved 4882 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT8 : __CODEGEN_BITFIELD(8, 15); 4883 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT16 : __CODEGEN_BITFIELD(16, 17); 4884 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT18 : __CODEGEN_BITFIELD(18, 22); 4885 uint32_t Reserved407 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 4886 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT24 : __CODEGEN_BITFIELD(24, 25); 4887 uint32_t PaletteModeEnable : __CODEGEN_BITFIELD(26, 26); //!< Palette Mode Enable 4888 uint32_t IbcControl : __CODEGEN_BITFIELD(27, 28); //!< IBC_CONTROL 4889 uint32_t Reserved413 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4890 }; 4891 uint32_t Value; 4892 } DW12; 4893 union 4894 { 4895 struct 4896 { 4897 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW13_BIT0 : __CODEGEN_BITFIELD(0, 9); 4898 uint32_t Reserved426 : __CODEGEN_BITFIELD(10, 15); //!< Reserved 4899 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW13_BIT16 : __CODEGEN_BITFIELD(16, 25); 4900 uint32_t Reserved442 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 4901 }; 4902 uint32_t Value; 4903 } DW13; 4904 union 4905 { 4906 struct 4907 { 4908 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT0 : __CODEGEN_BITFIELD(0, 5); 4909 uint32_t Reserved454 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 4910 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT8 : __CODEGEN_BITFIELD(8, 13); 4911 uint32_t Reserved462 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 4912 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT16 : __CODEGEN_BITFIELD(16, 20); 4913 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT21 : __CODEGEN_BITFIELD(21, 22); 4914 uint32_t Reserved471 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 4915 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT24 : __CODEGEN_BITFIELD(24, 30); 4916 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT31 : __CODEGEN_BITFIELD(31, 31); 4917 }; 4918 uint32_t Value; 4919 } DW14; 4920 union 4921 { 4922 struct 4923 { 4924 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW15_BIT0 : __CODEGEN_BITFIELD(0, 9); 4925 uint32_t Reserved490 : __CODEGEN_BITFIELD(10, 15); //!< Reserved 4926 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW15_BIT16 : __CODEGEN_BITFIELD(16, 31); 4927 }; 4928 uint32_t Value; 4929 } DW15; 4930 union 4931 { 4932 struct 4933 { 4934 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT0 : __CODEGEN_BITFIELD(0, 5); 4935 uint32_t Reserved518 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 4936 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT8 : __CODEGEN_BITFIELD(8, 13); 4937 uint32_t Reserved526 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 4938 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT16 : __CODEGEN_BITFIELD(16, 21); 4939 uint32_t Reserved534 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 4940 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT24 : __CODEGEN_BITFIELD(24, 28); 4941 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT29 : __CODEGEN_BITFIELD(29, 29); 4942 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT30 : __CODEGEN_BITFIELD(30, 30); 4943 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT31 : __CODEGEN_BITFIELD(31, 31); 4944 }; 4945 uint32_t Value; 4946 } DW16; 4947 union 4948 { 4949 struct 4950 { 4951 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW17_BIT0 : __CODEGEN_BITFIELD(0, 0); 4952 uint32_t Reserved545 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4953 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW17_BIT6 : __CODEGEN_BITFIELD(6, 31); 4954 }; 4955 uint32_t Value; 4956 } DW17; 4957 union 4958 { 4959 struct 4960 { 4961 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW18_BIT0 : __CODEGEN_BITFIELD(0, 0); 4962 uint32_t Reserved577 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4963 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW18_BIT6 : __CODEGEN_BITFIELD(6, 31); 4964 }; 4965 uint32_t Value; 4966 } DW18; 4967 union 4968 { 4969 struct 4970 { 4971 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW19_BIT0; 4972 }; 4973 uint32_t Value; 4974 } DW19; 4975 union 4976 { 4977 struct 4978 { 4979 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW20_BIT0; 4980 }; 4981 uint32_t Value; 4982 } DW20; 4983 union 4984 { 4985 struct 4986 { 4987 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW21_BIT0; 4988 }; 4989 uint32_t Value; 4990 } DW21; 4991 union 4992 { 4993 struct 4994 { 4995 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW22_BIT0; 4996 }; 4997 uint32_t Value; 4998 } DW22; 4999 union 5000 { 5001 struct 5002 { 5003 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW23_BIT0; 5004 }; 5005 uint32_t Value; 5006 } DW23; 5007 union 5008 { 5009 struct 5010 { 5011 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW24_BIT0; 5012 }; 5013 uint32_t Value; 5014 } DW24; 5015 union 5016 { 5017 struct 5018 { 5019 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW25_BIT0; 5020 }; 5021 uint32_t Value; 5022 } DW25; 5023 union 5024 { 5025 struct 5026 { 5027 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW26_BIT0; 5028 }; 5029 uint32_t Value; 5030 } DW26; 5031 union 5032 { 5033 struct 5034 { 5035 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW27_BIT0 : __CODEGEN_BITFIELD(0, 0); 5036 uint32_t Reserved15 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 5037 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW27_BIT6 : __CODEGEN_BITFIELD(6, 31); 5038 }; 5039 uint32_t Value; 5040 } DW27; 5041 5042 //! \brief Explicit member initialization function VDENC_HEVC_VP9_TILE_SLICE_STATE_CMDCmd::VDENC_HEVC_VP9_TILE_SLICE_STATE_CMD5043 VDENC_HEVC_VP9_TILE_SLICE_STATE_CMD() 5044 { 5045 MOS_ZeroMemory(this, sizeof(*this)); 5046 5047 DW0.Value = 0x708d001a; 5048 5049 DW14.Value = 0x3f400000; 5050 5051 DW16.Value = 0x003f3f3f; 5052 } 5053 5054 static const size_t dwSize = 28; 5055 static const size_t byteSize = 112; 5056 }; 5057 5058 using VDENC_CMD1_CMD = _VDENC_CMD1_CMD; 5059 using VDENC_CMD2_CMD = _VDENC_CMD2_CMD; 5060 using VDENC_CMD3_CMD = _VDENC_CMD3_CMD; 5061 using VDENC_AVC_IMG_STATE_CMD = _VDENC_AVC_IMG_STATE_CMD; 5062 }; 5063 } // namespace v1 5064 } // namespace xe_lpm_plus_base 5065 } // namespace vdenc 5066 } // namespace vdbox 5067 } // namespace mhw 5068 5069 #pragma pack() 5070 5071 #endif // __MHW_VDBOX_VDENC_HWCMD_XE2_HPM_H__ 5072