xref: /btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h (revision c30869498fb8e98c1408c9db0e7624f02f483b73) 
1 /* generated configuration header file - do not edit */
2 #ifndef BSP_MCU_FAMILY_CFG_H_
3 #define BSP_MCU_FAMILY_CFG_H_
4 #ifdef __cplusplus
5 extern "C" {
6 #endif
7 
8 #include "bsp_mcu_device_pn_cfg.h"
9 #include "bsp_mcu_device_cfg.h"
10 #include "../../../ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h"
11 #include "bsp_clock_cfg.h"
12 #define BSP_MCU_GROUP_RA6M4 (1)
13 #define BSP_LOCO_HZ                 (32768)
14 #define BSP_MOCO_HZ                 (8000000)
15 #define BSP_SUB_CLOCK_HZ            (32768)
16 #if   BSP_CFG_HOCO_FREQUENCY == 0
17 #define BSP_HOCO_HZ                 (16000000)
18 #elif BSP_CFG_HOCO_FREQUENCY == 1
19                 #define BSP_HOCO_HZ                 (18000000)
20             #elif BSP_CFG_HOCO_FREQUENCY == 2
21                 #define BSP_HOCO_HZ                 (20000000)
22             #else
23                 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
24             #endif
25 
26 #define BSP_CFG_FLL_ENABLE                 (0)
27 
28 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
29 #define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
30 #define BSP_MCU_VBATT_SUPPORT              (1)
31 
32 #if defined(_RA_TZ_SECURE)
33             #define BSP_TZ_SECURE_BUILD           (1)
34             #define BSP_TZ_NONSECURE_BUILD        (0)
35             #elif defined(_RA_TZ_NONSECURE)
36             #define BSP_TZ_SECURE_BUILD           (0)
37             #define BSP_TZ_NONSECURE_BUILD        (1)
38             #else
39 #define BSP_TZ_SECURE_BUILD           (0)
40 #define BSP_TZ_NONSECURE_BUILD        (0)
41 #endif
42 
43 /* TrustZone Settings */
44 #define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
45 #define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
46 #define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
47 
48 /* CMSIS TrustZone Settings */
49 #define SCB_CSR_AIRCR_INIT                (1)
50 #define SCB_AIRCR_BFHFNMINS_VAL           (0)
51 #define SCB_AIRCR_SYSRESETREQS_VAL        (1)
52 #define SCB_AIRCR_PRIS_VAL                (0)
53 #define TZ_FPU_NS_USAGE                   (1)
54 #ifndef SCB_NSACR_CP10_11_VAL
55 #define SCB_NSACR_CP10_11_VAL             (3U)
56 #endif
57 
58 #ifndef FPU_FPCCR_TS_VAL
59 #define FPU_FPCCR_TS_VAL                  (1U)
60 #endif
61 #define FPU_FPCCR_CLRONRETS_VAL           (1)
62 
63 #ifndef FPU_FPCCR_CLRONRET_VAL
64 #define FPU_FPCCR_CLRONRET_VAL            (1)
65 #endif
66 
67 /* The C-Cache line size that is configured during startup. */
68 #ifndef BSP_CFG_C_CACHE_LINE_SIZE
69 #define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
70 #endif
71 
72 /* Type 1 Peripheral Security Attribution */
73 
74 /* Peripheral Security Attribution Register (PSAR) Settings */
75 #ifndef BSP_TZ_CFG_PSARB
76 #define BSP_TZ_CFG_PSARB (\
77             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
78             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
79             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
80             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
81             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
82             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
83             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
84             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
85             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
86             (((1 > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
87             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
88             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
89             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
90             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
91             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
92             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
93             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
94             0x33f4f9) /* Unused */
95 #endif
96 #ifndef BSP_TZ_CFG_PSARC
97 #define BSP_TZ_CFG_PSARC (\
98             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
99             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
100             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
101             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
102             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
103             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
104             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
105             0x7fffcef4) /* Unused */
106 #endif
107 #ifndef BSP_TZ_CFG_PSARD
108 #define BSP_TZ_CFG_PSARD (\
109             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
110             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
111             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
112             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
113             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
114             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
115             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
116             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
117             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
118             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
119             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
120             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
121             0xffae07f0) /* Unused */
122 #endif
123 #ifndef BSP_TZ_CFG_PSARE
124 #define BSP_TZ_CFG_PSARE (\
125             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
126             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
127             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
128             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
129             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
130             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
131             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
132             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
133             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
134             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
135             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
136             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
137             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
138             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
139             (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
140             0x3f3ff8) /* Unused */
141 #endif
142 #ifndef BSP_TZ_CFG_MSSAR
143 #define BSP_TZ_CFG_MSSAR (\
144             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
145             (((2 > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
146             0xfffffffc) /* Unused */
147 #endif
148 
149 /* Type 2 Peripheral Security Attribution */
150 
151 /* Security attribution for Cache registers. */
152 #ifndef BSP_TZ_CFG_CSAR
153 #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
154 #endif
155 
156 /* Security attribution for RSTSRn registers. */
157 #ifndef BSP_TZ_CFG_RSTSAR
158 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
159 #endif
160 
161 /* Security attribution for registers of LVD channels. */
162 #ifndef BSP_TZ_CFG_LVDSAR
163 #define BSP_TZ_CFG_LVDSAR (\
164             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
165             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
166             0xFFFFFFFCU)
167 #endif
168 
169 /* Security attribution for LPM registers. */
170 #ifndef BSP_TZ_CFG_LPMSAR
171 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
172 #endif
173 /* Deep Standby Interrupt Factor Security Attribution Register. */
174 #ifndef BSP_TZ_CFG_DPFSAR
175 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
176 #endif
177 
178 /* Security attribution for CGC registers. */
179 #ifndef BSP_TZ_CFG_CGFSAR
180 #if BSP_CFG_CLOCKS_SECURE
181 /* Protect all CGC registers from Non-secure write access. */
182 #define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
183 #else
184 /* Allow Secure and Non-secure write access. */
185 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
186 #endif
187 #endif
188 
189 /* Security attribution for Battery Backup registers. */
190 #ifndef BSP_TZ_CFG_BBFSAR
191 #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
192 #endif
193 
194 /* Security attribution for registers for IRQ channels. */
195 #ifndef BSP_TZ_CFG_ICUSARA
196 #define BSP_TZ_CFG_ICUSARA (\
197             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
198             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
199             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
200             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
201             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
202             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
203             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
204             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
205             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
206             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
207             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
208             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
209             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
210             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
211             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
212             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
213             0xFFFF0000U)
214 #endif
215 
216 /* Security attribution for NMI registers. */
217 #ifndef BSP_TZ_CFG_ICUSARB
218 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
219 #endif
220 
221 /* Security attribution for registers for DMAC channels */
222 #ifndef BSP_TZ_CFG_ICUSARC
223 #define BSP_TZ_CFG_ICUSARC (\
224             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
225             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
226             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
227             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
228             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
229             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
230             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
231             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
232             0xFFFFFF00U)
233 #endif
234 
235 /* Security attribution registers for SELSR0. */
236 #ifndef BSP_TZ_CFG_ICUSARD
237 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
238 #endif
239 
240 /* Security attribution registers for WUPEN0. */
241 #ifndef BSP_TZ_CFG_ICUSARE
242 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
243 #endif
244 
245 /* Security attribution registers for WUPEN1. */
246 #ifndef BSP_TZ_CFG_ICUSARF
247 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
248 #endif
249 
250 /* Set DTCSTSAR if the Secure program uses the DTC. */
251 #if 2 == RA_NOT_DEFINED
252  #define BSP_TZ_CFG_DTC_USED (0U)
253 #else
254 #define BSP_TZ_CFG_DTC_USED (1U)
255 #endif
256 
257 /* Security attribution of FLWT and FCKMHZ registers. */
258 #ifndef BSP_TZ_CFG_FSAR
259 /* If the CGC registers are only accessible in Secure mode, than there is no
260  * reason for nonsecure applications to access FLWT and FCKMHZ. */
261 #if BSP_CFG_CLOCKS_SECURE
262 /* Protect FLWT and FCKMHZ registers from nonsecure write access. */
263 #define BSP_TZ_CFG_FSAR (0xFEFEU)
264 #else
265 /* Allow Secure and Non-secure write access. */
266 #define BSP_TZ_CFG_FSAR (0xFFFFU)
267 #endif
268 #endif
269 
270 /* Security attribution for SRAM registers. */
271 #ifndef BSP_TZ_CFG_SRAMSAR
272 /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
273  * SRAM0WTEN and therefore there is no reason to access PRCR2. */
274 #define BSP_TZ_CFG_SRAMSAR (\
275         1 | \
276         ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
277         4 | \
278         0xFFFFFFF8U)
279 #endif
280 
281 /* Security attribution for Standby RAM registers. */
282 #ifndef BSP_TZ_CFG_STBRAMSAR
283 #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
284 #endif
285 
286 /* Security attribution for the DMAC Bus Master MPU settings. */
287 #ifndef BSP_TZ_CFG_MMPUSARA
288 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
289 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
290 #endif
291 
292 /* Security Attribution Register A for BUS Control registers. */
293 #ifndef BSP_TZ_CFG_BUSSARA
294 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
295 #endif
296 /* Security Attribution Register B for BUS Control registers. */
297 #ifndef BSP_TZ_CFG_BUSSARB
298 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
299 #endif
300 
301 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
302 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
303 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
304 #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
305 #define OFS_SEQ5 (1 << 28) | (1 << 30)
306 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
307 
308 /* Option Function Select Register 1 Security Attribution */
309 #ifndef BSP_CFG_ROM_REG_OFS1_SEL
310 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
311             #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
312 #else
313 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
314 #endif
315 #endif
316 
317 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
318 
319 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
320 #define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
321 
322 /* Dual Mode Select Register */
323 #ifndef BSP_CFG_ROM_REG_DUALSEL
324 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
325 #endif
326 
327 /* Block Protection Register 0 */
328 #ifndef BSP_CFG_ROM_REG_BPS0
329 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
330 #endif
331 /* Block Protection Register 1 */
332 #ifndef BSP_CFG_ROM_REG_BPS1
333 #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
334 #endif
335 /* Block Protection Register 2 */
336 #ifndef BSP_CFG_ROM_REG_BPS2
337 #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
338 #endif
339 /* Permanent Block Protection Register 0 */
340 #ifndef BSP_CFG_ROM_REG_PBPS0
341 #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
342 #endif
343 /* Permanent Block Protection Register 1 */
344 #ifndef BSP_CFG_ROM_REG_PBPS1
345 #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
346 #endif
347 /* Permanent Block Protection Register 2 */
348 #ifndef BSP_CFG_ROM_REG_PBPS2
349 #define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
350 #endif
351 /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
352 #ifndef BSP_CFG_ROM_REG_BPS_SEL0
353 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
354 #endif
355 /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
356 #ifndef BSP_CFG_ROM_REG_BPS_SEL1
357 #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
358 #endif
359 /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
360 #ifndef BSP_CFG_ROM_REG_BPS_SEL2
361 #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
362 #endif
363 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
364 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
365 #endif
366 
367 #ifdef __cplusplus
368 }
369 #endif
370 #endif /* BSP_MCU_FAMILY_CFG_H_ */
371