| /aosp_15_r20/external/clang/test/SemaTemplate/ |
| H A D | instantiation-default-1.cpp | 4 template<> struct Def1<int> { struct
8 template<> struct Def1<const int> { // expected-note{{previous definition is here}} struct
12 template<> struct Def1<int&> { struct
39 template<> struct Def1<const int, const int> { }; // expected-error{{redefinition of 'Def1<const in… struct
|
| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 75 MachineInstr *Def1, *Def2; member
265 MachineInstr &Def1 = *It1, &Def2 = *It2; in genMuxInBlock() local
|
| H A D | HexagonEarlyIfConv.cpp | 444 MachineInstr *Def1 = MRI->getVRegDef(RO1.getReg()); in computePhiCost() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 110 MachineInstr *Def1, *Def2; member
298 MachineInstr &Def1 = *It1, &Def2 = *It2; in genMuxInBlock() local
|
| H A D | HexagonEarlyIfConv.cpp | 480 const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg()); in computePhiCost() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 110 MachineInstr *Def1, *Def2; member
304 MachineInstr &Def1 = *It1, &Def2 = *It2; in genMuxInBlock() local
|
| H A D | HexagonEarlyIfConv.cpp | 480 const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg()); in computePhiCost() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | GCNPreRAOptimizations.cpp | 87 MachineInstr *Def1 = nullptr; in processReg() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCReduceCRLogicals.cpp | 472 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(), in createCRLogicalOpInfo() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCReduceCRLogicals.cpp | 473 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(), in createCRLogicalOpInfo() local
|
| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1517 MachineInstr *Def1 = MRI->getVRegDef(Addr1); in produceSameValue() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1807 MachineInstr *Def1 = MRI->getVRegDef(Addr1); in produceSameValue() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1919 MachineInstr *Def1 = MRI->getVRegDef(Addr1); in produceSameValue() local
|
| /aosp_15_r20/external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4216 bool Def1 = !Elems[I1].isUndef(); in buildVector() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4865 bool Def1 = !Elems[I1].isUndef(); in buildVector() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5405 bool Def1 = !Elems[I1].isUndef(); in buildVector() local
|