1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DRAMC_PI_API_MT8183_H 4 #define _DRAMC_PI_API_MT8183_H 5 6 #include <types.h> 7 #include <soc/dramc_common.h> 8 #include <soc/emi.h> 9 10 #define DATLAT_TAP_NUMBER 32 11 #define HW_REG_SHUFFLE_MAX 4 12 13 #define DRAMC_BROADCAST_ON 0x1f 14 #define DRAMC_BROADCAST_OFF 0x0 15 #define TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP 64 16 17 #define IMP_LP4X_TERM_VREF_SEL 0x1b 18 #define IMP_DRVP_LP4X_UNTERM_VREF_SEL 0x1a 19 #define IMP_DRVN_LP4X_UNTERM_VREF_SEL 0x16 20 #define IMP_TRACK_LP4X_UNTERM_VREF_SEL 0x1a 21 #define MR23_DEFAULT_VALUE 0x3f 22 #define CA_TRAINING_NUM 10 23 24 enum dram_te_op { 25 TE_OP_WRITE_READ_CHECK = 0, 26 TE_OP_READ_CHECK 27 }; 28 29 enum { 30 PASS_RANGE_NA = 0x7fff 31 }; 32 33 enum { 34 GATING_PATTERN_NUM = 0x23, 35 GATING_GOLDEND_DQSCNT = 0x4646 36 }; 37 38 enum cke_type { 39 CKE_FIXOFF = 0, 40 CKE_FIXON, 41 CKE_DYNAMIC 42 }; 43 44 typedef enum { 45 CBT_LOW_FREQ = 0, 46 CBT_HIGH_FREQ, 47 } cbt_freq; 48 49 enum { 50 IMPCAL_STAGE_DRVP = 0x1, 51 IMPCAL_STAGE_DRVN, 52 IMPCAL_STAGE_TRACKING 53 }; 54 55 enum { 56 DQS_GW_COARSE_STEP = 1, 57 DQS_GW_FINE_END = 32, 58 DQS_GW_FINE_STEP = 4, 59 RX_DQS_CTL_LOOP = 8, 60 RX_DLY_DQSIENSTB_LOOP = 32 61 }; 62 63 enum { 64 DLL_MASTER = 0, 65 DLL_SLAVE, 66 }; 67 68 struct reg_value { 69 u32 *addr; 70 u32 value; 71 }; 72 73 #define _SELPH_DQS_BITS(l, h) ((l << 0) | (l << 4) | (l << 8) | (l << 12) | \ 74 (h << 16) | (h << 20) | (h << 24) | (h << 28)) 75 76 enum { 77 DQ_DIV_SHIFT = 3, 78 DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, 79 OEN_SHIFT = 16, 80 81 SELPH_DQS0_1600 = _SELPH_DQS_BITS(0x2, 0x1), 82 SELPH_DQS1_1600 = _SELPH_DQS_BITS(0x1, 0x6), 83 SELPH_DQS0_2400 = _SELPH_DQS_BITS(0x3, 0x2), 84 SELPH_DQS1_2400 = _SELPH_DQS_BITS(0x1, 0x6), 85 SELPH_DQS0_3200 = _SELPH_DQS_BITS(0x3, 0x3), 86 SELPH_DQS1_3200 = _SELPH_DQS_BITS(0x5, 0x2), 87 SELPH_DQS0_3600 = _SELPH_DQS_BITS(0x4, 0x3), 88 SELPH_DQS1_3600 = _SELPH_DQS_BITS(0x1, 0x6), 89 }; 90 91 void dramc_get_rank_size(u64 *dram_rank_size); 92 void dramc_runtime_config(u32 rk_num); 93 void dramc_set_broadcast(u32 onoff); 94 u32 dramc_get_broadcast(void); 95 u8 get_freq_fsq(u8 freq_group); 96 void dramc_init(const struct sdram_params *params, u8 freq_group, 97 struct dram_shared_data *shared); 98 void dramc_sw_impedance_save_reg(u8 freq_group, 99 const struct dram_impedance *impedance); 100 void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option, 101 struct dram_impedance *impedance); 102 void dramc_apply_config_before_calibration(u8 freq_group, u32 cbt_mode); 103 void dramc_apply_config_after_calibration(const struct mr_value *mr, u32 rk_num); 104 int dramc_calibrate_all_channels(const struct sdram_params *pams, 105 u8 freq_group, struct mr_value *mr, bool run_dvfs); 106 void dramc_hw_gating_onoff(u8 chn, bool onoff); 107 void dramc_enable_phy_dcm(u8 chn, bool bEn); 108 void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); 109 u32 get_shu_freq(u8 shu); 110 void dramc_hw_dqsosc(u8 chn, u32 rk_num); 111 void dramc_dqs_precalculation_preset(void); 112 void get_dram_info_after_cal(u8 *density, u32 rk_num); 113 void set_mrr_pinmux_mapping(void); 114 void dramc_cke_fix_onoff(enum cke_type option, u8 chn); 115 void cbt_mrr_pinmux_mapping(void); 116 117 #endif /* _DRAMC_PI_API_MT8183_H */ 118