1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_MEDIATEK_COMMON 4 bool 5 select NO_ECAM_MMCONF_SUPPORT if PCI 6 help 7 common code blocks for Mediatek SOCs 8 9if SOC_MEDIATEK_COMMON 10 11config MEDIATEK_DRAM_ADAPTIVE 12 bool 13 default n if SOC_MEDIATEK_MT8173 14 default n if SOC_MEDIATEK_MT8183 15 default n if SOC_MEDIATEK_MT8192 16 default y 17 help 18 Starting from MT8195, MediaTek platform supports "dram adaptive" to 19 automatically detect dram information, including channel, rank, die 20 size..., and can automatically configure EMI settings. So we can just 21 pass a placeholder param blob to `mt_mem_init_run` by enabling this 22 option. 23 Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive" 24 need to implement `get_sdram_config` to get the DRAM configuration info. 25 26config MEDIATEK_DRAM_DVFS 27 bool 28 default n 29 help 30 This option enables DRAM calibration with multiple frequencies (low, 31 medium and high frequency groups, with total 7 frequencies) for DVFS 32 feature. All supported data rates are: 800, 1200, 1600, 1866, 2400, 33 3200, 4266. 34 35config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT 36 bool 37 default y 38 depends on MEDIATEK_DRAM_DVFS 39 help 40 This options limit DRAM frequency calibration count from total 7 to 3, 41 other frequency will directly use the low frequency shu result. 42 43config MEDIATEK_DRAM_BLOB_FAST_INIT 44 bool "Enable running fast calibration by blob" 45 default n 46 help 47 This option allows performing fast calibration through different 48 open-source policy. 49 50config MEDIATEK_DRAM_SCRAMBLE 51 bool "Enable DRAM scramble feature" 52 default n 53 help 54 This option enables DRAM data scramble, which can prevent DRAM data from 55 being hacked. 56 57config MEMORY_TEST 58 bool 59 default y 60 help 61 This option enables memory basic compare test to verify the DRAM read 62 or write is as expected. 63 64config DPM_FOUR_CHANNEL 65 bool 66 default n 67 help 68 This option enables four channel configuration for DPM. 69 70config MTK_DFD 71 bool "Enable MediaTek DFD (Design For Debug) settings" 72 help 73 DFD (Design for Debug) is a debugging tool, which scans flip-flops 74 and dumps to internal RAM on the WDT reset. We reserve 1MB on DRAM 75 to store logs of DFD. 76 77config USE_CBMEM_DRAM_INFO 78 bool "Support filling dram information to cbmem" 79 help 80 The DRAM initialization will keep and return DRAM information (size, 81 geometry and other DDR info) so we can fill that into the CBMEM. 82 83config FLASH_DUAL_IO_READ 84 bool 85 default n 86 help 87 When this option is enabled, the flash controller provides the ability 88 to dual IO read mode. 89 90config PWRAP_WITH_PMIF_SPMI 91 bool 92 default n 93 help 94 When this option is enabled, the PMIC interface only supports PWRAP 95 and PMIF_SPMI. 96 97config PMIF_SPMI_IOCFG_DEFAULT_SETTING 98 bool 99 default n 100 help 101 For SoCs where IO pins default to PMIF_SPMI mode, enable this option 102 to skip software PMIF_SPMI IO pins configuration. 103 104config DEVAPC_DEBUG 105 bool 106 default n 107 help 108 When this option is enabled, the DEVAPC driver prints the settings after 109 initialization. 110 111config EARLY_MMU_INIT 112 bool 113 default n 114 help 115 When this option is enabled, `mtk_mmu_init()` will be done in 116 `bootblock_soc_early_init()` to reduce the boot time. 117 118endif 119