1 /*==============================================================================
2 Copyright(c) 2022 Intel Corporation
3
4 Permission is hereby granted, free of charge, to any person obtaining a
5 copy of this software and associated documentation files(the "Software"),
6 to deal in the Software without restriction, including without limitation
7 the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 and / or sell copies of the Software, and to permit persons to whom the
9 Software is furnished to do so, subject to the following conditions:
10
11 The above copyright notice and this permission notice shall be included
12 in all copies or substantial portions of the Software.
13
14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 OTHER DEALINGS IN THE SOFTWARE.
21 ============================================================================*/
22 #include "GmmXe_LPGCachePolicyULT.h"
23
24 using namespace std;
25
26 /////////////////////////////////////////////////////////////////////////////////////
27 /// Sets up common environment for Cache Policy fixture tests. this is called once per
28 /// test case before executing all tests under resource fixture test case.
29 /// It also calls SetupTestCase from CommonULT to initialize global context and others.
30 ///
31 /////////////////////////////////////////////////////////////////////////////////////
SetUpTestCase()32 void CTestXe_LPGCachePolicy::SetUpTestCase()
33 {
34 }
35
36 /////////////////////////////////////////////////////////////////////////////////////
37 /// cleans up once all the tests finish execution. It also calls TearDownTestCase
38 /// from CommonULT to destroy global context and others.
39 ///
40 /////////////////////////////////////////////////////////////////////////////////////
TearDownTestCase()41 void CTestXe_LPGCachePolicy::TearDownTestCase()
42 {
43 }
44
SetUpXe_LPGVariant(PRODUCT_FAMILY platform)45 void CTestXe_LPGCachePolicy::SetUpXe_LPGVariant(PRODUCT_FAMILY platform)
46 {
47 printf("%s\n", __FUNCTION__);
48
49 GfxPlatform.eProductFamily = platform;
50
51 if (platform == IGFX_LUNARLAKE)
52 {
53 GfxPlatform.eRenderCoreFamily = IGFX_XE2_LPG_CORE;
54 }
55 else if (platform >= IGFX_BMG)
56 {
57 GfxPlatform.eRenderCoreFamily = IGFX_XE2_HPG_CORE;
58 }
59 else
60 {
61 GfxPlatform.eRenderCoreFamily = IGFX_XE_HPG_CORE;
62 }
63
64 pGfxAdapterInfo = (ADAPTER_INFO *)malloc(sizeof(ADAPTER_INFO));
65 if(pGfxAdapterInfo)
66 {
67 memset(pGfxAdapterInfo, 0, sizeof(ADAPTER_INFO));
68
69 pGfxAdapterInfo->SkuTable.FtrLinearCCS = 1; //legacy y =>0 - test both
70 pGfxAdapterInfo->SkuTable.FtrStandardMipTailFormat = 1;
71 pGfxAdapterInfo->SkuTable.FtrTileY = 0;
72 pGfxAdapterInfo->SkuTable.FtrLocalMemory = 0;
73 pGfxAdapterInfo->SkuTable.FtrDiscrete = 0;
74 pGfxAdapterInfo->SkuTable.FtrIA32eGfxPTEs = 1;
75 pGfxAdapterInfo->SkuTable.FtrL4Cache = 1;
76 pGfxAdapterInfo->SkuTable.FtrL3TransientDataFlush = 0;
77
78 if (platform == IGFX_BMG)
79 {
80 pGfxAdapterInfo->SkuTable.FtrLocalMemory = 1;
81 pGfxAdapterInfo->SkuTable.FtrDiscrete = 1;
82 }
83
84 if (platform >= IGFX_BMG)
85 {
86 pGfxAdapterInfo->SkuTable.FtrL3TransientDataFlush = 1;
87 pGfxAdapterInfo->WaTable.Wa_14018976079 = 1;
88 pGfxAdapterInfo->WaTable.Wa_14018984349 = 1;
89 }
90
91 CommonULT::SetUpTestCase();
92 }
93 }
94
TearDownXe_LPGVariant()95 void CTestXe_LPGCachePolicy::TearDownXe_LPGVariant()
96 {
97 printf("%s\n", __FUNCTION__);
98
99 CommonULT::TearDownTestCase();
100 }
101
102 /***********************XeLPG***********************************/
TEST_F(CTestXe_LPGCachePolicy,TestXe_LPGCachePolicy_FtrL4CacheEnabled)103 TEST_F(CTestXe_LPGCachePolicy, TestXe_LPGCachePolicy_FtrL4CacheEnabled)
104 {
105 SetUpXe_LPGVariant(IGFX_METEORLAKE);
106 CheckVirtualL3CachePolicy();
107 CheckPAT();
108 TearDownXe_LPGVariant();
109 }
110
111 /***********************Xe2_HPG***********************************/
TEST_F(CTestXe_LPGCachePolicy,TestXe2_HPGCachePolicy_FtrL4CacheEnabled)112 TEST_F(CTestXe_LPGCachePolicy, TestXe2_HPGCachePolicy_FtrL4CacheEnabled)
113 {
114 SetUpXe_LPGVariant(IGFX_BMG);
115 CheckXe2_HPGVirtualL3CachePolicy();
116 CheckPAT(); // Has both L3 and PAT within
117 Check_Xe2_HPG_PATCompressed();
118
119 TearDownXe_LPGVariant();
120 }
TEST_F(CTestXe_LPGCachePolicy,TestXe2_LPGCachePolicy_FtrL4CacheEnabled)121 TEST_F(CTestXe_LPGCachePolicy, TestXe2_LPGCachePolicy_FtrL4CacheEnabled)
122 {
123 SetUpXe_LPGVariant(IGFX_LUNARLAKE);
124
125 CheckXe2_HPGVirtualL3CachePolicy();
126 CheckPAT(); // Has both L3 and PAT within
127 Check_Xe2_HPG_PATCompressed();
128
129 TearDownXe_LPGVariant();
130 }
CheckVirtualL3CachePolicy()131 void CTestXe_LPGCachePolicy::CheckVirtualL3CachePolicy()
132 {
133 const uint32_t L4_WB_CACHEABLE = 0x0;
134 const uint32_t L4_WT_CACHEABLE = 0x1;
135 const uint32_t L4_UNCACHEABLE = 0x3;
136
137 const uint32_t L3_WB_CACHEABLE = 0x3;
138 const uint32_t L3_UNCACHEABLE = 0x1;
139
140 for(uint32_t MocsIndex = 0; MocsIndex < GMM_XE_NUM_MOCS_ENTRIES; MocsIndex++)
141 {
142 GMM_CACHE_POLICY_TBL_ELEMENT Mocs = pGmmULTClientContext->GetCachePolicyTlbElement(MocsIndex);
143 //printf("Xe LPG: MocsIndex: %d --> Global Index: [0x%x]\n", MocsIndex, Mocs.LeCC.Xe_LPG.DwordValue);
144 //printf("Xe LPG: MocsIndex: %d --> L3 Index: [0x%x]\n", MocsIndex, Mocs.L3.UshortValue);
145 }
146
147 // Check Usage MOCS index against MOCS settings
148 for(uint32_t Usage = GMM_RESOURCE_USAGE_UNKNOWN; Usage < GMM_RESOURCE_USAGE_MAX; Usage++)
149 {
150 GMM_CACHE_POLICY_ELEMENT ClientRequest = pGmmULTClientContext->GetCachePolicyElement((GMM_RESOURCE_USAGE_TYPE)Usage);
151 uint32_t AssignedMocsIdx = ClientRequest.MemoryObjectOverride.XE_LPG.Index;
152 GMM_CACHE_POLICY_TBL_ELEMENT Mocs = pGmmULTClientContext->GetCachePolicyTlbElement(AssignedMocsIdx);
153 uint32_t StartMocsIdx = 0;
154
155 EXPECT_EQ(0, Mocs.L3.ESC) << "Usage# " << Usage << ": ESC is non-zero";
156 EXPECT_EQ(0, Mocs.L3.SCC) << "Usage# " << Usage << ": SCC is non-zero";
157 EXPECT_EQ(0, Mocs.L3.Reserved) << "Usage# " << Usage << ": Reserved field is non-zero";
158 // Check if Mocs Index is not greater than GMM_MAX_NUMBER_MOCS_INDEXES
159 EXPECT_GT(GMM_XE_NUM_MOCS_ENTRIES, AssignedMocsIdx) << "Usage# " << Usage << ": MOCS Index greater than MAX allowed (16)";
160 EXPECT_EQ(0, Mocs.LeCC.Xe_LPG.Reserved0) << "Usage# " << Usage << ": : Reserved field is non-zero";
161 EXPECT_EQ(0, Mocs.LeCC.Xe_LPG.Reserved1) << "Usage# " << Usage << ": : Reserved field is non-zero";
162 EXPECT_EQ(0, Mocs.LeCC.Xe_LPG.Reserved2) << "Usage# " << Usage << ": : Reserved field is non-zero";
163 EXPECT_EQ(0, Mocs.LeCC.Xe_LPG.Reserved3) << "Usage# " << Usage << ": : Reserved field is non-zero";
164 EXPECT_EQ(1, Mocs.LeCC.Xe_LPG.igPAT) << "Usage# " << Usage << ": Incorrect igPAT cachebility setting";
165
166 //printf("Xe LPG: Usage: %d --> Index: [%d]\n", Usage, AssignedMocsIdx);
167
168 //L3
169 if (ClientRequest.L3CC)
170 {
171 EXPECT_EQ(L3_WB_CACHEABLE, Mocs.L3.Cacheability) << "Usage# " << Usage << ": Incorrect L3 cachebility setting";
172 }
173 else
174 {
175 EXPECT_EQ(L3_UNCACHEABLE, Mocs.L3.Cacheability) << "Usage# " << Usage << ": Incorrect L3 cachebility setting";
176 }
177
178 // L4 cache memory- 0: UC, 1:WB, 2: WT
179 switch(ClientRequest.L4CC)
180 {
181 case 0x1:
182 {
183 EXPECT_EQ(L4_WB_CACHEABLE, Mocs.LeCC.Xe_LPG.L4CC) << "Usage# " << Usage << ": Incorrect L4CC cachebility setting";
184 break;
185 }
186 case 0x2:
187 {
188 EXPECT_EQ(L4_WT_CACHEABLE, Mocs.LeCC.Xe_LPG.L4CC) << "Usage# " << Usage << ": Incorrect L4CC cachebility setting";
189 break;
190 }
191 default:
192 EXPECT_EQ(L4_UNCACHEABLE, Mocs.LeCC.Xe_LPG.L4CC) << "Usage# " << Usage << ": Incorrect L4CC cachebility setting";
193 }
194 }
195 }
196
CheckPAT()197 void CTestXe_LPGCachePolicy::CheckPAT()
198 {
199
200 // Check Usage PAT index against PAT settings
201 for(uint32_t Usage = GMM_RESOURCE_USAGE_UNKNOWN; Usage < GMM_RESOURCE_USAGE_MAX; Usage++)
202 {
203 GMM_CACHE_POLICY_ELEMENT ClientRequest = pGmmULTClientContext->GetCachePolicyElement((GMM_RESOURCE_USAGE_TYPE)Usage);
204 if(ClientRequest.Initialized == false) // undefined resource in platform
205 {
206 continue;
207 }
208 uint32_t PATIndex = pGmmULTClientContext->CachePolicyGetPATIndex(NULL, (GMM_RESOURCE_USAGE_TYPE)Usage, NULL, false);
209 EXPECT_NE(PATIndex, GMM_PAT_ERROR) << "Usage# " << Usage << ": No matching PAT Index";
210 }
211 }
212
Check_Xe2_HPG_PATCompressed()213 void CTestXe_LPGCachePolicy::Check_Xe2_HPG_PATCompressed()
214 {
215 bool CompressionEnReq = true;
216
217 // Check Usage PAT index against PAT settings
218 for (uint32_t Usage = GMM_RESOURCE_USAGE_UNKNOWN; Usage < GMM_RESOURCE_USAGE_MAX; Usage++)
219 {
220 GMM_CACHE_POLICY_ELEMENT ClientRequest = pGmmULTClientContext->GetCachePolicyElement((GMM_RESOURCE_USAGE_TYPE)Usage);
221 CompressionEnReq = true;
222 if (ClientRequest.Initialized == false) // undefined resource in platform
223 {
224 continue;
225 }
226 uint32_t PATIndex = pGmmULTClientContext->CachePolicyGetPATIndex(NULL, (GMM_RESOURCE_USAGE_TYPE)Usage, &CompressionEnReq, false);
227 //printf("Xe HPG: Usage: %d --> Compressed PAT Index: [%d], ComEn: [%d]\n", Usage, PATIndex, CompressionEnReq);
228 EXPECT_NE(PATIndex, GMM_PAT_ERROR) << "Usage# " << Usage << ": No matching PAT Index";
229 }
230 }
231
CheckXe2_HPGVirtualL3CachePolicy()232 void CTestXe_LPGCachePolicy::CheckXe2_HPGVirtualL3CachePolicy()
233 {
234 const uint32_t L4_WB_CACHEABLE = 0x0;
235 const uint32_t L4_WT_CACHEABLE = 0x1;
236 const uint32_t L4_UNCACHEABLE = 0x3;
237
238 const uint32_t L3_WB_CACHEABLE = 0x0;
239 const uint32_t L3_XD_CACHEABLE = pGmmULTClientContext->GetSkuTable().FtrL3TransientDataFlush ? 0x1 : 0x0;
240 const uint32_t L3_UNCACHEABLE = 0x3;
241
242 // Check Usage MOCS index against MOCS settings
243 for (uint32_t Usage = GMM_RESOURCE_USAGE_UNKNOWN; Usage < GMM_RESOURCE_USAGE_MAX; Usage++)
244 {
245 GMM_CACHE_POLICY_ELEMENT ClientRequest = pGmmULTClientContext->GetCachePolicyElement((GMM_RESOURCE_USAGE_TYPE)Usage);
246 uint32_t AssignedMocsIdx = ClientRequest.MemoryObjectOverride.XE_HP.Index;
247 GMM_CACHE_POLICY_TBL_ELEMENT Mocs = pGmmULTClientContext->GetCachePolicyTlbElement(AssignedMocsIdx);
248 uint32_t StartMocsIdx = 0;
249
250 EXPECT_EQ(0, Mocs.L3.PhysicalL3.Reserved) << "Usage# " << Usage << ": Reserved field is non-zero";
251 EXPECT_EQ(0, Mocs.L3.PhysicalL3.Reserved0) << "Usage# " << Usage << ": Reserved field is non-zero";
252 EXPECT_EQ(0, Mocs.L3.PhysicalL3.L3CLOS) << "Usage# " << Usage << ": L3CLOS field is non-zero";
253 // Check if Mocs Index is not greater than GMM_MAX_NUMBER_MOCS_INDEXES
254 EXPECT_GT(GMM_XE2_NUM_MOCS_ENTRIES, AssignedMocsIdx) << "Usage# " << Usage << ": MOCS Index greater than MAX allowed (16)";
255
256 //printf("Xe HPG: Usage: %d --> Index: [%d]\n", Usage, AssignedMocsIdx);
257
258 if (ClientRequest.IgnorePAT == true)
259 {
260 EXPECT_EQ(1, Mocs.L3.PhysicalL3.igPAT) << "Usage# " << Usage << ": Incorrect igPAT cachebility setting";
261
262 // L4 memory cache 0: UC, 1:WB, 2: WT
263 switch (ClientRequest.L4CC)
264 {
265 case 0x1:
266 {
267 EXPECT_EQ(L4_WB_CACHEABLE, Mocs.L3.PhysicalL3.L4CC) << "Usage# " << Usage << ": Incorrect L4CC cachebility setting";
268 break;
269 }
270 case 0x2:
271 {
272 EXPECT_EQ(L4_WT_CACHEABLE, Mocs.L3.PhysicalL3.L4CC) << "Usage# " << Usage << ": Incorrect L4CC cachebility setting";
273 break;
274 }
275 default:
276 EXPECT_EQ(L4_UNCACHEABLE, Mocs.L3.PhysicalL3.L4CC) << "Usage# " << Usage << ": Incorrect L4CC cachebility setting";
277 }
278
279 // 0:UC, 1:WB 2:WB_T_Display, 3:WB_T_App
280 switch (ClientRequest.L3CC)
281 {
282
283 case 0x1:
284 EXPECT_EQ(L3_WB_CACHEABLE, Mocs.L3.PhysicalL3.L3CC) << "Usage# " << Usage << ": Incorrect L3CC cachebility setting";
285 break;
286 case 0x3:
287 {
288 EXPECT_EQ(L3_XD_CACHEABLE, Mocs.L3.PhysicalL3.L3CC) << "Usage# " << Usage << ": Incorrect L3CC cachebility setting";
289 break;
290 }
291 default:
292 EXPECT_EQ(L3_UNCACHEABLE, Mocs.L3.PhysicalL3.L3CC) << "Usage# " << Usage << ": Incorrect L3CC cachebility setting";
293 }
294 }
295 else
296 {
297 EXPECT_EQ(0, Mocs.L3.PhysicalL3.igPAT) << "Usage# " << Usage << ": Incorrect igPAT cachebility setting";
298 }
299 }
300 }
301