1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for Exception vector offsets 79 ******************************************************************************/ 80 #define CURRENT_EL_SP0 0x0 81 #define CURRENT_EL_SPX 0x200 82 #define LOWER_EL_AARCH64 0x400 83 #define LOWER_EL_AARCH32 0x600 84 85 #define SYNC_EXCEPTION 0x0 86 #define IRQ_EXCEPTION 0x80 87 #define FIQ_EXCEPTION 0x100 88 #define SERROR_EXCEPTION 0x180 89 90 /******************************************************************************* 91 * Definitions for CPU system register interface to GICv3 92 ******************************************************************************/ 93 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 94 #define ICC_SGI1R S3_0_C12_C11_5 95 #define ICC_ASGI1R S3_0_C12_C11_6 96 #define ICC_SRE_EL1 S3_0_C12_C12_5 97 #define ICC_SRE_EL2 S3_4_C12_C9_5 98 #define ICC_SRE_EL3 S3_6_C12_C12_5 99 #define ICC_CTLR_EL1 S3_0_C12_C12_4 100 #define ICC_CTLR_EL3 S3_6_C12_C12_4 101 #define ICC_PMR_EL1 S3_0_C4_C6_0 102 #define ICC_RPR_EL1 S3_0_C12_C11_3 103 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 104 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 105 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 106 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 107 #define ICC_IAR0_EL1 S3_0_c12_c8_0 108 #define ICC_IAR1_EL1 S3_0_c12_c12_0 109 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 110 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 111 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 112 113 /******************************************************************************* 114 * Definitions for EL2 system registers for save/restore routine 115 ******************************************************************************/ 116 #define CNTPOFF_EL2 S3_4_C14_C0_6 117 #define HAFGRTR_EL2 S3_4_C3_C1_6 118 #define HDFGRTR_EL2 S3_4_C3_C1_4 119 #define HDFGWTR_EL2 S3_4_C3_C1_5 120 #define HFGITR_EL2 S3_4_C1_C1_6 121 #define HFGRTR_EL2 S3_4_C1_C1_4 122 #define HFGWTR_EL2 S3_4_C1_C1_5 123 #define ICH_HCR_EL2 S3_4_C12_C11_0 124 #define ICH_VMCR_EL2 S3_4_C12_C11_7 125 #define MPAMVPM0_EL2 S3_4_C10_C6_0 126 #define MPAMVPM1_EL2 S3_4_C10_C6_1 127 #define MPAMVPM2_EL2 S3_4_C10_C6_2 128 #define MPAMVPM3_EL2 S3_4_C10_C6_3 129 #define MPAMVPM4_EL2 S3_4_C10_C6_4 130 #define MPAMVPM5_EL2 S3_4_C10_C6_5 131 #define MPAMVPM6_EL2 S3_4_C10_C6_6 132 #define MPAMVPM7_EL2 S3_4_C10_C6_7 133 #define MPAMVPMV_EL2 S3_4_C10_C4_1 134 #define VNCR_EL2 S3_4_C2_C2_0 135 #define PMSCR_EL2 S3_4_C9_C9_0 136 #define TFSR_EL2 S3_4_C5_C6_0 137 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 138 #define TTBR1_EL2 S3_4_C2_C0_1 139 140 /******************************************************************************* 141 * Generic timer memory mapped registers & offsets 142 ******************************************************************************/ 143 #define CNTCR_OFF U(0x000) 144 #define CNTCV_OFF U(0x008) 145 #define CNTFID_OFF U(0x020) 146 147 #define CNTCR_EN (U(1) << 0) 148 #define CNTCR_HDBG (U(1) << 1) 149 #define CNTCR_FCREQ(x) ((x) << 8) 150 151 /******************************************************************************* 152 * System register bit definitions 153 ******************************************************************************/ 154 /* CLIDR definitions */ 155 #define LOUIS_SHIFT U(21) 156 #define LOC_SHIFT U(24) 157 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 158 #define CLIDR_FIELD_WIDTH U(3) 159 160 /* CSSELR definitions */ 161 #define LEVEL_SHIFT U(1) 162 163 /* Data cache set/way op type defines */ 164 #define DCISW U(0x0) 165 #define DCCISW U(0x1) 166 #if ERRATA_A53_827319 167 #define DCCSW DCCISW 168 #else 169 #define DCCSW U(0x2) 170 #endif 171 172 #define ID_REG_FIELD_MASK ULL(0xf) 173 174 /* ID_AA64PFR0_EL1 definitions */ 175 #define ID_AA64PFR0_EL0_SHIFT U(0) 176 #define ID_AA64PFR0_EL1_SHIFT U(4) 177 #define ID_AA64PFR0_EL2_SHIFT U(8) 178 #define ID_AA64PFR0_EL3_SHIFT U(12) 179 180 #define ID_AA64PFR0_AMU_SHIFT U(44) 181 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 182 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 183 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 184 185 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 186 187 #define ID_AA64PFR0_GIC_SHIFT U(24) 188 #define ID_AA64PFR0_GIC_WIDTH U(4) 189 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 190 191 #define ID_AA64PFR0_SVE_SHIFT U(32) 192 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 193 #define ID_AA64PFR0_SVE_LENGTH U(4) 194 #define SVE_IMPLEMENTED ULL(0x1) 195 196 #define ID_AA64PFR0_SEL2_SHIFT U(36) 197 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 198 199 #define ID_AA64PFR0_MPAM_SHIFT U(40) 200 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 201 202 #define ID_AA64PFR0_DIT_SHIFT U(48) 203 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 204 #define ID_AA64PFR0_DIT_LENGTH U(4) 205 #define DIT_IMPLEMENTED ULL(1) 206 207 #define ID_AA64PFR0_CSV2_SHIFT U(56) 208 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 209 #define ID_AA64PFR0_CSV2_LENGTH U(4) 210 #define CSV2_2_IMPLEMENTED ULL(0x2) 211 #define CSV2_3_IMPLEMENTED ULL(0x3) 212 213 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 214 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 215 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 216 #define RME_NOT_IMPLEMENTED ULL(0) 217 218 #define ID_AA64PFR0_RAS_SHIFT U(28) 219 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 220 #define ID_AA64PFR0_RAS_LENGTH U(4) 221 222 /* Exception level handling */ 223 #define EL_IMPL_NONE ULL(0) 224 #define EL_IMPL_A64ONLY ULL(1) 225 #define EL_IMPL_A64_A32 ULL(2) 226 227 /* ID_AA64DFR0_EL1.TraceVer definitions */ 228 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 229 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 230 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 231 232 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 233 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 234 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 235 #define TRACEFILT_IMPLEMENTED ULL(1) 236 237 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 238 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 239 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 240 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 241 #define ID_AA64DFR0_PMUVER_PMUV3P7 U(7) 242 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 243 244 /* ID_AA64DFR0_EL1.SEBEP definitions */ 245 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 246 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 247 #define SEBEP_IMPLEMENTED ULL(1) 248 249 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 250 #define ID_AA64DFR0_PMS_SHIFT U(32) 251 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 252 #define SPE_IMPLEMENTED ULL(0x1) 253 #define SPE_NOT_IMPLEMENTED ULL(0x0) 254 255 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 256 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 257 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 258 #define TRACEBUFFER_IMPLEMENTED ULL(1) 259 260 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 261 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 262 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 263 #define MTPMU_IMPLEMENTED ULL(1) 264 #define MTPMU_NOT_IMPLEMENTED ULL(15) 265 266 /* ID_AA64DFR0_EL1.BRBE definitions */ 267 #define ID_AA64DFR0_BRBE_SHIFT U(52) 268 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 269 #define BRBE_IMPLEMENTED ULL(1) 270 271 /* ID_AA64DFR1_EL1 definitions */ 272 #define ID_AA64DFR1_EBEP_SHIFT U(48) 273 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 274 #define EBEP_IMPLEMENTED ULL(1) 275 276 /* ID_AA64ISAR0_EL1 definitions */ 277 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 278 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 279 280 /* ID_AA64ISAR1_EL1 definitions */ 281 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 282 283 #define ID_AA64ISAR1_GPI_SHIFT U(28) 284 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 285 #define ID_AA64ISAR1_GPA_SHIFT U(24) 286 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 287 288 #define ID_AA64ISAR1_API_SHIFT U(8) 289 #define ID_AA64ISAR1_API_MASK ULL(0xf) 290 #define ID_AA64ISAR1_APA_SHIFT U(4) 291 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 292 293 #define ID_AA64ISAR1_SB_SHIFT U(36) 294 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 295 #define SB_IMPLEMENTED ULL(0x1) 296 #define SB_NOT_IMPLEMENTED ULL(0x0) 297 298 /* ID_AA64ISAR2_EL1 definitions */ 299 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 300 301 /* ID_AA64PFR2_EL1 definitions */ 302 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 303 304 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 305 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 306 307 #define ID_AA64ISAR2_APA3_SHIFT U(12) 308 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 309 310 /* ID_AA64MMFR0_EL1 definitions */ 311 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 312 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 313 314 #define PARANGE_0000 U(32) 315 #define PARANGE_0001 U(36) 316 #define PARANGE_0010 U(40) 317 #define PARANGE_0011 U(42) 318 #define PARANGE_0100 U(44) 319 #define PARANGE_0101 U(48) 320 #define PARANGE_0110 U(52) 321 322 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 323 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 324 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 325 #define ECV_IMPLEMENTED ULL(0x1) 326 327 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 328 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 329 #define FGT_IMPLEMENTED ULL(0x1) 330 #define FGT_NOT_IMPLEMENTED ULL(0x0) 331 332 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 333 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 334 335 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 336 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 337 338 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 339 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 340 #define TGRAN16_IMPLEMENTED ULL(0x1) 341 342 /* ID_AA64MMFR1_EL1 definitions */ 343 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 344 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 345 #define TWED_IMPLEMENTED ULL(0x1) 346 347 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 348 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 349 #define PAN_IMPLEMENTED ULL(0x1) 350 #define PAN2_IMPLEMENTED ULL(0x2) 351 #define PAN3_IMPLEMENTED ULL(0x3) 352 353 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 354 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 355 356 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 357 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 358 #define HCX_IMPLEMENTED ULL(0x1) 359 360 /* ID_AA64MMFR2_EL1 definitions */ 361 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 362 363 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 364 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 365 366 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 367 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 368 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 369 370 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 371 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 372 373 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 374 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 375 376 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 377 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 378 #define NV2_IMPLEMENTED ULL(0x2) 379 380 /* ID_AA64MMFR3_EL1 definitions */ 381 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 382 383 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 384 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 385 386 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 387 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 388 389 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 390 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 391 392 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 393 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 394 395 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 396 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 397 398 /* ID_AA64PFR1_EL1 definitions */ 399 400 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 401 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 402 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 403 404 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 405 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 406 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 407 408 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 409 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 410 411 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 412 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 413 414 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 415 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 416 #define NMI_IMPLEMENTED ULL(1) 417 418 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 419 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 420 #define GCS_IMPLEMENTED ULL(1) 421 422 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 423 424 /* ID_AA64PFR2_EL1 definitions */ 425 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 426 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 427 428 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 429 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 430 431 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 432 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 433 434 #define VDISR_EL2 S3_4_C12_C1_1 435 #define VSESR_EL2 S3_4_C5_C2_3 436 437 /* Memory Tagging Extension is not implemented */ 438 #define MTE_UNIMPLEMENTED U(0) 439 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 440 #define MTE_IMPLEMENTED_EL0 U(1) 441 /* FEAT_MTE2: Full MTE is implemented */ 442 #define MTE_IMPLEMENTED_ELX U(2) 443 /* 444 * FEAT_MTE3: MTE is implemented with support for 445 * asymmetric Tag Check Fault handling 446 */ 447 #define MTE_IMPLEMENTED_ASY U(3) 448 449 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 450 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 451 452 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 453 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 454 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 455 #define SME_IMPLEMENTED ULL(0x1) 456 #define SME2_IMPLEMENTED ULL(0x2) 457 #define SME_NOT_IMPLEMENTED ULL(0x0) 458 459 /* ID_PFR1_EL1 definitions */ 460 #define ID_PFR1_VIRTEXT_SHIFT U(12) 461 #define ID_PFR1_VIRTEXT_MASK U(0xf) 462 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 463 & ID_PFR1_VIRTEXT_MASK) 464 465 /* SCTLR definitions */ 466 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 467 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 468 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 469 470 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 471 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 472 473 #define SCTLR_AARCH32_EL1_RES1 \ 474 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 475 (U(1) << 4) | (U(1) << 3)) 476 477 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 478 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 479 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 480 481 #define SCTLR_M_BIT (ULL(1) << 0) 482 #define SCTLR_A_BIT (ULL(1) << 1) 483 #define SCTLR_C_BIT (ULL(1) << 2) 484 #define SCTLR_SA_BIT (ULL(1) << 3) 485 #define SCTLR_SA0_BIT (ULL(1) << 4) 486 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 487 #define SCTLR_nAA_BIT (ULL(1) << 6) 488 #define SCTLR_ITD_BIT (ULL(1) << 7) 489 #define SCTLR_SED_BIT (ULL(1) << 8) 490 #define SCTLR_UMA_BIT (ULL(1) << 9) 491 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 492 #define SCTLR_EOS_BIT (ULL(1) << 11) 493 #define SCTLR_I_BIT (ULL(1) << 12) 494 #define SCTLR_EnDB_BIT (ULL(1) << 13) 495 #define SCTLR_DZE_BIT (ULL(1) << 14) 496 #define SCTLR_UCT_BIT (ULL(1) << 15) 497 #define SCTLR_NTWI_BIT (ULL(1) << 16) 498 #define SCTLR_NTWE_BIT (ULL(1) << 18) 499 #define SCTLR_WXN_BIT (ULL(1) << 19) 500 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 501 #define SCTLR_IESB_BIT (ULL(1) << 21) 502 #define SCTLR_EIS_BIT (ULL(1) << 22) 503 #define SCTLR_SPAN_BIT (ULL(1) << 23) 504 #define SCTLR_E0E_BIT (ULL(1) << 24) 505 #define SCTLR_EE_BIT (ULL(1) << 25) 506 #define SCTLR_UCI_BIT (ULL(1) << 26) 507 #define SCTLR_EnDA_BIT (ULL(1) << 27) 508 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 509 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 510 #define SCTLR_EnIB_BIT (ULL(1) << 30) 511 #define SCTLR_EnIA_BIT (ULL(1) << 31) 512 #define SCTLR_BT0_BIT (ULL(1) << 35) 513 #define SCTLR_BT1_BIT (ULL(1) << 36) 514 #define SCTLR_BT_BIT (ULL(1) << 36) 515 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 516 #define SCTLR_TCF0_SHIFT U(38) 517 #define SCTLR_TCF0_MASK ULL(3) 518 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 519 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 520 521 /* Tag Check Faults in EL0 have no effect on the PE */ 522 #define SCTLR_TCF0_NO_EFFECT U(0) 523 /* Tag Check Faults in EL0 cause a synchronous exception */ 524 #define SCTLR_TCF0_SYNC U(1) 525 /* Tag Check Faults in EL0 are asynchronously accumulated */ 526 #define SCTLR_TCF0_ASYNC U(2) 527 /* 528 * Tag Check Faults in EL0 cause a synchronous exception on reads, 529 * and are asynchronously accumulated on writes 530 */ 531 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 532 533 #define SCTLR_TCF_SHIFT U(40) 534 #define SCTLR_TCF_MASK ULL(3) 535 536 /* Tag Check Faults in EL1 have no effect on the PE */ 537 #define SCTLR_TCF_NO_EFFECT U(0) 538 /* Tag Check Faults in EL1 cause a synchronous exception */ 539 #define SCTLR_TCF_SYNC U(1) 540 /* Tag Check Faults in EL1 are asynchronously accumulated */ 541 #define SCTLR_TCF_ASYNC U(2) 542 /* 543 * Tag Check Faults in EL1 cause a synchronous exception on reads, 544 * and are asynchronously accumulated on writes 545 */ 546 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 547 548 #define SCTLR_ATA0_BIT (ULL(1) << 42) 549 #define SCTLR_ATA_BIT (ULL(1) << 43) 550 #define SCTLR_DSSBS_SHIFT U(44) 551 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 552 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 553 #define SCTLR_TWEDEL_SHIFT U(46) 554 #define SCTLR_TWEDEL_MASK ULL(0xf) 555 #define SCTLR_EnASR_BIT (ULL(1) << 54) 556 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 557 #define SCTLR_EnALS_BIT (ULL(1) << 56) 558 #define SCTLR_EPAN_BIT (ULL(1) << 57) 559 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 560 561 /* CPACR_EL1 definitions */ 562 #define CPACR_EL1_FPEN(x) ((x) << 20) 563 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 564 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 565 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 566 #define CPACR_EL1_SMEN_SHIFT U(24) 567 #define CPACR_EL1_SMEN_MASK ULL(0x3) 568 569 /* SCR definitions */ 570 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 571 #define SCR_NSE_SHIFT U(62) 572 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 573 #define SCR_GPF_BIT (UL(1) << 48) 574 #define SCR_TWEDEL_SHIFT U(30) 575 #define SCR_TWEDEL_MASK ULL(0xf) 576 #define SCR_PIEN_BIT (UL(1) << 45) 577 #define SCR_TCR2EN_BIT (UL(1) << 43) 578 #define SCR_TRNDR_BIT (UL(1) << 40) 579 #define SCR_GCSEn_BIT (UL(1) << 39) 580 #define SCR_HXEn_BIT (UL(1) << 38) 581 #define SCR_ENTP2_SHIFT U(41) 582 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 583 #define SCR_AMVOFFEN_SHIFT U(35) 584 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 585 #define SCR_TWEDEn_BIT (UL(1) << 29) 586 #define SCR_ECVEN_BIT (UL(1) << 28) 587 #define SCR_FGTEN_BIT (UL(1) << 27) 588 #define SCR_ATA_BIT (UL(1) << 26) 589 #define SCR_EnSCXT_BIT (UL(1) << 25) 590 #define SCR_FIEN_BIT (UL(1) << 21) 591 #define SCR_EEL2_BIT (UL(1) << 18) 592 #define SCR_API_BIT (UL(1) << 17) 593 #define SCR_APK_BIT (UL(1) << 16) 594 #define SCR_TERR_BIT (UL(1) << 15) 595 #define SCR_TWE_BIT (UL(1) << 13) 596 #define SCR_TWI_BIT (UL(1) << 12) 597 #define SCR_ST_BIT (UL(1) << 11) 598 #define SCR_RW_BIT (UL(1) << 10) 599 #define SCR_SIF_BIT (UL(1) << 9) 600 #define SCR_HCE_BIT (UL(1) << 8) 601 #define SCR_SMD_BIT (UL(1) << 7) 602 #define SCR_EA_BIT (UL(1) << 3) 603 #define SCR_FIQ_BIT (UL(1) << 2) 604 #define SCR_IRQ_BIT (UL(1) << 1) 605 #define SCR_NS_BIT (UL(1) << 0) 606 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 607 #define SCR_RESET_VAL SCR_RES1_BITS 608 609 /* MDCR_EL3 definitions */ 610 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 611 #define MDCR_MPMX_BIT (ULL(1) << 35) 612 #define MDCR_MCCD_BIT (ULL(1) << 34) 613 #define MDCR_SBRBE_SHIFT U(32) 614 #define MDCR_SBRBE_MASK ULL(0x3) 615 #define MDCR_NSTB(x) ((x) << 24) 616 #define MDCR_NSTB_EL1 ULL(0x3) 617 #define MDCR_NSTBE_BIT (ULL(1) << 26) 618 #define MDCR_MTPME_BIT (ULL(1) << 28) 619 #define MDCR_TDCC_BIT (ULL(1) << 27) 620 #define MDCR_SCCD_BIT (ULL(1) << 23) 621 #define MDCR_EPMAD_BIT (ULL(1) << 21) 622 #define MDCR_EDAD_BIT (ULL(1) << 20) 623 #define MDCR_TTRF_BIT (ULL(1) << 19) 624 #define MDCR_STE_BIT (ULL(1) << 18) 625 #define MDCR_SPME_BIT (ULL(1) << 17) 626 #define MDCR_SDD_BIT (ULL(1) << 16) 627 #define MDCR_SPD32(x) ((x) << 14) 628 #define MDCR_SPD32_LEGACY ULL(0x0) 629 #define MDCR_SPD32_DISABLE ULL(0x2) 630 #define MDCR_SPD32_ENABLE ULL(0x3) 631 #define MDCR_NSPB(x) ((x) << 12) 632 #define MDCR_NSPB_EL1 ULL(0x3) 633 #define MDCR_NSPBE_BIT (ULL(1) << 11) 634 #define MDCR_TDOSA_BIT (ULL(1) << 10) 635 #define MDCR_TDA_BIT (ULL(1) << 9) 636 #define MDCR_TPM_BIT (ULL(1) << 6) 637 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 638 639 /* MDCR_EL2 definitions */ 640 #define MDCR_EL2_MTPME (U(1) << 28) 641 #define MDCR_EL2_HLP_BIT (U(1) << 26) 642 #define MDCR_EL2_E2TB(x) ((x) << 24) 643 #define MDCR_EL2_E2TB_EL1 U(0x3) 644 #define MDCR_EL2_HCCD_BIT (U(1) << 23) 645 #define MDCR_EL2_TTRF (U(1) << 19) 646 #define MDCR_EL2_HPMD_BIT (U(1) << 17) 647 #define MDCR_EL2_TPMS (U(1) << 14) 648 #define MDCR_EL2_E2PB(x) ((x) << 12) 649 #define MDCR_EL2_E2PB_EL1 U(0x3) 650 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 651 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 652 #define MDCR_EL2_TDA_BIT (U(1) << 9) 653 #define MDCR_EL2_TDE_BIT (U(1) << 8) 654 #define MDCR_EL2_HPME_BIT (U(1) << 7) 655 #define MDCR_EL2_TPM_BIT (U(1) << 6) 656 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 657 #define MDCR_EL2_HPMN_MASK U(0x1f) 658 #define MDCR_EL2_RESET_VAL U(0x0) 659 660 /* HSTR_EL2 definitions */ 661 #define HSTR_EL2_RESET_VAL U(0x0) 662 #define HSTR_EL2_T_MASK U(0xff) 663 664 /* CNTHP_CTL_EL2 definitions */ 665 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 666 #define CNTHP_CTL_RESET_VAL U(0x0) 667 668 /* VTTBR_EL2 definitions */ 669 #define VTTBR_RESET_VAL ULL(0x0) 670 #define VTTBR_VMID_MASK ULL(0xff) 671 #define VTTBR_VMID_SHIFT U(48) 672 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 673 #define VTTBR_BADDR_SHIFT U(0) 674 675 /* HCR definitions */ 676 #define HCR_RESET_VAL ULL(0x0) 677 #define HCR_AMVOFFEN_SHIFT U(51) 678 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 679 #define HCR_TEA_BIT (ULL(1) << 47) 680 #define HCR_API_BIT (ULL(1) << 41) 681 #define HCR_APK_BIT (ULL(1) << 40) 682 #define HCR_E2H_BIT (ULL(1) << 34) 683 #define HCR_HCD_BIT (ULL(1) << 29) 684 #define HCR_TGE_BIT (ULL(1) << 27) 685 #define HCR_RW_SHIFT U(31) 686 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 687 #define HCR_TWE_BIT (ULL(1) << 14) 688 #define HCR_TWI_BIT (ULL(1) << 13) 689 #define HCR_AMO_BIT (ULL(1) << 5) 690 #define HCR_IMO_BIT (ULL(1) << 4) 691 #define HCR_FMO_BIT (ULL(1) << 3) 692 693 /* ISR definitions */ 694 #define ISR_A_SHIFT U(8) 695 #define ISR_I_SHIFT U(7) 696 #define ISR_F_SHIFT U(6) 697 698 /* CNTHCTL_EL2 definitions */ 699 #define CNTHCTL_RESET_VAL U(0x0) 700 #define EVNTEN_BIT (U(1) << 2) 701 #define EL1PCEN_BIT (U(1) << 1) 702 #define EL1PCTEN_BIT (U(1) << 0) 703 704 /* CNTKCTL_EL1 definitions */ 705 #define EL0PTEN_BIT (U(1) << 9) 706 #define EL0VTEN_BIT (U(1) << 8) 707 #define EL0PCTEN_BIT (U(1) << 0) 708 #define EL0VCTEN_BIT (U(1) << 1) 709 #define EVNTEN_BIT (U(1) << 2) 710 #define EVNTDIR_BIT (U(1) << 3) 711 #define EVNTI_SHIFT U(4) 712 #define EVNTI_MASK U(0xf) 713 714 /* CPTR_EL3 definitions */ 715 #define TCPAC_BIT (U(1) << 31) 716 #define TAM_SHIFT U(30) 717 #define TAM_BIT (U(1) << TAM_SHIFT) 718 #define TTA_BIT (U(1) << 20) 719 #define ESM_BIT (U(1) << 12) 720 #define TFP_BIT (U(1) << 10) 721 #define CPTR_EZ_BIT (U(1) << 8) 722 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 723 ~(CPTR_EZ_BIT | ESM_BIT)) 724 725 /* CPTR_EL2 definitions */ 726 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 727 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 728 #define CPTR_EL2_TAM_SHIFT U(30) 729 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 730 #define CPTR_EL2_SMEN_MASK ULL(0x3) 731 #define CPTR_EL2_SMEN_SHIFT U(24) 732 #define CPTR_EL2_TTA_BIT (U(1) << 20) 733 #define CPTR_EL2_TSM_BIT (U(1) << 12) 734 #define CPTR_EL2_TFP_BIT (U(1) << 10) 735 #define CPTR_EL2_TZ_BIT (U(1) << 8) 736 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 737 738 /* VTCR_EL2 definitions */ 739 #define VTCR_RESET_VAL U(0x0) 740 #define VTCR_EL2_MSA (U(1) << 31) 741 742 /* CPSR/SPSR definitions */ 743 #define DAIF_FIQ_BIT (U(1) << 0) 744 #define DAIF_IRQ_BIT (U(1) << 1) 745 #define DAIF_ABT_BIT (U(1) << 2) 746 #define DAIF_DBG_BIT (U(1) << 3) 747 #define SPSR_V_BIT (U(1) << 28) 748 #define SPSR_C_BIT (U(1) << 29) 749 #define SPSR_Z_BIT (U(1) << 30) 750 #define SPSR_N_BIT (U(1) << 31) 751 #define SPSR_DAIF_SHIFT U(6) 752 #define SPSR_DAIF_MASK U(0xf) 753 754 #define SPSR_AIF_SHIFT U(6) 755 #define SPSR_AIF_MASK U(0x7) 756 757 #define SPSR_E_SHIFT U(9) 758 #define SPSR_E_MASK U(0x1) 759 #define SPSR_E_LITTLE U(0x0) 760 #define SPSR_E_BIG U(0x1) 761 762 #define SPSR_T_SHIFT U(5) 763 #define SPSR_T_MASK U(0x1) 764 #define SPSR_T_ARM U(0x0) 765 #define SPSR_T_THUMB U(0x1) 766 767 #define SPSR_M_SHIFT U(4) 768 #define SPSR_M_MASK U(0x1) 769 #define SPSR_M_AARCH64 U(0x0) 770 #define SPSR_M_AARCH32 U(0x1) 771 #define SPSR_M_EL1H U(0x5) 772 #define SPSR_M_EL2H U(0x9) 773 774 #define SPSR_EL_SHIFT U(2) 775 #define SPSR_EL_WIDTH U(2) 776 777 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 778 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 779 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 780 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 781 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 782 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 783 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 784 #define SPSR_IL_BIT BIT_64(20) 785 #define SPSR_SS_BIT BIT_64(21) 786 #define SPSR_PAN_BIT BIT_64(22) 787 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 788 #define SPSR_DIT_BIT BIT(24) 789 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 790 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 791 #define SPSR_PPEND_BIT BIT(33) 792 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 793 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 794 795 #define DISABLE_ALL_EXCEPTIONS \ 796 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 797 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 798 799 /* 800 * RMR_EL3 definitions 801 */ 802 #define RMR_EL3_RR_BIT (U(1) << 1) 803 #define RMR_EL3_AA64_BIT (U(1) << 0) 804 805 /* 806 * HI-VECTOR address for AArch32 state 807 */ 808 #define HI_VECTOR_BASE U(0xFFFF0000) 809 810 /* 811 * TCR definitions 812 */ 813 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 814 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 815 #define TCR_EL1_IPS_SHIFT U(32) 816 #define TCR_EL2_PS_SHIFT U(16) 817 #define TCR_EL3_PS_SHIFT U(16) 818 819 #define TCR_TxSZ_MIN ULL(16) 820 #define TCR_TxSZ_MAX ULL(39) 821 #define TCR_TxSZ_MAX_TTST ULL(48) 822 823 #define TCR_T0SZ_SHIFT U(0) 824 #define TCR_T1SZ_SHIFT U(16) 825 826 /* (internal) physical address size bits in EL3/EL1 */ 827 #define TCR_PS_BITS_4GB ULL(0x0) 828 #define TCR_PS_BITS_64GB ULL(0x1) 829 #define TCR_PS_BITS_1TB ULL(0x2) 830 #define TCR_PS_BITS_4TB ULL(0x3) 831 #define TCR_PS_BITS_16TB ULL(0x4) 832 #define TCR_PS_BITS_256TB ULL(0x5) 833 834 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 835 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 836 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 837 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 838 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 839 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 840 841 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 842 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 843 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 844 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 845 846 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 847 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 848 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 849 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 850 851 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 852 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 853 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 854 855 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 856 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 857 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 858 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 859 860 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 861 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 862 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 863 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 864 865 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 866 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 867 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 868 869 #define TCR_TG0_SHIFT U(14) 870 #define TCR_TG0_MASK ULL(3) 871 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 872 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 873 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 874 875 #define TCR_TG1_SHIFT U(30) 876 #define TCR_TG1_MASK ULL(3) 877 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 878 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 879 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 880 881 #define TCR_EPD0_BIT (ULL(1) << 7) 882 #define TCR_EPD1_BIT (ULL(1) << 23) 883 884 #define MODE_SP_SHIFT U(0x0) 885 #define MODE_SP_MASK U(0x1) 886 #define MODE_SP_EL0 U(0x0) 887 #define MODE_SP_ELX U(0x1) 888 889 #define MODE_RW_SHIFT U(0x4) 890 #define MODE_RW_MASK U(0x1) 891 #define MODE_RW_64 U(0x0) 892 #define MODE_RW_32 U(0x1) 893 894 #define MODE_EL_SHIFT U(0x2) 895 #define MODE_EL_MASK U(0x3) 896 #define MODE_EL_WIDTH U(0x2) 897 #define MODE_EL3 U(0x3) 898 #define MODE_EL2 U(0x2) 899 #define MODE_EL1 U(0x1) 900 #define MODE_EL0 U(0x0) 901 902 #define MODE32_SHIFT U(0) 903 #define MODE32_MASK U(0xf) 904 #define MODE32_usr U(0x0) 905 #define MODE32_fiq U(0x1) 906 #define MODE32_irq U(0x2) 907 #define MODE32_svc U(0x3) 908 #define MODE32_mon U(0x6) 909 #define MODE32_abt U(0x7) 910 #define MODE32_hyp U(0xa) 911 #define MODE32_und U(0xb) 912 #define MODE32_sys U(0xf) 913 914 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 915 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 916 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 917 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 918 919 #define SPSR_64(el, sp, daif) \ 920 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 921 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 922 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 923 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 924 (~(SPSR_SSBS_BIT_AARCH64))) 925 926 #define SPSR_MODE32(mode, isa, endian, aif) \ 927 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 928 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 929 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 930 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 931 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 932 (~(SPSR_SSBS_BIT_AARCH32))) 933 934 /* 935 * TTBR Definitions 936 */ 937 #define TTBR_CNP_BIT ULL(0x1) 938 939 /* 940 * CTR_EL0 definitions 941 */ 942 #define CTR_CWG_SHIFT U(24) 943 #define CTR_CWG_MASK U(0xf) 944 #define CTR_ERG_SHIFT U(20) 945 #define CTR_ERG_MASK U(0xf) 946 #define CTR_DMINLINE_SHIFT U(16) 947 #define CTR_DMINLINE_MASK U(0xf) 948 #define CTR_L1IP_SHIFT U(14) 949 #define CTR_L1IP_MASK U(0x3) 950 #define CTR_IMINLINE_SHIFT U(0) 951 #define CTR_IMINLINE_MASK U(0xf) 952 953 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 954 955 /* Physical timer control register bit fields shifts and masks */ 956 #define CNTP_CTL_ENABLE_SHIFT U(0) 957 #define CNTP_CTL_IMASK_SHIFT U(1) 958 #define CNTP_CTL_ISTATUS_SHIFT U(2) 959 960 #define CNTP_CTL_ENABLE_MASK U(1) 961 #define CNTP_CTL_IMASK_MASK U(1) 962 #define CNTP_CTL_ISTATUS_MASK U(1) 963 964 /* Physical timer control macros */ 965 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 966 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 967 968 /* Exception Syndrome register bits and bobs */ 969 #define ESR_EC_SHIFT U(26) 970 #define ESR_EC_MASK U(0x3f) 971 #define ESR_EC_LENGTH U(6) 972 #define ESR_ISS_SHIFT U(0) 973 #define ESR_ISS_LENGTH U(25) 974 #define ESR_IL_BIT (U(1) << 25) 975 #define EC_UNKNOWN U(0x0) 976 #define EC_WFE_WFI U(0x1) 977 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 978 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 979 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 980 #define EC_AARCH32_CP14_LDC_STC U(0x6) 981 #define EC_FP_SIMD U(0x7) 982 #define EC_AARCH32_CP10_MRC U(0x8) 983 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 984 #define EC_ILLEGAL U(0xe) 985 #define EC_AARCH32_SVC U(0x11) 986 #define EC_AARCH32_HVC U(0x12) 987 #define EC_AARCH32_SMC U(0x13) 988 #define EC_AARCH64_SVC U(0x15) 989 #define EC_AARCH64_HVC U(0x16) 990 #define EC_AARCH64_SMC U(0x17) 991 #define EC_AARCH64_SYS U(0x18) 992 #define EC_IMP_DEF_EL3 U(0x1f) 993 #define EC_IABORT_LOWER_EL U(0x20) 994 #define EC_IABORT_CUR_EL U(0x21) 995 #define EC_PC_ALIGN U(0x22) 996 #define EC_DABORT_LOWER_EL U(0x24) 997 #define EC_DABORT_CUR_EL U(0x25) 998 #define EC_SP_ALIGN U(0x26) 999 #define EC_AARCH32_FP U(0x28) 1000 #define EC_AARCH64_FP U(0x2c) 1001 #define EC_SERROR U(0x2f) 1002 #define EC_BRK U(0x3c) 1003 1004 /* 1005 * External Abort bit in Instruction and Data Aborts synchronous exception 1006 * syndromes. 1007 */ 1008 #define ESR_ISS_EABORT_EA_BIT U(9) 1009 1010 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1011 1012 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1013 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1014 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1015 1016 /******************************************************************************* 1017 * Definitions of register offsets, fields and macros for CPU system 1018 * instructions. 1019 ******************************************************************************/ 1020 1021 #define TLBI_ADDR_SHIFT U(12) 1022 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1023 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1024 1025 /******************************************************************************* 1026 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1027 * system level implementation of the Generic Timer. 1028 ******************************************************************************/ 1029 #define CNTCTLBASE_CNTFRQ U(0x0) 1030 #define CNTNSAR U(0x4) 1031 #define CNTNSAR_NS_SHIFT(x) (x) 1032 1033 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1034 #define CNTACR_RPCT_SHIFT U(0x0) 1035 #define CNTACR_RVCT_SHIFT U(0x1) 1036 #define CNTACR_RFRQ_SHIFT U(0x2) 1037 #define CNTACR_RVOFF_SHIFT U(0x3) 1038 #define CNTACR_RWVT_SHIFT U(0x4) 1039 #define CNTACR_RWPT_SHIFT U(0x5) 1040 1041 /******************************************************************************* 1042 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1043 * system level implementation of the Generic Timer. 1044 ******************************************************************************/ 1045 /* Physical Count register. */ 1046 #define CNTPCT_LO U(0x0) 1047 /* Counter Frequency register. */ 1048 #define CNTBASEN_CNTFRQ U(0x10) 1049 /* Physical Timer CompareValue register. */ 1050 #define CNTP_CVAL_LO U(0x20) 1051 /* Physical Timer Control register. */ 1052 #define CNTP_CTL U(0x2c) 1053 1054 /* PMCR_EL0 definitions */ 1055 #define PMCR_EL0_RESET_VAL U(0x0) 1056 #define PMCR_EL0_N_SHIFT U(11) 1057 #define PMCR_EL0_N_MASK U(0x1f) 1058 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1059 #define PMCR_EL0_LP_BIT (U(1) << 7) 1060 #define PMCR_EL0_LC_BIT (U(1) << 6) 1061 #define PMCR_EL0_DP_BIT (U(1) << 5) 1062 #define PMCR_EL0_X_BIT (U(1) << 4) 1063 #define PMCR_EL0_D_BIT (U(1) << 3) 1064 #define PMCR_EL0_C_BIT (U(1) << 2) 1065 #define PMCR_EL0_P_BIT (U(1) << 1) 1066 #define PMCR_EL0_E_BIT (U(1) << 0) 1067 1068 /******************************************************************************* 1069 * Definitions for system register interface to SVE 1070 ******************************************************************************/ 1071 #define ZCR_EL3 S3_6_C1_C2_0 1072 #define ZCR_EL2 S3_4_C1_C2_0 1073 1074 /* ZCR_EL3 definitions */ 1075 #define ZCR_EL3_LEN_MASK U(0xf) 1076 1077 /* ZCR_EL2 definitions */ 1078 #define ZCR_EL2_LEN_MASK U(0xf) 1079 1080 /******************************************************************************* 1081 * Definitions for system register interface to SME as needed in EL3 1082 ******************************************************************************/ 1083 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1084 #define SMCR_EL3 S3_6_C1_C2_6 1085 1086 /* ID_AA64SMFR0_EL1 definitions */ 1087 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1088 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1089 #define SME_FA64_IMPLEMENTED U(0x1) 1090 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1091 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1092 #define SME_INST_IMPLEMENTED ULL(0x0) 1093 #define SME2_INST_IMPLEMENTED ULL(0x1) 1094 1095 /* SMCR_ELx definitions */ 1096 #define SMCR_ELX_LEN_SHIFT U(0) 1097 #define SMCR_ELX_LEN_MAX U(0x1ff) 1098 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1099 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1100 1101 /******************************************************************************* 1102 * Definitions of MAIR encodings for device and normal memory 1103 ******************************************************************************/ 1104 /* 1105 * MAIR encodings for device memory attributes. 1106 */ 1107 #define MAIR_DEV_nGnRnE ULL(0x0) 1108 #define MAIR_DEV_nGnRE ULL(0x4) 1109 #define MAIR_DEV_nGRE ULL(0x8) 1110 #define MAIR_DEV_GRE ULL(0xc) 1111 1112 /* 1113 * MAIR encodings for normal memory attributes. 1114 * 1115 * Cache Policy 1116 * WT: Write Through 1117 * WB: Write Back 1118 * NC: Non-Cacheable 1119 * 1120 * Transient Hint 1121 * NTR: Non-Transient 1122 * TR: Transient 1123 * 1124 * Allocation Policy 1125 * RA: Read Allocate 1126 * WA: Write Allocate 1127 * RWA: Read and Write Allocate 1128 * NA: No Allocation 1129 */ 1130 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1131 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1132 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1133 #define MAIR_NORM_NC ULL(0x4) 1134 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1135 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1136 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1137 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1138 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1139 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1140 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1141 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1142 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1143 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1144 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1145 1146 #define MAIR_NORM_OUTER_SHIFT U(4) 1147 1148 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1149 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1150 1151 /* PAR_EL1 fields */ 1152 #define PAR_F_SHIFT U(0) 1153 #define PAR_F_MASK ULL(0x1) 1154 #define PAR_ADDR_SHIFT U(12) 1155 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1156 1157 /******************************************************************************* 1158 * Definitions for system register interface to SPE 1159 ******************************************************************************/ 1160 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1161 1162 /******************************************************************************* 1163 * Definitions for system register interface, shifts and masks for MPAM 1164 ******************************************************************************/ 1165 #define MPAMIDR_EL1 S3_0_C10_C4_4 1166 #define MPAM2_EL2 S3_4_C10_C5_0 1167 #define MPAMHCR_EL2 S3_4_C10_C4_0 1168 #define MPAM3_EL3 S3_6_C10_C5_0 1169 1170 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1171 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1172 /******************************************************************************* 1173 * Definitions for system register interface to AMU for FEAT_AMUv1 1174 ******************************************************************************/ 1175 #define AMCR_EL0 S3_3_C13_C2_0 1176 #define AMCFGR_EL0 S3_3_C13_C2_1 1177 #define AMCGCR_EL0 S3_3_C13_C2_2 1178 #define AMUSERENR_EL0 S3_3_C13_C2_3 1179 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1180 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1181 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1182 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1183 1184 /* Activity Monitor Group 0 Event Counter Registers */ 1185 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1186 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1187 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1188 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1189 1190 /* Activity Monitor Group 0 Event Type Registers */ 1191 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1192 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1193 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1194 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1195 1196 /* Activity Monitor Group 1 Event Counter Registers */ 1197 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1198 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1199 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1200 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1201 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1202 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1203 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1204 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1205 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1206 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1207 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1208 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1209 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1210 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1211 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1212 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1213 1214 /* Activity Monitor Group 1 Event Type Registers */ 1215 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1216 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1217 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1218 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1219 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1220 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1221 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1222 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1223 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1224 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1225 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1226 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1227 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1228 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1229 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1230 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1231 1232 /* AMCNTENSET0_EL0 definitions */ 1233 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1234 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1235 1236 /* AMCNTENSET1_EL0 definitions */ 1237 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1238 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1239 1240 /* AMCNTENCLR0_EL0 definitions */ 1241 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1242 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1243 1244 /* AMCNTENCLR1_EL0 definitions */ 1245 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1246 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1247 1248 /* AMCFGR_EL0 definitions */ 1249 #define AMCFGR_EL0_NCG_SHIFT U(28) 1250 #define AMCFGR_EL0_NCG_MASK U(0xf) 1251 #define AMCFGR_EL0_N_SHIFT U(0) 1252 #define AMCFGR_EL0_N_MASK U(0xff) 1253 1254 /* AMCGCR_EL0 definitions */ 1255 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1256 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1257 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1258 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1259 1260 /* MPAM register definitions */ 1261 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1262 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1263 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1264 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1265 1266 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1267 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1268 1269 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1270 1271 /******************************************************************************* 1272 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1273 ******************************************************************************/ 1274 1275 /* Definition for register defining which virtual offsets are implemented. */ 1276 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1277 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1278 #define AMCG1IDR_CTR_SHIFT U(0) 1279 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1280 #define AMCG1IDR_VOFF_SHIFT U(16) 1281 1282 /* New bit added to AMCR_EL0 */ 1283 #define AMCR_CG1RZ_SHIFT U(17) 1284 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1285 1286 /* 1287 * Definitions for virtual offset registers for architected activity monitor 1288 * event counters. 1289 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1290 */ 1291 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1292 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1293 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1294 1295 /* 1296 * Definitions for virtual offset registers for auxiliary activity monitor event 1297 * counters. 1298 */ 1299 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1300 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1301 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1302 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1303 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1304 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1305 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1306 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1307 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1308 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1309 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1310 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1311 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1312 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1313 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1314 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1315 1316 /******************************************************************************* 1317 * Realm management extension register definitions 1318 ******************************************************************************/ 1319 #define GPCCR_EL3 S3_6_C2_C1_6 1320 #define GPTBR_EL3 S3_6_C2_C1_4 1321 1322 #define SCXTNUM_EL2 S3_4_C13_C0_7 1323 #define SCXTNUM_EL1 S3_0_C13_C0_7 1324 #define SCXTNUM_EL0 S3_3_C13_C0_7 1325 1326 /******************************************************************************* 1327 * RAS system registers 1328 ******************************************************************************/ 1329 #define DISR_EL1 S3_0_C12_C1_1 1330 #define DISR_A_BIT U(31) 1331 1332 #define ERRIDR_EL1 S3_0_C5_C3_0 1333 #define ERRIDR_MASK U(0xffff) 1334 1335 #define ERRSELR_EL1 S3_0_C5_C3_1 1336 1337 /* System register access to Standard Error Record registers */ 1338 #define ERXFR_EL1 S3_0_C5_C4_0 1339 #define ERXCTLR_EL1 S3_0_C5_C4_1 1340 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1341 #define ERXADDR_EL1 S3_0_C5_C4_3 1342 #define ERXPFGF_EL1 S3_0_C5_C4_4 1343 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1344 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1345 #define ERXMISC0_EL1 S3_0_C5_C5_0 1346 #define ERXMISC1_EL1 S3_0_C5_C5_1 1347 1348 #define ERXCTLR_ED_SHIFT U(0) 1349 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1350 #define ERXCTLR_UE_BIT (U(1) << 4) 1351 1352 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1353 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1354 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1355 1356 /******************************************************************************* 1357 * Armv8.3 Pointer Authentication Registers 1358 ******************************************************************************/ 1359 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1360 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1361 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1362 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1363 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1364 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1365 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1366 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1367 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1368 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1369 1370 /******************************************************************************* 1371 * Armv8.4 Data Independent Timing Registers 1372 ******************************************************************************/ 1373 #define DIT S3_3_C4_C2_5 1374 #define DIT_BIT BIT(24) 1375 1376 /******************************************************************************* 1377 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1378 ******************************************************************************/ 1379 #define SSBS S3_3_C4_C2_6 1380 1381 /******************************************************************************* 1382 * Armv8.5 - Memory Tagging Extension Registers 1383 ******************************************************************************/ 1384 #define TFSRE0_EL1 S3_0_C5_C6_1 1385 #define TFSR_EL1 S3_0_C5_C6_0 1386 #define RGSR_EL1 S3_0_C1_C0_5 1387 #define GCR_EL1 S3_0_C1_C0_6 1388 1389 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1390 1391 /******************************************************************************* 1392 * Armv8.5 - Random Number Generator Registers 1393 ******************************************************************************/ 1394 #define RNDR S3_3_C2_C4_0 1395 #define RNDRRS S3_3_C2_C4_1 1396 1397 /******************************************************************************* 1398 * FEAT_HCX - Extended Hypervisor Configuration Register 1399 ******************************************************************************/ 1400 #define HCRX_EL2 S3_4_C1_C2_2 1401 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1402 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1403 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1404 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1405 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1406 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1407 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1408 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1409 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1410 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1411 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1412 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1413 #define HCRX_EL2_INIT_VAL ULL(0x0) 1414 1415 /******************************************************************************* 1416 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1417 ******************************************************************************/ 1418 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1419 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1420 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1421 1422 /******************************************************************************* 1423 * FEAT_TCR2 - Extended Translation Control Registers 1424 ******************************************************************************/ 1425 #define TCR2_EL1 S3_0_C2_C0_3 1426 #define TCR2_EL2 S3_4_C2_C0_3 1427 1428 /******************************************************************************* 1429 * Permission indirection and overlay Registers 1430 ******************************************************************************/ 1431 1432 #define PIRE0_EL1 S3_0_C10_C2_2 1433 #define PIRE0_EL2 S3_4_C10_C2_2 1434 #define PIR_EL1 S3_0_C10_C2_3 1435 #define PIR_EL2 S3_4_C10_C2_3 1436 #define POR_EL1 S3_0_C10_C2_4 1437 #define POR_EL2 S3_4_C10_C2_4 1438 #define S2PIR_EL2 S3_4_C10_C2_5 1439 #define S2POR_EL1 S3_0_C10_C2_5 1440 1441 /******************************************************************************* 1442 * FEAT_GCS - Guarded Control Stack Registers 1443 ******************************************************************************/ 1444 #define GCSCR_EL2 S3_4_C2_C5_0 1445 #define GCSPR_EL2 S3_4_C2_C5_1 1446 #define GCSCR_EL1 S3_0_C2_C5_0 1447 #define GCSCRE0_EL1 S3_0_C2_C5_2 1448 #define GCSPR_EL1 S3_0_C2_C5_1 1449 #define GCSPR_EL0 S3_3_C2_C5_1 1450 1451 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1452 1453 /******************************************************************************* 1454 * FEAT_TRF - Trace Filter Control Registers 1455 ******************************************************************************/ 1456 #define TRFCR_EL2 S3_4_C1_C2_1 1457 #define TRFCR_EL1 S3_0_C1_C2_1 1458 1459 /******************************************************************************* 1460 * Definitions for DynamicIQ Shared Unit registers 1461 ******************************************************************************/ 1462 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1463 1464 /* CLUSTERPWRDN_EL1 register definitions */ 1465 #define DSU_CLUSTER_PWR_OFF 0 1466 #define DSU_CLUSTER_PWR_ON 1 1467 #define DSU_CLUSTER_PWR_MASK U(1) 1468 #define DSU_CLUSTER_MEM_RET BIT(1) 1469 1470 /******************************************************************************* 1471 * Definitions for CPU Power/Performance Management registers 1472 ******************************************************************************/ 1473 1474 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1475 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1476 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1477 1478 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1479 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1480 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1481 1482 /* alternative system register encoding for the "sb" speculation barrier */ 1483 #define SYSREG_SB S0_3_C3_C0_7 1484 1485 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1486 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1487 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1488 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1489 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1490 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1491 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1492 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1493 1494 #define CLUSTERPMCR_E_BIT BIT(0) 1495 #define CLUSTERPMCR_N_SHIFT U(11) 1496 #define CLUSTERPMCR_N_MASK U(0x1f) 1497 1498 #endif /* ARCH_H */ 1499