1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_ACPI_H_ 4 #define _SOC_ACPI_H_ 5 6 #include <acpi/acpi.h> 7 8 #define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 9 #define MAX_ACPI_MEMORY_AFFINITY_COUNT 256 10 11 /** 12 Select C-state map set in config cstate_states 13 **/ 14 enum acpi_cstate_mode { 15 CSTATES_ALL = 0, 16 CSTATES_C1C6 17 }; 18 19 unsigned long northbridge_write_acpi_tables(const struct device *device, 20 unsigned long current, struct acpi_rsdp *rsdp); 21 unsigned long acpi_fill_cedt(unsigned long current); 22 unsigned long acpi_fill_hmat(unsigned long current); 23 unsigned long cxl_fill_srat(unsigned long current); 24 25 void iio_domain_set_acpi_name(struct device *dev, const char *prefix); 26 27 #define PCIE_NATIVE_HOTPLUG_CONTROL 0x01 28 #define SHPC_NATIVE_HOTPLUG_CONTROL 0x02 29 #define PCIE_PME_CONTROL 0x04 30 #define PCIE_AER_CONTROL 0x08 31 #define PCIE_CAP_STRUCTURE_CONTROL 0x10 32 #define PCIE_LTR_CONTROL 0x20 33 #define PCIE_DPC_COTROL 0x80 34 35 #define CXL_ERROR_REPORTING_CONTROL 0x01 36 37 void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain, 38 const uint32_t granted_pcie_features, 39 const bool is_cxl_domain, 40 const uint32_t granted_cxl_features); 41 42 #endif /* _SOC_ACPI_H_ */ 43