1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CSS_DEF_H 8 #define CSS_DEF_H 9 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gic_common.h> 12 #include <drivers/arm/tzc400.h> 13 14 /************************************************************************* 15 * Definitions common to all ARM Compute SubSystems (CSS) 16 *************************************************************************/ 17 #define NSROM_BASE 0x1f000000 18 #define NSROM_SIZE 0x00001000 19 20 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 21 #define CSS_DEVICE_BASE 0x20000000 22 #define CSS_DEVICE_SIZE 0x0e000000 23 24 /* System Security Control Registers */ 25 #define SSC_REG_BASE 0x2a420000 26 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 27 28 /* System ID Registers Unit */ 29 #define SID_REG_BASE 0x2a4a0000 30 #define SID_SYSTEM_ID_OFFSET 0x40 31 #define SID_SYSTEM_CFG_OFFSET 0x70 32 #define SID_NODE_ID_OFFSET 0x60 33 #define SID_CHIP_ID_MASK 0xFF 34 #define SID_MULTI_CHIP_MODE_MASK 0x100 35 #define SID_MULTI_CHIP_MODE_SHIFT 8 36 37 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 38 #define CSS_NIC400_SLAVE_BOOTSECURE 8 39 40 /* Interrupt handling constants */ 41 #define CSS_IRQ_MHU 69 42 #define CSS_IRQ_GPU_SMMU_0 71 43 #define CSS_IRQ_TZC 80 44 #define CSS_IRQ_TZ_WDOG 86 45 #define CSS_IRQ_SEC_SYS_TIMER 91 46 47 /* MHU register offsets */ 48 #define MHU_CPU_INTR_S_SET_OFFSET 0x308 49 50 /* 51 * Define a list of Group 1 Secure interrupt properties as per GICv3 52 * terminology. On a GICv2 system or mode, the interrupts will be treated as 53 * Group 0 interrupts. 54 */ 55 #define CSS_G1S_INT_PROPS(grp) \ 56 INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ 57 GIC_INTR_CFG_LEVEL), \ 58 INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 59 GIC_INTR_CFG_LEVEL), \ 60 INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 61 GIC_INTR_CFG_LEVEL) 62 63 #define CSS_G1S_IRQ_PROPS(grp) \ 64 CSS_G1S_INT_PROPS(grp), \ 65 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 66 GIC_INTR_CFG_LEVEL), \ 67 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 68 GIC_INTR_CFG_LEVEL) 69 70 #if CSS_USE_SCMI_SDS_DRIVER 71 /* Memory region for shared data storage */ 72 #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE 73 #define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */ 74 /* 75 * The SCMI Channel is placed right after the SDS region 76 */ 77 #define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) 78 #define CSS_SCMI_PAYLOAD_SIZE_MAX 0x100 /* 2x128 bytes for bidirectional communication */ 79 #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET 80 81 /* Trusted mailbox base address common to all CSS */ 82 /* If SDS is present, then mailbox is at top of SRAM */ 83 #define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8) 84 85 /* Number of retries for SCP_RAM_READY flag */ 86 #define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */ 87 88 #else 89 /* 90 * SCP <=> AP boot configuration 91 * 92 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 93 * the start of the Trusted SRAM. 94 * 95 * Note that the value stored at this address is only valid at boot time, before 96 * the SCP_BL2 image is transferred to SCP. 97 */ 98 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 99 100 /* Trusted mailbox base address common to all CSS */ 101 /* If SDS is not present, then the mailbox is at the bottom of SRAM */ 102 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 103 104 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 105 106 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 107 CSS_DEVICE_BASE, \ 108 CSS_DEVICE_SIZE, \ 109 MT_DEVICE | MT_RW | MT_SECURE) 110 111 #define CSS_MAP_NSRAM MAP_REGION_FLAT( \ 112 NSRAM_BASE, \ 113 NSRAM_SIZE, \ 114 MT_DEVICE | MT_RW | MT_NS) 115 116 #if defined(IMAGE_BL2U) 117 #define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \ 118 SCP_BL2U_BASE, \ 119 SCP_BL2U_LIMIT \ 120 - SCP_BL2U_BASE,\ 121 MT_RW_DATA | MT_SECURE) 122 #endif 123 124 /* Platform ID address */ 125 #define SSC_VERSION_OFFSET 0x040 126 127 #define SSC_VERSION_CONFIG_SHIFT 28 128 #define SSC_VERSION_MAJOR_REV_SHIFT 24 129 #define SSC_VERSION_MINOR_REV_SHIFT 20 130 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 131 #define SSC_VERSION_PART_NUM_SHIFT 0x0 132 #define SSC_VERSION_CONFIG_MASK 0xf 133 #define SSC_VERSION_MAJOR_REV_MASK 0xf 134 #define SSC_VERSION_MINOR_REV_MASK 0xf 135 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 136 #define SSC_VERSION_PART_NUM_MASK 0xfff 137 138 #define SID_SYSTEM_ID_PART_NUM_MASK 0xfff 139 140 /* SSC debug configuration registers */ 141 #define SSC_DBGCFG_SET 0x14 142 #define SSC_DBGCFG_CLR 0x18 143 144 #define SPNIDEN_INT_CLR_SHIFT 4 145 #define SPNIDEN_SEL_SET_SHIFT 5 146 #define SPIDEN_INT_CLR_SHIFT 6 147 #define SPIDEN_SEL_SET_SHIFT 7 148 149 #ifndef __ASSEMBLER__ 150 151 /* SSC_VERSION related accessors */ 152 153 /* Returns the part number of the platform */ 154 #define GET_SSC_VERSION_PART_NUM(val) \ 155 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 156 SSC_VERSION_PART_NUM_MASK) 157 158 /* Returns the configuration number of the platform */ 159 #define GET_SSC_VERSION_CONFIG(val) \ 160 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 161 SSC_VERSION_CONFIG_MASK) 162 163 #endif /* __ASSEMBLER__ */ 164 165 /************************************************************************* 166 * Required platform porting definitions common to all 167 * ARM Compute SubSystems (CSS) 168 ************************************************************************/ 169 170 /* 171 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 172 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 173 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 174 * an SCP_BL2/SCP_BL2U image. 175 */ 176 #if CSS_LOAD_SCP_IMAGES 177 178 #if ARM_BL31_IN_DRAM 179 #error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" 180 #endif 181 182 /* 183 * Load address of SCP_BL2 in CSS platform ports 184 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 185 * rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and 186 * BL31 is loaded over the top. 187 */ 188 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) 189 #define SCP_BL2_LIMIT BL2_BASE 190 191 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) 192 #define SCP_BL2U_LIMIT BL2_BASE 193 #endif /* CSS_LOAD_SCP_IMAGES */ 194 195 /* Load address of Non-Secure Image for CSS platform ports */ 196 #define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000) 197 198 /* 199 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 200 * command 201 */ 202 #define CSS_CLUSTER_PWR_STATE_ON 0 203 #define CSS_CLUSTER_PWR_STATE_OFF 3 204 205 #define CSS_CPU_PWR_STATE_ON 1 206 #define CSS_CPU_PWR_STATE_OFF 0 207 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 208 209 #endif /* CSS_DEF_H */ 210