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Searched defs:CSSELR (Results 1 – 7 of 7) sorted by relevance

/aosp_15_r20/external/arm-trusted-firmware/include/arch/aarch32/
H A Darch.h560 #define CSSELR p15, 2, c0, c0, 0 macro
/aosp_15_r20/external/trusty/arm-trusted-firmware/include/arch/aarch32/
Darch.h585 #define CSSELR p15, 2, c0, c0, 0 macro
/aosp_15_r20/external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/
H A Ddevice1.ini53 CSSELR=0x00000002 key
/aosp_15_r20/external/OpenCSD/decoder/tests/snapshots/trace_cov_a15/
H A Ddevice1.ini53 CSSELR=0x00000002 key
/aosp_15_r20/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm7.h435 …__IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register … member
/aosp_15_r20/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/
H A Dcore_cm7.h525 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
/aosp_15_r20/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/
H A Dcore_cm7.h525 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member