1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __ARCH_ARM64_CORTEX_A57_H__ 4 #define __ARCH_ARM64_CORTEX_A57_H__ 5 6 #define CPUACTLR_EL1 s3_1_c15_c2_0 7 #define BTB_INVALIDATE (1 << 0) 8 9 #define CPUECTLR_EL1 S3_1_c15_c2_1 10 #define SMPEN_SHIFT 6 11 12 /* Cortex MIDR[15:4] PN */ 13 #define CORTEX_A53_PN 0xd03 14 15 /* Double lock control bit */ 16 #define OSDLR_DBL_LOCK_BIT 1 17 18 #endif /* __ARCH_ARM64_CORTEX_A57_H__ */ 19