1 /** 2 * \file 3 * 4 * \brief SAMV71-XLTRA Board Definition. 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef _SAMV71_XLTRA_H_ 48 #define _SAMV71_XLTRA_H_ 49 50 #include "compiler.h" 51 #include "system_samv71.h" 52 53 /*----------------------------------------------------------------------------*/ 54 /** 55 * \page samv71_xplained_ultra_opfreq "SAMV71-XLTRA - Operating frequencies" 56 * This page lists several definition related to the board operating frequency 57 * 58 * \section Definitions 59 * - \ref BOARD_FREQ_* 60 * - \ref BOARD_MCK 61 */ 62 63 /** Board oscillator settings */ 64 #define BOARD_FREQ_SLCK_XTAL (32768U) 65 #define BOARD_FREQ_SLCK_BYPASS (32768U) 66 #define BOARD_FREQ_MAINCK_XTAL (12000000U) 67 #define BOARD_FREQ_MAINCK_BYPASS (12000000U) 68 69 /** Master clock frequency */ 70 #define BOARD_MCK CHIP_FREQ_CPU_MAX 71 72 /** board main clock xtal statup time */ 73 #define BOARD_OSC_STARTUP_US 15625 74 75 /*----------------------------------------------------------------------------*/ 76 /** 77 * \page samv71_xplained_ultra_info "SAMV71-XLTRA - Board informations" 78 * This page lists several definition related to the board description. 79 * 80 * \section Definitions 81 * - \ref BOARD_NAME 82 */ 83 84 /** Name of the board */ 85 #define BOARD_NAME "SAMV71-XLTRA" 86 /** Board definition */ 87 #define samv71xultra 88 /** Family definition (already defined) */ 89 #define samv71 90 /** Core definition */ 91 #define cortexm7 92 93 /*----------------------------------------------------------------------------*/ 94 95 #define CONSOLE_UART USART1 96 #define CONSOLE_UART_ID ID_USART1 97 /** USART1 pins definitions, PA21,PB4. */ 98 #define USART1_RXD_GPIO PIO_PA21_IDX 99 #define USART1_RXD_FLAGS IOPORT_MODE_MUX_A 100 #define USART1_TXD_GPIO PIO_PB4_IDX 101 #define USART1_TXD_FLAGS IOPORT_MODE_MUX_D 102 103 /** USART0 pins definitions, PB0,PB1. */ 104 #define USART0_RXD_GPIO PIO_PB0_IDX 105 #define USART0_RXD_FLAGS IOPORT_MODE_MUX_C 106 #define USART0_TXD_GPIO PIO_PB1_IDX 107 #define USART0_TXD_FLAGS IOPORT_MODE_MUX_C 108 109 #define PIN_USART0_SCK_IDX (PIO_PB13_IDX) 110 #define PIN_USART0_SCK_FLAGS (IOPORT_MODE_MUX_C) 111 112 /** USART0 pin CTS */ 113 #define PIN_USART0_CTS_IDX (PIO_PB2_IDX) 114 #define PIN_USART0_CTS_FLAGS (IOPORT_MODE_MUX_C) 115 116 /** USART0 pin RTS */ 117 #define PIN_USART0_RTS_IDX (PIO_PB3_IDX) 118 #define PIN_USART0_RTS_FLAGS (IOPORT_MODE_MUX_C) 119 120 121 //! \name LED definitions 122 //@{ 123 #define LED0_GPIO (PIO_PA23_IDX) 124 #define LED0_FLAGS (0) 125 #define LED0_ACTIVE_LEVEL (IOPORT_PIN_LEVEL_LOW) 126 #define LED0_INACTIVE_LEVEL (IOPORT_PIN_LEVEL_HIGH) 127 128 #define LED1_GPIO (PIO_PC9_IDX) 129 #define LED1_FLAGS (0) 130 #define LED1_ACTIVE_LEVEL (IOPORT_PIN_LEVEL_LOW) 131 #define LED1_INACTIVE_LEVEL (IOPORT_PIN_LEVEL_HIGH) 132 133 #define LED_COUNT (2) 134 //@} 135 136 //! \name SW0 definitions 137 //@{ 138 #define SW0_PIN (PIO_PA9_IDX) 139 #define SW0_ACTIVE (IOPORT_PIN_LEVEL_LOW) 140 #define SW0_INACTIVE (!SW0_ACTIVE) 141 #define SW0_SUPC_INPUT 2 142 143 /** 144 * Wrapper macros for SW0, to ensure common naming across all Xplained Ultra 145 * boards. 146 */ 147 #define PIN_SW0 {PIO_PA9, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} 148 #define PIN_SW0_MASK PIO_PA9 149 #define PIN_SW0_PIO PIOA 150 #define PIN_SW0_ID ID_PIOA 151 #define PIN_SW0_TYPE PIO_INPUT 152 #define PIN_SW0_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) 153 //@} 154 155 //! \name SW1 definitions 156 //@{ 157 #define SW1_PIN (PIO_PB12_IDX) 158 #define SW1_ACTIVE (IOPORT_PIN_LEVEL_LOW) 159 #define SW1_INACTIVE (!SW1_ACTIVE) 160 #define SW1_SUPC_INPUT 2 161 162 /** 163 * Wrapper macros for SW1, to ensure common naming across all Xplained Ultra 164 * boards. 165 */ 166 #define PIN_SW1 {PIO_PB12, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} 167 #define PIN_SW1_MASK PIO_PB12 168 #define PIN_SW1_PIO PIOB 169 #define PIN_SW1_ID ID_PIOB 170 #define PIN_SW1_TYPE PIO_INPUT 171 #define PIN_SW1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) 172 //@} 173 174 /** 175 * \name LED #0 definitions 176 * 177 * Wrapper macros for LED0, to ensure common naming across all Xplained Ultra 178 * boards. 179 */ 180 //@{ 181 #define LED_0_NAME "LED0 (yellow)" 182 #define LED_0_PIN LED0_GPIO 183 #define LED_0_ACTIVE LED0_ACTIVE_LEVEL 184 #define LED_0_INACTIVE LED0_INACTIVE_LEVEL 185 186 #define PIN_LED_0 {PIO_PA23, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} 187 #define PIN_LED_0_MASK PIO_PA23 188 #define PIN_LED_0_PIO PIOA 189 #define PIN_LED_0_ID ID_PIOA 190 #define PIN_LED_0_TYPE PIO_OUTPUT_1 191 #define PIN_LED_0_ATTR PIO_DEFAULT 192 //@} 193 194 /* TC-- Timer Count */ 195 #define PIN_TC0_TIOA0 (PIO_PA0_IDX) 196 #define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B) 197 #define PIN_TC0_TIOA0_FLAGS (IOPORT_MODE_MUX_B) 198 199 #define PIN_TC0_TIOA0_PIO PIOA 200 #define PIN_TC0_TIOA0_MASK PIO_PA0 201 #define PIN_TC0_TIOA0_ID ID_PIOA 202 #define PIN_TC0_TIOA0_TYPE PIO_PERIPH_B 203 #define PIN_TC0_TIOA0_ATTR PIO_DEFAULT 204 205 #define PIN_TC3_TIOA11 (PIO_PD21_IDX) 206 #define PIN_TC3_TIOA11_MUX (IOPORT_MODE_MUX_C) 207 #define PIN_TC3_TIOA11_FLAGS (IOPORT_MODE_MUX_C) 208 209 #define PIN_TC3_TIOA11_PIO PIOD 210 #define PIN_TC3_TIOA11_MASK PIO_PD21 211 #define PIN_TC3_TIOA11_ID ID_PIOD 212 #define PIN_TC3_TIOA11_TYPE PIO_PERIPH_C 213 #define PIN_TC3_TIOA11_ATTR PIO_DEFAULT 214 /** 215 * \name LED #1 definitions 216 * 217 * Wrapper macros for LED1, to ensure common naming across all Xplained Ultra 218 * boards. 219 */ 220 //@{ 221 #define LED_1_NAME "LED1 (yellow)" 222 #define LED_1_PIN LED1_GPIO 223 #define LED_1_ACTIVE LED1_ACTIVE_LEVEL 224 #define LED_1_INACTIVE LED1_INACTIVE_LEVEL 225 226 #define PIN_LED_1 {PIO_PC9, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} 227 #define PIN_LED_1_MASK PIO_PC9 228 #define PIN_LED_1_PIO PIOC 229 #define PIN_LED_1_ID ID_PIOC 230 #define PIN_LED_1_TYPE PIO_OUTPUT_1 231 #define PIN_LED_1_ATTR PIO_DEFAULT 232 //@} 233 234 //! Number of on-board LEDs 235 #define BOARD_NUM_OF_LED 2 236 237 /** 238 * Push button #0 definition. Attributes = pull-up + debounce + interrupt on 239 * rising edge. 240 */ 241 #define BUTTON_0_NAME "SW0" 242 #define BUTTON_0_PIN SW0_PIN 243 #define BUTTON_0_ACTIVE SW0_ACTIVE 244 #define BUTTON_0_INACTIVE SW0_INACTIVE 245 #define BUTTON_0_SUPC_INPUT SW0_SUPC_INPUT 246 #define GPIO_PUSH_BUTTON_0 BUTTON_0_PIN 247 248 #define PUSHBUTTON_1_NAME "SW0" 249 #define PUSHBUTTON_1_WKUP_LINE (2) 250 #define PUSHBUTTON_1_WKUP_FSTT (PMC_FSMR_FSTT2) 251 #define GPIO_PUSH_BUTTON_1 (PIO_PA9_IDX) 252 #define GPIO_PUSH_BUTTON_1_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) 253 #define GPIO_PUSH_BUTTON_1_SENSE (IOPORT_SENSE_RISING) 254 255 #define PIN_PUSHBUTTON_1 {PIO_PA9, PIOA, ID_PIOA, PIO_INPUT, \ 256 PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} 257 #define PIN_PUSHBUTTON_1_MASK PIO_PA9 258 #define PIN_PUSHBUTTON_1_PIO PIOA 259 #define PIN_PUSHBUTTON_1_ID ID_PIOA 260 #define PIN_PUSHBUTTON_1_TYPE PIO_INPUT 261 #define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) 262 #define PIN_PUSHBUTTON_1_IRQn PIOA_IRQn 263 264 /** 265 * Push button #1 definition. Attributes = pull-up + debounce + interrupt on 266 * rising edge. 267 */ 268 #define BUTTON_1_NAME "SW1" 269 #define BUTTON_1_PIN SW1_PIN 270 #define BUTTON_1_ACTIVE SW1_ACTIVE 271 #define BUTTON_1_INACTIVE SW1_INACTIVE 272 #define BUTTON_1_SUPC_INPUT SW1_SUPC_INPUT 273 274 #define PUSHBUTTON_2_NAME "SW1" 275 #define PUSHBUTTON_2_WKUP_LINE (2) 276 #define PUSHBUTTON_2_WKUP_FSTT (PMC_FSMR_FSTT2) 277 #define GPIO_PUSH_BUTTON_2 (PIO_PB12_IDX) 278 #define GPIO_PUSH_BUTTON_2_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) 279 #define GPIO_PUSH_BUTTON_2_SENSE (IOPORT_SENSE_RISING) 280 281 #define PIN_PUSHBUTTON_2 {PIO_PB12, PIOB, ID_PIOB, PIO_INPUT, \ 282 PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} 283 #define PIN_PUSHBUTTON_2_MASK PIO_PB12 284 #define PIN_PUSHBUTTON_2_PIO PIOB 285 #define PIN_PUSHBUTTON_2_ID ID_PIOB 286 #define PIN_PUSHBUTTON_2_TYPE PIO_INPUT 287 #define PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) 288 #define PIN_PUSHBUTTON_2_IRQn PIOB_IRQn 289 290 /** List of all push button definitions. */ 291 #define PINS_PUSHBUTTONS {PIN_PUSHBUTTON_1,PIN_PUSHBUTTON_2} 292 293 /** PCK0 pin definition (PA6) */ 294 #define PIN_PCK0 (PIO_PA6_IDX) 295 #define PIN_PCK0_MUX (IOPORT_MODE_MUX_B) 296 #define PIN_PCK0_FLAGS (IOPORT_MODE_MUX_B) 297 #define PIN_PCK0_PORT IOPORT_PIOA 298 #define PIN_PCK0_MASK PIO_PA6B_PCK0 299 #define PIN_PCK0_PIO PIOA 300 #define PIN_PCK0_ID ID_PIOA 301 #define PIN_PCK0_TYPE PIO_PERIPH_B 302 #define PIN_PCK0_ATTR PIO_DEFAULT 303 304 305 /** TWI0 pins definition */ 306 #define TWIHS0_DATA_GPIO PIO_PA3_IDX 307 #define TWIHS0_DATA_FLAGS (IOPORT_MODE_MUX_A) 308 #define TWIHS0_CLK_GPIO PIO_PA4_IDX 309 #define TWIHS0_CLK_FLAGS (IOPORT_MODE_MUX_A) 310 311 /** SPI0 pins definition */ 312 #define SPI0_MISO_GPIO PIO_PD20_IDX 313 #define SPI0_MISO_FLAGS (IOPORT_MODE_MUX_B) 314 #define SPI0_MOSI_GPIO PIO_PD21_IDX 315 #define SPI0_MOSI_FLAGS (IOPORT_MODE_MUX_B) 316 #define SPI0_NPCS0_GPIO PIO_PB2_IDX 317 #define SPI0_NPCS0_FLAGS (IOPORT_MODE_MUX_D) 318 #define SPI0_NPCS1_GPIO PIO_PD25_IDX 319 #define SPI0_NPCS1_FLAGS (IOPORT_MODE_MUX_B) 320 #define SPI0_NPCS2_GPIO PIO_PD12_IDX 321 #define SPI0_NPCS2_FLAGS (IOPORT_MODE_MUX_C) 322 #define SPI0_NPCS3_GPIO PIO_PD27_IDX 323 #define SPI0_NPCS3_FLAGS (IOPORT_MODE_MUX_B) 324 #define SPI0_SPCK_GPIO PIO_PD22_IDX 325 #define SPI0_SPCK_FLAGS (IOPORT_MODE_MUX_B) 326 327 /** QSPI pins definition */ 328 #define QSPI_QSCK_GPIO PIO_PA14_IDX 329 #define QSPI_QSCK_FLAGS (IOPORT_MODE_MUX_A) 330 #define QSPI_QCS_GPIO PIO_PA11_IDX 331 #define QSPI_QCS_FLAGS (IOPORT_MODE_MUX_A) 332 #define QSPI_QIO0_GPIO PIO_PA13_IDX 333 #define QSPI_QIO0_FLAGS (IOPORT_MODE_MUX_A) 334 #define QSPI_QIO1_GPIO PIO_PA12_IDX 335 #define QSPI_QIO1_FLAGS (IOPORT_MODE_MUX_A) 336 #define QSPI_QIO2_GPIO PIO_PA17_IDX 337 #define QSPI_QIO2_FLAGS (IOPORT_MODE_MUX_A) 338 #define QSPI_QIO3_GPIO PIO_PD31_IDX 339 #define QSPI_QIO3_FLAGS (IOPORT_MODE_MUX_A) 340 341 /** AFEC channel for potentiometer */ 342 #define AFEC_CHANNEL_POTENTIOMETER AFEC_CHANNEL_0 343 344 #define MCAN_MODULE MCAN1 345 /*----------------------------------------------------------------------------*/ 346 /** 347 * \page samv71_xpro_CAN "SAMV71-XPRO - CAN" 348 * This page lists definitions related to CAN0 and CAN1. 349 * 350 * CAN 351 * - \ref PIN_CAN0_TRANSCEIVER_RXEN 352 * - \ref PIN_CAN0_TRANSCEIVER_RS 353 * - \ref PIN_CAN0_TXD 354 * - \ref PIN_CAN0_RXD 355 * - \ref PINS_CAN0 356 * 357 * - \ref PIN_CAN1_TRANSCEIVER_RXEN 358 * - \ref PIN_CAN1_TRANSCEIVER_RS 359 * - \ref PIN_CAN1_TXD 360 * - \ref PIN_CAN1_RXD 361 * - \ref PINS_CAN1 362 */ 363 /** CAN0 transceiver PIN RS. */ 364 #define PIN_CAN0_TR_RS_IDX PIO_PE0_IDX 365 #define PIN_CAN0_TR_RS_FLAGS IOPORT_DIR_OUTPUT 366 367 /** CAN0 transceiver PIN EN. */ 368 #define PIN_CAN0_TR_EN_IDX PIO_PE1_IDX 369 #define PIN_CAN0_TR_EN_FLAGS IOPORT_DIR_OUTPUT 370 371 /** CAN0 PIN RX. */ 372 #define PIN_CAN0_RX_IDX PIO_PB3_IDX 373 #define PIN_CAN0_RX_FLAGS IOPORT_MODE_MUX_A 374 375 /** CAN0 PIN TX. */ 376 #define PIN_CAN0_TX_IDX PIO_PB2_IDX 377 #define PIN_CAN0_TX_FLAGS IOPORT_MODE_MUX_A 378 379 /** CAN1 transceiver PIN RS. */ 380 #define PIN_CAN1_TR_RS_IDX PIO_PE2_IDX 381 #define PIN_CAN1_TR_RS_FLAGS IOPORT_DIR_OUTPUT 382 383 /** CAN1 transceiver PIN EN. */ 384 #define PIN_CAN1_TR_EN_IDX PIO_PE3_IDX 385 #define PIN_CAN1_TR_EN_FLAGS IOPORT_DIR_OUTPUT 386 387 /** CAN1 PIN RX. */ 388 #define PIN_CAN1_RX_IDX PIO_PC12_IDX 389 #define PIN_CAN1_RX_FLAGS IOPORT_MODE_MUX_C 390 391 /** CAN1 PIN TX. */ 392 #define PIN_CAN1_TX_IDX PIO_PC14_IDX 393 #define PIN_CAN1_TX_FLAGS IOPORT_MODE_MUX_C 394 395 /** PWM LED0 pin definitions. */ 396 #define PIN_PWM_LED0_GPIO PIO_PA23_IDX 397 #define PIN_PWM_LED0_FLAGS (IOPORT_MODE_MUX_B) 398 #define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_0 399 400 /** PWM LED1 pin definitions. */ 401 #define PIN_PWM_LED1_GPIO PIO_PA24_IDX 402 #define PIN_PWM_LED1_FLAGS (IOPORT_MODE_MUX_B) 403 #define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_1 404 405 /*----------------------------------------------------------------------------*/ 406 /** GMAC HW configurations */ 407 #define BOARD_GMAC_PHY_ADDR 1 408 409 #define PIN_GMAC_RESET_MASK PIO_PC10 410 #define PIN_GMAC_RESET_PIO PIOC 411 #define PIN_GMAC_INT_MASK PIO_PA19 412 #define PIN_GMAC_INT_PIO PIOA 413 #define PIN_GMAC_SIGDET_MASK PIO_PA29 414 #define PIN_GMAC_SIGDET_PIO PIOA 415 #define PIN_GMAC_PERIPH PIO_PERIPH_A 416 #define PIN_GMAC_PIO PIOD 417 #define PIN_GMAC_MASK (PIO_PD0A_GTXCK | PIO_PD1A_GTXEN | PIO_PD2A_GTX0 | \ 418 PIO_PD3A_GTX1 | PIO_PD4A_GRXDV | PIO_PD5A_GRX0 | \ 419 PIO_PD6A_GRX1 | PIO_PD7A_GRXER | PIO_PD8A_GMDC | \ 420 PIO_PD9A_GMDIO) 421 422 /** Board configuration of the AT24MAC EEPROM */ 423 #define BOARD_AT24MAC_TWIHS_INSTANCE TWIHS0 424 #define BOARD_AT24MAC_ADDRESS (0xAE >> 1) 425 #define BOARD_CLK_TWIHS_EEPROM 0 426 #define BOARD_CLK_TWIHS_MUX_EEPROM 0 427 428 /** HSMCI pins definition. */ 429 /*! Number of slot connected on HSMCI interface */ 430 #define SD_MMC_HSMCI_MEM_CNT 1 431 #define SD_MMC_HSMCI_SLOT_0_SIZE 4 432 /** HSMCI MCCDA pin definition. */ 433 #define PIN_HSMCI_MCCDA_GPIO (PIO_PA28_IDX) 434 #define PIN_HSMCI_MCCDA_FLAGS (IOPORT_MODE_MUX_C) 435 /** HSMCI MCCK pin definition. */ 436 #define PIN_HSMCI_MCCK_GPIO (PIO_PA25_IDX) 437 #define PIN_HSMCI_MCCK_FLAGS (IOPORT_MODE_MUX_D) 438 /** HSMCI MCDA0 pin definition. */ 439 #define PIN_HSMCI_MCDA0_GPIO (PIO_PA30_IDX) 440 #define PIN_HSMCI_MCDA0_FLAGS (IOPORT_MODE_MUX_C) 441 /** HSMCI MCDA1 pin definition. */ 442 #define PIN_HSMCI_MCDA1_GPIO (PIO_PA31_IDX) 443 #define PIN_HSMCI_MCDA1_FLAGS (IOPORT_MODE_MUX_C) 444 /** HSMCI MCDA2 pin definition. */ 445 #define PIN_HSMCI_MCDA2_GPIO (PIO_PA26_IDX) 446 #define PIN_HSMCI_MCDA2_FLAGS (IOPORT_MODE_MUX_C) 447 /** HSMCI MCDA3 pin definition. */ 448 #define PIN_HSMCI_MCDA3_GPIO (PIO_PA27_IDX) 449 #define PIN_HSMCI_MCDA3_FLAGS (IOPORT_MODE_MUX_C) 450 451 /** SD/MMC card detect pin definition. */ 452 #define PIN_HSMCI_CD {PIO_PD18, PIOD, ID_PIOD, PIO_INPUT, PIO_PULLUP} 453 #define SD_MMC_0_CD_GPIO (PIO_PD18_IDX) 454 #define SD_MMC_0_CD_PIO_ID ID_PIOD 455 #define SD_MMC_0_CD_FLAGS (IOPORT_MODE_PULLUP) 456 #define SD_MMC_0_CD_DETECT_VALUE 0 457 458 /** EBI pins configuration for LCD */ 459 /** LCD reset pin */ 460 #define PIN_EBI_RESET_MASK PIO_PC13 461 #define PIN_EBI_RESET_PIO PIOC 462 #define PIN_EBI_RESET_TYPE PIO_OUTPUT_1 463 #define PIN_EBI_RESET_ATTRI PIO_DEFAULT 464 465 /** LCD command/data select pin */ 466 #define PIN_EBI_CDS_MASK PIO_PC30 467 #define PIN_EBI_CDS_PIO PIOC 468 #define PIN_EBI_CDS_TYPE PIO_OUTPUT_1 469 #define PIN_EBI_CDS_ATTRI PIO_DEFAULT 470 471 /** LCD data pin */ 472 #define PIN_EBI_DATAL_MASK 0xFF 473 #define PIN_EBI_DATAL_PIO PIOC 474 #define PIN_EBI_DATAL_TYPE PIO_PERIPH_A 475 #define PIN_EBI_DATAL_ATTRI PIO_PULLUP 476 477 #define PIN_EBI_DATAH_0_MASK 0x3F 478 #define PIN_EBI_DATAH_0_PIO PIOE 479 #define PIN_EBI_DATAH_0_TYPE PIO_PERIPH_A 480 #define PIN_EBI_DATAH_0_ATTRI PIO_PULLUP 481 482 #define PIN_EBI_DATAH_1_MASK (PIO_PA15A_D14|PIO_PA16A_D15) 483 #define PIN_EBI_DATAH_1_PIO PIOA 484 #define PIN_EBI_DATAH_1_TYPE PIO_PERIPH_A 485 #define PIN_EBI_DATAH_1_ATTRI PIO_PULLUP 486 487 /** LCD WE pin */ 488 #define PIN_EBI_NWE_MASK PIO_PC8A_NWE 489 #define PIN_EBI_NWE_PIO PIOC 490 #define PIN_EBI_NWE_TYPE PIO_PERIPH_A 491 #define PIN_EBI_NWE_ATTRI PIO_PULLUP 492 493 /** LCD RD pin */ 494 #define PIN_EBI_NRD_MASK PIO_PC11A_NRD 495 #define PIN_EBI_NRD_PIO PIOC 496 #define PIN_EBI_NRD_TYPE PIO_PERIPH_A 497 #define PIN_EBI_NRD_ATTRI PIO_PULLUP 498 499 /** LCD CS pin (NCS3) */ 500 #define PIN_EBI_CS_MASK PIO_PD19A_NCS3 501 #define PIN_EBI_CS_PIO PIOD 502 #define PIN_EBI_CS_TYPE PIO_PERIPH_A 503 #define PIN_EBI_CS_ATTRI PIO_PULLUP 504 505 /** Back-light pin definition. */ 506 #define PIN_EBI_BACKLIGHT_MASK PIO_PC9B_TIOB7 507 #define PIN_EBI_BACKLIGHT_PIO PIOC 508 #define PIN_EBI_BACKLIGHT_TYPE PIO_PERIPH_B 509 #define PIN_EBI_BACKLIGHT_ATTRI PIO_DEFAULT 510 511 /*! \name GPIO Connections of VBUS monitoring 512 */ 513 //! @{ 514 #define USB_VBUS_FLAGS (PIO_INPUT | PIO_PULLUP) 515 #define USB_VBUS_PIN PIO_PC9_IDX /* As IO pin input */ 516 #define USB_VBUS_PIN_IRQn ( PIOC_IRQn) 517 #define USB_VBUS_PIO_ID ID_PIOC 518 #define USB_VBUS_PIO_MASK PIO_PC9 519 //! @} 520 521 /*! \name GPIO Connections of ID detecting 522 */ 523 //! @{ 524 #define USB_ID_FLAGS (PIO_INPUT | PIO_PULLUP) 525 #define USB_ID_PIN PIO_PC16_IDX /* As IO pin input */ 526 #define USB_ID_PIN_IRQn (PIOC_IRQn) 527 #define USB_ID_PIO_ID ID_PIOC 528 #define USB_ID_PIO_MASK PIO_PC16 529 //! @} 530 531 /** WM8904 Slave address */ 532 #define WM8904_SLAVE_ADDRESS (0x34 >> 1) 533 534 /** TWI interface for WM8904 */ 535 #define WM8904_TWIHS TWIHS0 536 537 /** WM8904 pins definition */ 538 #define WM8904_TK_PIO PIO_PB1_IDX 539 #define WM8904_TK_FLAGS PIO_PERIPH_D 540 #define WM8904_TF_PIO PIO_PB0_IDX 541 #define WM8904_TF_FLAGS PIO_PERIPH_D 542 #define WM8904_TD_PIO PIO_PD26_IDX 543 #define WM8904_TD_FLAGS PIO_PERIPH_B 544 #define WM8904_RK_PIO PIO_PA22_IDX 545 #define WM8904_RK_FLAGS PIO_PERIPH_A 546 #define WM8904_RF_PIO PIO_PD24_IDX 547 #define WM8904_RF_FLAGS PIO_PERIPH_B 548 #define WM8904_RD_PIO PIO_PA10_IDX 549 #define WM8904_RD_FLAGS PIO_PERIPH_C 550 #define WM8904_PCK2_PIO PIO_PA18_IDX 551 #define WM8904_PCK2_FLAGS PIO_PERIPH_B 552 553 /** Board SDRAM size for MT48LC16M16A2 */ 554 #define BOARD_SDRAM_SIZE (2 * 1024 * 1024) 555 556 /** Address for transferring command bytes to the SDRAM. */ 557 #define BOARD_SDRAM_ADDR 0x70000000 558 559 /** SDRAM pins definitions */ 560 #define SDRAM_BA0_PIO PIO_PA20_IDX 561 #define SDRAM_SDCK_PIO PIO_PD23_IDX 562 #define SDRAM_SDCKE_PIO PIO_PD14_IDX 563 #define SDRAM_SDCS_PIO PIO_PC15_IDX 564 #define SDRAM_RAS_PIO PIO_PD16_IDX 565 #define SDRAM_CAS_PIO PIO_PD17_IDX 566 #define SDRAM_SDWE_PIO PIO_PD29_IDX 567 #define SDRAM_NBS0_PIO PIO_PC18_IDX 568 #define SDRAM_NBS1_PIO PIO_PD15_IDX 569 #define SDRAM_A2_PIO PIO_PC20_IDX 570 #define SDRAM_A3_PIO PIO_PC21_IDX 571 #define SDRAM_A4_PIO PIO_PC22_IDX 572 #define SDRAM_A5_PIO PIO_PC23_IDX 573 #define SDRAM_A6_PIO PIO_PC24_IDX 574 #define SDRAM_A7_PIO PIO_PC25_IDX 575 #define SDRAM_A8_PIO PIO_PC26_IDX 576 #define SDRAM_A9_PIO PIO_PC27_IDX 577 #define SDRAM_A10_PIO PIO_PC28_IDX 578 #define SDRAM_A11_PIO PIO_PC29_IDX 579 #define SDRAM_SDA10_PIO PIO_PD13_IDX 580 #define SDRAM_D0_PIO PIO_PC0_IDX 581 #define SDRAM_D1_PIO PIO_PC1_IDX 582 #define SDRAM_D2_PIO PIO_PC2_IDX 583 #define SDRAM_D3_PIO PIO_PC3_IDX 584 #define SDRAM_D4_PIO PIO_PC4_IDX 585 #define SDRAM_D5_PIO PIO_PC5_IDX 586 #define SDRAM_D6_PIO PIO_PC6_IDX 587 #define SDRAM_D7_PIO PIO_PC7_IDX 588 #define SDRAM_D8_PIO PIO_PE0_IDX 589 #define SDRAM_D9_PIO PIO_PE1_IDX 590 #define SDRAM_D10_PIO PIO_PE2_IDX 591 #define SDRAM_D11_PIO PIO_PE3_IDX 592 #define SDRAM_D12_PIO PIO_PE4_IDX 593 #define SDRAM_D13_PIO PIO_PE5_IDX 594 #define SDRAM_D14_PIO PIO_PA15_IDX 595 #define SDRAM_D15_PIO PIO_PA16_IDX 596 597 #define SDRAM_BA0_FLAGS PIO_PERIPH_C 598 #define SDRAM_SDCK_FLAGS PIO_PERIPH_C 599 #define SDRAM_SDCKE_FLAGS PIO_PERIPH_C 600 #define SDRAM_SDCS_FLAGS PIO_PERIPH_A 601 #define SDRAM_RAS_FLAGS PIO_PERIPH_C 602 #define SDRAM_CAS_FLAGS PIO_PERIPH_C 603 #define SDRAM_SDWE_FLAGS PIO_PERIPH_C 604 #define SDRAM_NBS0_FLAGS PIO_PERIPH_A 605 #define SDRAM_NBS1_FLAGS PIO_PERIPH_C 606 #define SDRAM_A_FLAGS PIO_PERIPH_A 607 #define SDRAM_SDA10_FLAGS PIO_PERIPH_C 608 #define SDRAM_D_FLAGS PIO_PERIPH_A 609 610 611 /*----------------------------------------------------------------------------*/ 612 #endif /* _SAMV71_XLTRA_H_ */ 613