1 /* 2 * Copyright (c) 2023, Aspeed Technology Inc. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <platform_reg.h> 13 14 #define PLATFORM_STACK_SIZE UL(0x1000) 15 16 /* cpu topology */ 17 #define PLATFORM_SYSTEM_COUNT U(1) 18 #define PLATFORM_CLUSTER_COUNT U(1) 19 #define PLATFORM_CORE_PRIMARY U(0) 20 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) 21 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 22 PLATFORM_CORE_COUNT_PER_CLUSTER) 23 24 /* arch timer */ 25 #define PLAT_SYSCNT_CLKIN_HZ U(1600000000) 26 27 /* power domain */ 28 #define PLAT_MAX_PWR_LVL U(1) 29 #define PLAT_NUM_PWR_DOMAINS U(5) 30 #define PLAT_MAX_RET_STATE U(1) 31 #define PLAT_MAX_OFF_STATE U(2) 32 33 /* cache line size */ 34 #define CACHE_WRITEBACK_SHIFT U(6) 35 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 36 37 /* translation tables */ 38 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) 39 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 40 #define MAX_XLAT_TABLES U(8) 41 #define MAX_MMAP_REGIONS U(32) 42 43 /* BL31 region */ 44 #define BL31_BASE ULL(0x430000000) 45 #define BL31_SIZE SZ_512K 46 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 47 48 /* BL32 region */ 49 #define BL32_BASE BL31_LIMIT 50 #define BL32_SIZE SZ_16M 51 #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 52 53 /* console */ 54 #define CONSOLE_UART_BASE UART12_BASE 55 #define CONSOLE_UART_CLKIN_HZ U(1846153) 56 #define CONSOLE_UART_BAUDRATE U(115200) 57 58 #endif /* PLATFORM_DEF_H */ 59