1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_SIP_SVC_H 8 #define SOCFPGA_SIP_SVC_H 9 10 11 /* SiP status response */ 12 #define INTEL_SIP_SMC_STATUS_OK 0 13 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 14 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 15 #define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3 16 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 17 #define INTEL_SIP_SMC_RSU_ERROR 0x7 18 #define INTEL_SIP_SMC_SEU_ERR_READ_ERROR 0x8 19 20 /* SiP mailbox error code */ 21 #define GENERIC_RESPONSE_ERROR 0x3FF 22 23 /* SiP V2 command code range */ 24 #define INTEL_SIP_SMC_CMD_MASK 0xFFFF 25 #define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400 26 #define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF 27 28 /* SiP V2 protocol header */ 29 #define INTEL_SIP_SMC_HEADER_JOB_ID_MASK 0xF 30 #define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET 0U 31 #define INTEL_SIP_SMC_HEADER_CID_MASK 0xF 32 #define INTEL_SIP_SMC_HEADER_CID_OFFSET 4U 33 #define INTEL_SIP_SMC_HEADER_VERSION_MASK 0xF 34 #define INTEL_SIP_SMC_HEADER_VERSION_OFFSET 60U 35 36 /* SMC SiP service function identifier for version 1 */ 37 38 /* FPGA Reconfig */ 39 #define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 40 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 41 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 42 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 43 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 44 45 /* FPGA Bitstream Flag */ 46 #define FLAG_PARTIAL_CONFIG BIT(0) 47 #define FLAG_AUTHENTICATION BIT(1) 48 #define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \ 49 == FLAG_##_type) 50 51 /* Secure Register Access */ 52 #define INTEL_SIP_SMC_REG_READ 0xC2000007 53 #define INTEL_SIP_SMC_REG_WRITE 0xC2000008 54 #define INTEL_SIP_SMC_REG_UPDATE 0xC2000009 55 56 /* Remote System Update */ 57 #define INTEL_SIP_SMC_RSU_STATUS 0xC200000B 58 #define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C 59 #define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E 60 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F 61 #define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010 62 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011 63 #define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012 64 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013 65 #define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014 66 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015 67 68 /* Hardware monitor */ 69 #define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020 70 #define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021 71 #define TEMP_CHANNEL_MAX (1 << 15) 72 #define VOLT_CHANNEL_MAX (1 << 15) 73 74 /* ECC */ 75 #define INTEL_SIP_SMC_ECC_DBE 0xC200000D 76 77 /* Generic Command */ 78 #define INTEL_SIP_SMC_SERVICE_COMPLETED 0xC200001E 79 #define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F 80 #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 81 #define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040 82 83 #define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E 84 85 /* Mailbox Command */ 86 #define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200003C 87 #define INTEL_SIP_SMC_GET_USERCODE 0xC200003D 88 89 /* FPGA Crypto Services */ 90 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A 91 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F 92 #define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B 93 #define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090 94 #define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C 95 #define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D 96 #define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E 97 #define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F 98 #define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064 99 #define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065 100 #define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066 101 #define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067 102 #define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068 103 #define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069 104 #define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E 105 #define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F 106 #define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070 107 #define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071 108 #define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072 109 #define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073 110 #define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074 111 #define INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE 0x42000075 112 #define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076 113 #define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077 114 #define INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE 0xC2000078 115 #define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079 116 #define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE 0x42000091 117 #define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE 0x42000092 118 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A 119 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE 0xC200007B 120 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C 121 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE 0x42000093 122 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE 0x42000094 123 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D 124 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F 125 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080 126 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE 0xC2000081 127 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082 128 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE 0x42000095 129 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE 0x42000096 130 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083 131 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085 132 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086 133 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE 0xC2000087 134 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088 135 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE 0x42000097 136 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE 0x42000098 137 #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089 138 #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B 139 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C 140 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E 141 142 /* SEU ERR */ 143 #define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099 144 #define INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR 0xC200009A 145 146 #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF 147 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF 148 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U 149 #define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF 150 151 /* ECC DBE */ 152 #define WARM_RESET_WFI_FLAG BIT(31) 153 #define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\ 154 SYSMGR_ECC_DDR0_MASK |\ 155 SYSMGR_ECC_DDR1_MASK) 156 157 /* Non-mailbox SMC Call */ 158 #define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 159 160 /** 161 * SMC SiP service function identifier for version 2 162 * Command code from 0x400 ~ 0x4FF 163 */ 164 165 /* V2: Non-mailbox function identifier */ 166 #define INTEL_SIP_SMC_V2_GET_SVC_VERSION 0xC2000400 167 #define INTEL_SIP_SMC_V2_REG_READ 0xC2000401 168 #define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402 169 #define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403 170 #define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404 171 #define INTEL_SIP_SMC_V2_RSU_UPDATE_ADDR 0xC2000405 172 173 /* V2: Mailbox function identifier */ 174 #define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND 0xC2000420 175 #define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE 0xC2000421 176 177 /* SMC function IDs for SiP Service queries */ 178 #define SIP_SVC_CALL_COUNT 0x8200ff00 179 #define SIP_SVC_UID 0x8200ff01 180 #define SIP_SVC_VERSION 0x8200ff03 181 182 /* SiP Service Calls version numbers */ 183 /* 184 * Increase if there is any backward compatibility impact 185 */ 186 #define SIP_SVC_VERSION_MAJOR 2 187 /* 188 * Increase if there is new SMC function ID being added 189 */ 190 #define SIP_SVC_VERSION_MINOR 2 191 192 193 /* Structure Definitions */ 194 struct fpga_config_info { 195 uint32_t addr; 196 int size; 197 int size_written; 198 uint32_t write_requested; 199 int subblocks_sent; 200 int block_number; 201 }; 202 203 typedef enum { 204 NO_REQUEST = 0, 205 RECONFIGURATION, 206 BITSTREAM_AUTH 207 } config_type; 208 209 /* Function Definitions */ 210 bool is_size_4_bytes_aligned(uint32_t size); 211 bool is_address_in_ddr_range(uint64_t addr, uint64_t size); 212 213 /* ECC DBE */ 214 bool cold_reset_for_ecc_dbe(void); 215 uint32_t intel_ecc_dbe_notification(uint64_t dbe_value); 216 217 /* Secure register access */ 218 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval); 219 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 220 uint32_t *retval); 221 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 222 uint32_t val, uint32_t *retval); 223 224 /* Set RSU update address*/ 225 uint32_t intel_rsu_update(uint64_t update_address); 226 227 /* Miscellaneous HPS services */ 228 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask); 229 230 /* SiP Service handler for version 2 */ 231 uintptr_t sip_smc_handler_v2(uint32_t smc_fid, 232 u_register_t x1, 233 u_register_t x2, 234 u_register_t x3, 235 u_register_t x4, 236 void *cookie, 237 void *handle, 238 u_register_t flags); 239 240 #endif /* SOCFPGA_SIP_SVC_H */ 241