1 /* Copyright 2014 The ChromiumOS Authors 2 * Use of this source code is governed by a BSD-style license that can be 3 * found in the LICENSE file. 4 */ 5 6 #ifndef __CROS_EC_BOARD_H 7 #define __CROS_EC_BOARD_H 8 9 #define CONFIG_LTO 10 11 /* 12 * The default watchdog timeout is 1.6 seconds, but there are some legitimate 13 * flash-intensive TPM operations that actually take close to that long to 14 * complete. Make sure we don't trigger the watchdog accidentally if the timing 15 * is just a little off. 16 */ 17 #undef CONFIG_WATCHDOG_PERIOD_MS 18 #define CONFIG_WATCHDOG_PERIOD_MS 5000 19 20 /* Features that we don't want */ 21 #undef CONFIG_CMD_LID_ANGLE 22 #undef CONFIG_CMD_POWERINDEBUG 23 #undef CONFIG_DMA_DEFAULT_HANDLERS 24 #undef CONFIG_FMAP 25 #undef CONFIG_HIBERNATE 26 #undef CONFIG_LID_SWITCH 27 #undef CONFIG_CMD_SYSINFO 28 #undef CONFIG_CMD_SYSJUMP 29 #undef CONFIG_CMD_SYSLOCK 30 31 #define CONFIG_CUSTOMIZED_RO 32 /* TODO: find a way to drop RO build. */ 33 #define CONFIG_FW_INCLUDE_RO 34 35 #ifndef CR50_DEV 36 /* Disable stuff that should only be in debug builds */ 37 #undef CONFIG_CMD_CRASH 38 #undef CONFIG_CMD_MD 39 #undef CONFIG_CMD_RW 40 #undef CONFIG_CMD_SLEEPMASK_SET 41 #undef CONFIG_CMD_WAITMS 42 #undef CONFIG_FLASH 43 #else 44 /* 45 * Add chargen to standard TOT images. The DBG image doesn't have enough room 46 * for it. 47 */ 48 #define CONFIG_CMD_CHARGEN 49 #endif 50 51 #if defined(H1_RED_BOARD) || defined(CR50_DEV) 52 #define CONFIG_USB_SELECT_PHY 53 #endif 54 55 /* Enable getting gpio flags to tell if open drain pins are asserted */ 56 #define CONFIG_GPIO_GET_EXTENDED 57 /* Disable sleep when gpios with GPIO_SLEEP_DIS flags are asserted. */ 58 #define CONFIG_GPIO_DISABLE_SLEEP 59 60 /* Flash configuration */ 61 #undef CONFIG_FLASH_PSTATE 62 #define CONFIG_WP_ALWAYS 63 #define CONFIG_CMD_FLASH 64 65 #define CONFIG_CRC8 66 67 /* We're using TOP_A for partition 0, TOP_B for partition 1 */ 68 #define CONFIG_FLASH_NVMEM 69 /* Offset to start of NvMem area from base of flash */ 70 #define CONFIG_FLASH_NVMEM_OFFSET_A (CFG_TOP_A_OFF) 71 #define CONFIG_FLASH_NVMEM_OFFSET_B (CFG_TOP_B_OFF) 72 /* Address of start of Nvmem area */ 73 #define CONFIG_FLASH_NVMEM_BASE_A \ 74 (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_NVMEM_OFFSET_A) 75 #define CONFIG_FLASH_NVMEM_BASE_B \ 76 (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_NVMEM_OFFSET_B) 77 #define CONFIG_FLASH_NEW_NVMEM_BASE_A \ 78 (CONFIG_FLASH_NVMEM_BASE_A + CONFIG_FLASH_BANK_SIZE) 79 #define CONFIG_FLASH_NEW_NVMEM_BASE_B \ 80 (CONFIG_FLASH_NVMEM_BASE_B + CONFIG_FLASH_BANK_SIZE) 81 82 /* Size partition in NvMem */ 83 #define NVMEM_PARTITION_SIZE (CFG_TOP_SIZE) 84 #define NEW_NVMEM_PARTITION_SIZE (NVMEM_PARTITION_SIZE - CONFIG_FLASH_BANK_SIZE) 85 #define NEW_NVMEM_TOTAL_PAGES \ 86 (2 * NEW_NVMEM_PARTITION_SIZE / CONFIG_FLASH_BANK_SIZE) 87 /* Size in bytes of NvMem area */ 88 #define CONFIG_FLASH_LOG 89 #define CONFIG_FLASH_NVMEM_SIZE (NVMEM_PARTITION_SIZE * NVMEM_NUM_PARTITIONS) 90 /* Enable <key, value> variable support. */ 91 #define CONFIG_FLASH_NVMEM_VARS 92 #define NVMEM_CR50_SIZE 272 93 #define CONFIG_FLASH_NVMEM_VARS_USER_SIZE NVMEM_CR50_SIZE 94 95 /* Go to sleep when nothing else is happening */ 96 #define CONFIG_LOW_POWER_IDLE 97 98 /* Allow multiple concurrent memory allocations. */ 99 #define CONFIG_MALLOC 100 101 /* Enable debug cable detection */ 102 #define CONFIG_RDD 103 104 /* Also use the cr50 as a second factor authentication */ 105 #define CONFIG_U2F 106 107 /* Additional FIPS KAT tests. */ 108 #define CONFIG_FIPS_RSA2048 109 #define CONFIG_FIPS_SW_HMAC_DRBG 110 #define CONFIG_FIPS_AES_CBC_256 111 112 /* USB configuration */ 113 #define CONFIG_USB 114 #define CONFIG_USB_CONSOLE_STREAM 115 #undef CONFIG_USB_CONSOLE_TX_BUF_SIZE 116 #define CONFIG_USB_CONSOLE_TX_BUF_SIZE 4096 117 #define CONFIG_USB_I2C 118 #define CONFIG_USB_INHIBIT_INIT 119 #define CONFIG_USB_SPI_V2 120 #define CONFIG_USB_SERIALNO 121 #define DEFAULT_SERIALNO "0" 122 123 #define CONFIG_STREAM_USART 124 #define CONFIG_STREAM_USB 125 #define CONFIG_STREAM_USART1 126 #define CONFIG_STREAM_USART2 127 128 /* Enable Case Closed Debugging */ 129 #define CONFIG_CASE_CLOSED_DEBUG_V1 130 #define CONFIG_PHYSICAL_PRESENCE 131 /* Loosen CCD open requirements. Only allowed in prePVT images */ 132 #define CONFIG_CCD_OPEN_PREPVT 133 134 #ifdef CR50_DEV 135 /* Remove console commands to save space. */ 136 #undef CONFIG_CMD_SLEEPMASK 137 #undef CONFIG_CMD_TIMERINFO 138 #undef CONFIG_CONSOLE_HISTORY 139 #undef CONFIG_CMD_I2C_SCAN 140 #undef CONFIG_CMD_I2C_XFER 141 #undef CONFIG_FLASH 142 /* Enable unsafe dev features for CCD in dev builds */ 143 #define CONFIG_CASE_CLOSED_DEBUG_V1_UNSAFE 144 #define CONFIG_CMD_FLASH_LOG 145 #define CONFIG_PHYSICAL_PRESENCE_DEBUG_UNSAFE 146 #define CONFIG_CMD_ROLLBACK 147 #endif 148 149 #define CONFIG_USB_PID 0x5014 150 #define CONFIG_USB_SELF_POWERED 151 152 #undef CONFIG_USB_MAXPOWER_MA 153 #define CONFIG_USB_MAXPOWER_MA 0 154 155 /* Need to be able to bitbang the EC UART for updates through CCD. */ 156 #define CONFIG_UART_BITBANG 157 158 /* Enable SPI controller (SPI) module */ 159 #define CONFIG_SPI_CONTROLLER 160 #define CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS 161 #define CONFIG_SPI_FLASH_PORT 0 162 163 /* Enable SPI peripheral (SPP) module */ 164 #define CONFIG_SPP 165 #define CONFIG_TPM_SPP 166 167 #define CONFIG_RBOX 168 #define CONFIG_RBOX_WAKEUP 169 170 /* We don't need to send events to the AP */ 171 #undef CONFIG_HOSTCMD_EVENTS 172 173 /* Make most commands restricted */ 174 #define CONFIG_CONSOLE_COMMAND_FLAGS 175 #define CONFIG_RESTRICTED_CONSOLE_COMMANDS 176 #define CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT CMD_FLAG_RESTRICTED 177 178 /* Inject the fips checksum into the image. */ 179 #define CONFIG_FIPS_CHECKSUM 180 /* Include crypto stuff, both software and hardware. Enable optimizations. */ 181 /* Use board specific version of dcrypto */ 182 #define CONFIG_FIPS_UTIL 183 #define CONFIG_DCRYPTO_BOARD 184 #define CONFIG_UPTO_SHA512 185 #define CONFIG_DCRYPTO_RSA_SPEEDUP 186 187 /** 188 * Make sw version equal to hw. Unlike SHA2-256, dcrypto implementation 189 * of SHA2-512/384 allows to save context, so can fully replace software 190 * implementation. 191 */ 192 #define CONFIG_SHA512_HW_EQ_SW 193 194 /* Don't link with third_party/cryptoc. */ 195 #undef CONFIG_LIBCRYPTOC 196 197 /* Don't use DCRYPTO code from chip/g. */ 198 #undef CONFIG_DCRYPTO 199 200 /* 201 * This is pretty arbitrary, a rough estimate of what's required for smooth 202 * Cr50 operation. 203 */ 204 #ifndef CRYPTO_TEST_SETUP 205 #define CONFIG_SHAREDMEM_MINIMUM_SIZE 5500 206 #else 207 /* Crypto tests require more statically allocated memory. */ 208 #define CONFIG_SHAREDMEM_MINIMUM_SIZE 5000 209 #endif 210 211 /* Implement custom udelay, due to usec hwtimer imprecision. */ 212 #define CONFIG_HW_SPECIFIC_UDELAY 213 214 #ifndef __ASSEMBLER__ 215 #include "common.h" 216 #include "gpio_signal.h" 217 218 /* USB string indexes */ 219 enum usb_strings { 220 USB_STR_DESC = 0, 221 USB_STR_VENDOR, 222 USB_STR_PRODUCT, 223 USB_STR_VERSION, 224 USB_STR_CONSOLE_NAME, 225 USB_STR_BLOB_NAME, 226 USB_STR_HID_KEYBOARD_NAME, 227 USB_STR_AP_NAME, 228 USB_STR_EC_NAME, 229 USB_STR_UPGRADE_NAME, 230 USB_STR_SPI_NAME, 231 USB_STR_SERIALNO, 232 USB_STR_I2C_NAME, 233 234 USB_STR_COUNT 235 }; 236 237 /* 238 * Device states 239 * 240 * Note that not all states are used by all devices. 241 */ 242 enum device_state { 243 /* Initial state at boot */ 244 DEVICE_STATE_INIT = 0, 245 246 /* 247 * Detect was not asserted at boot, but we're not willing to give up on 248 * the device right away so we're debouncing to see if it shows up. 249 */ 250 DEVICE_STATE_INIT_DEBOUNCING, 251 252 /* 253 * Device was detected at boot, but we can't enable transmit yet 254 * because that would interfere with detection of another device. 255 */ 256 DEVICE_STATE_INIT_RX_ONLY, 257 258 /* Disconnected or off, because detect is deasserted */ 259 DEVICE_STATE_DISCONNECTED, 260 DEVICE_STATE_OFF, 261 262 /* Device state is not knowable because we're driving detect */ 263 DEVICE_STATE_UNDETECTABLE, 264 265 /* Connected or on, because detect is asserted */ 266 DEVICE_STATE_CONNECTED, 267 DEVICE_STATE_ON, 268 269 /* 270 * Device was connected, but we saw detect deasserted and are 271 * debouncing to see if it stays deasserted - at which point we'll 272 * decide that it's disconnected. 273 */ 274 DEVICE_STATE_DEBOUNCING, 275 276 /* Device state is unknown. Used only by legacy device_state code. */ 277 DEVICE_STATE_UNKNOWN, 278 279 /* The state is being ignored. */ 280 DEVICE_STATE_IGNORED, 281 282 /* Number of device states */ 283 DEVICE_STATE_COUNT 284 }; 285 286 /** 287 * Return the name of the device state as as string. 288 * 289 * @param state State to look up 290 * @return Name of the state, or "?" if no match. 291 */ 292 const char *device_state_name(enum device_state state); 293 294 /* NVMem variables. */ 295 enum nvmem_vars { 296 NVMEM_VAR_CONSOLE_LOCKED = 0, 297 NVMEM_VAR_TEST_VAR, 298 NVMEM_VAR_U2F_SALT, 299 NVMEM_VAR_CCD_CONFIG, 300 NVMEM_VAR_G2F_SALT, 301 302 NVMEM_VARS_COUNT 303 }; 304 305 void board_configure_deep_sleep_wakepins(void); 306 void ap_detect_asserted(enum gpio_signal signal); 307 void ec_detect_asserted(enum gpio_signal signal); 308 void servo_detect_asserted(enum gpio_signal signal); 309 void tpm_rst_deasserted(enum gpio_signal signal); 310 void tpm_rst_asserted(enum gpio_signal signal); 311 void diom4_deasserted(enum gpio_signal signal); 312 313 void post_reboot_request(void); 314 315 /* Special controls over EC and AP */ 316 void assert_sys_rst(void); 317 void deassert_sys_rst(void); 318 void assert_ec_rst(void); 319 void deassert_ec_rst(void); 320 int is_ec_rst_asserted(void); 321 /* Ignore the servo state. */ 322 void servo_ignore(int enable); 323 324 /** 325 * Set up a deferred call to update CCD state. 326 * 327 * This will enable/disable UARTs, SPI, I2C, etc. as needed. 328 */ 329 void ccd_update_state(void); 330 331 /** 332 * Return the state of the BOARD_USE_PLT_RST board strap option. 333 * 334 * @return 0 if option is not set, !=0 if option set. 335 */ 336 int board_use_plt_rst(void); 337 /** 338 * Return the state of the BOARD_NEEDS_SYS_RST_PULL_UP board strap option. 339 * 340 * @return 0 if option is not set, !=0 if option set. 341 */ 342 int board_rst_pullup_needed(void); 343 /** 344 * Return the state of the BOARD_PERIPH_CONFIG_I2C board strap option. 345 * 346 * @return 0 if option is not set, !=0 if option set. 347 */ 348 int board_tpm_uses_i2c(void); 349 /** 350 * Return the state of the BOARD_PERIPH_CONFIG_SPI board strap option. 351 * 352 * @return 0 if option is not set, !=0 if option set. 353 */ 354 int board_tpm_uses_spi(void); 355 /** 356 * Return the state of the BOARD_CLOSED_SOURCE_SET1 board strap option. 357 * 358 * @return 0 if option is not set, !=0 if option set. 359 */ 360 int board_uses_closed_source_set1(void); 361 /** 362 * The board needs to wait until TPM_RST_L is asserted before deasserting 363 * system reset signals. 364 * 365 * @return 0 if option is not set, !=0 if option set. 366 */ 367 int board_uses_closed_loop_reset(void); 368 /** 369 * The board has all necessary I2C pins connected for INA support. 370 * 371 * @return 0 if option is not set, !=0 if option set. 372 */ 373 int board_has_ina_support(void); 374 /* The board supports EC-CR50 communication. */ 375 int board_has_ec_cr50_comm_support(void); 376 int board_id_is_mismatched(void); 377 /* Allow for deep sleep to be enabled on AP shutdown */ 378 int board_deep_sleep_allowed(void); 379 /* The board uses DIOM4 for user_pres_l */ 380 int board_use_diom4(void); 381 382 /* Set or clear a board property flag in long life scratch. */ 383 void board_write_prop(uint32_t flag, uint8_t enable); 384 385 void power_button_record(void); 386 387 /** 388 * Enable/disable power button release interrupt. 389 * 390 * @param enable Enable (!=0) or disable (==0) 391 */ 392 void power_button_release_enable_interrupt(int enable); 393 394 /* Functions needed by CCD config */ 395 int board_battery_is_present(void); 396 int board_fwmp_allows_boot_policy_update(void); 397 int board_fwmp_allows_unlock(void); 398 void board_fwmp_update_policies(void); 399 int board_vboot_dev_mode_enabled(void); 400 void board_reboot_ap(void); 401 void board_reboot_ec(void); 402 /** 403 * Reboot the EC 404 * @param usec_delay microseconds to delay in rebooting EC. 405 * negative input shall be disregarded. 406 */ 407 void board_reboot_ec_deferred(int usec_delay); 408 void board_closed_loop_reset(void); 409 int board_wipe_tpm(int reset_required); 410 int board_is_first_factory_boot(void); 411 412 int usb_i2c_board_enable(void); 413 void usb_i2c_board_disable(void); 414 415 void print_ap_state(void); 416 void print_ap_uart_state(void); 417 void print_ec_state(void); 418 void print_servo_state(void); 419 420 void pmu_check_tpm_rst(void); 421 int ap_is_on(void); 422 int ap_uart_is_on(void); 423 int ec_is_on(void); 424 int ec_is_rx_allowed(void); 425 int servo_is_connected(void); 426 427 /* 428 * Returns nonzero value if EC reset line is taken over and should not be 429 * touched by the 'standard' EC reset functions. 430 */ 431 int ec_rst_override(void); 432 433 /* 434 * Assert INT_AP_L to acknowledge AP that cr50 is ready for next TPM command. 435 * NOTE: must be called by ISR only. 436 * 437 * Returns 1 if it successfully asserted (or scheduled to assert), or 438 * 0 if the extended long pulse was disabled. 439 */ 440 int assert_int_ap(void); 441 442 /* 443 * Deassert INT_AP_L immediately. 444 * NOTE: must be called by ISR only. 445 */ 446 void deassert_int_ap(void); 447 448 /* Register a function that should be called when INT_AP_L extension starts. */ 449 void int_ap_register(void (*func_enable)(void)); 450 451 void int_ap_extension_enable(void); 452 void int_ap_extension_stop_pulse(void); 453 454 /* Moving from legacy versions might require NVMEM transition. */ 455 int board_nvmem_legacy_check_needed(void); 456 457 void set_ap_on(void); 458 459 /* 460 * Trigger generation of the ITE SYNC sequence on the way up after next 461 * reboot. 462 */ 463 void board_start_ite_sync(void); 464 465 /* 466 * Board specific function (needs information about pinmux settings) which 467 * allows to take the i2cp driver out of the 'wedged' state where the controller 468 * stopped i2c access mid transaction and the periph is holding SDA low. 469 */ 470 void board_unwedge_i2cp(void); 471 472 int board_in_prod_mode(void); 473 474 /* Bit masks for each bit in TPM_BOARD_CFG register */ 475 enum board_cfg_reg_bitmask { 476 BOARD_CFG_LONG_INT_AP_BIT = BIT(0), 477 478 BOARD_CFG_LOCKED_BIT = BIT(31), 479 }; 480 481 /* Disable write on TPM_BOARD_CFG register. */ 482 void board_cfg_reg_write_disable(void); 483 484 /* 485 * Write on TPM_BOARD_CFG register if BOARD_CFG_LOCKED_BIT is clear. 486 * 487 * @param value: value to write on TPM_BOARD_CFG 488 */ 489 void board_cfg_reg_write(unsigned int value); 490 491 /* 492 * Read TPM_BOARD_CFG register. 493 * 494 * @param TPM_BOARD_CFG register value in uint32_t type. 495 */ 496 unsigned int board_cfg_reg_read(void); 497 498 #endif /* !__ASSEMBLER__ */ 499 500 /* USB interface indexes (use define rather than enum to expand them) */ 501 #define USB_IFACE_CONSOLE 0 502 #define USB_IFACE_AP 1 503 #define USB_IFACE_EC 2 504 #define USB_IFACE_UPGRADE 3 505 #define USB_IFACE_SPI 4 506 #define USB_IFACE_I2C 5 507 #define USB_IFACE_COUNT 6 508 509 /* USB endpoint indexes (use define rather than enum to expand them) */ 510 #define USB_EP_CONTROL 0 511 #define USB_EP_CONSOLE 1 512 #define USB_EP_AP 2 513 #define USB_EP_EC 3 514 #define USB_EP_UPGRADE 4 515 #define USB_EP_SPI 5 516 #define USB_EP_I2C 6 517 #define USB_EP_COUNT 7 518 519 /* UART indexes (use define rather than enum to expand them) */ 520 #define UART_CR50 0 521 #define UART_AP 1 522 #define UART_EC 2 523 #define UART_NULL 0xff 524 525 #define UARTN UART_CR50 526 527 #define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_TPM)) 528 529 /* Nv Memory users */ 530 #ifndef __ASSEMBLER__ 531 enum nvmem_users { NVMEM_TPM = 0, NVMEM_CR50, NVMEM_NUM_USERS }; 532 #endif 533 534 #define CONFIG_FLASH_NVMEM_VARS_USER_NUM NVMEM_CR50 535 #define CONFIG_RW_B 536 537 #define CONFIG_AP_RO_VERIFICATION 538 #define CONFIG_SPI_HASH 539 540 /* Firmware upgrade options. */ 541 #define CONFIG_NON_HC_FW_UPDATE 542 #define CONFIG_USB_FW_UPDATE 543 544 #define CONFIG_I2C 545 #define CONFIG_I2C_CONTROLLER 546 #define CONFIG_I2C_PERIPH 547 #define CONFIG_TPM_I2CP 548 549 #define CONFIG_BOARD_ID_SUPPORT 550 #define CONFIG_SN_BITS_SUPPORT 551 #define CONFIG_EXTENDED_VERSION_INFO 552 553 #define I2C_PORT_CONTROLLER 0 554 555 #define CONFIG_BASE32 556 #define CONFIG_RMA_AUTH 557 #define CONFIG_FACTORY_MODE 558 #define CONFIG_RNG 559 560 #define CONFIG_EC_EFS_SUPPORT 561 #define CONFIG_EC_EFS2_VERSION 0 562 563 #define CONFIG_ENABLE_H1_ALERTS 564 565 /* Enable hardware backed brute force resistance feature */ 566 #define CONFIG_PLATFORM_PINWEAVER 567 568 /* 569 * Disabling p256 will result in RMA Auth falling back to the x25519 curve 570 * which in turn would require extra 5328 bytes of flash space. 571 */ 572 #define CONFIG_RMA_AUTH_USE_P256 573 #ifndef CONFIG_RMA_AUTH_USE_P256 574 #define CONFIG_CURVE25519 575 #endif 576 577 #define CONFIG_CCD_ITE_PROGRAMMING 578 579 /* 580 * Increase sizes of USB over I2C read and write queues. Sizes are are such 581 * that when appropriate overheads are included, total buffer sizes are powers 582 * of 2 (2^9 in both cases below). 583 */ 584 #undef CONFIG_USB_I2C_MAX_WRITE_COUNT 585 #undef CONFIG_USB_I2C_MAX_READ_COUNT 586 #define CONFIG_USB_I2C_MAX_WRITE_COUNT 508 587 #define CONFIG_USB_I2C_MAX_READ_COUNT 506 588 589 /* The below time constants are way longer than should be required in practice: 590 * 591 * Time it takes to finish processing TPM command 592 */ 593 #define TPM_PROCESSING_TIME (1 * SECOND) 594 595 /* 596 * Time it takse TPM reset function to wipe out the NVMEM and reboot the 597 * device. 598 */ 599 #define TPM_RESET_TIME (10 * SECOND) 600 601 /* Total time deep sleep should not be allowed while wiping the TPM. */ 602 #define DISABLE_SLEEP_TIME_TPM_WIPE (TPM_PROCESSING_TIME + TPM_RESET_TIME) 603 604 /*****************************************************************************/ 605 /* 606 * Options for CRYPTO_TEST=1 images. Crypto test support takes up more space 607 * than the standard image has available. Use this section to add crypto test 608 * features and remove things to free up enough space to build them. 609 */ 610 #ifdef CRYPTO_TEST_SETUP 611 /* Enable unsafe dev features for CCD in crypto test builds */ 612 #define CONFIG_CMD_ROLLBACK 613 614 /* Remove console commands to save space */ 615 #undef CONFIG_CMD_ECRST 616 #undef CONFIG_CMD_SYSRST 617 #undef CONFIG_CMD_WP 618 #undef CONFIG_CMD_DUMP_NVMEM 619 #undef CONFIG_CMD_PINMUX 620 #undef CONFIG_CMD_GPIOCFG 621 #undef CONFIG_CMD_SLEEPMASK 622 #undef CONFIG_CMD_TIMERINFO 623 #undef CONFIG_CONSOLE_HISTORY 624 #undef CONFIG_I2C_XFER 625 #undef CONFIG_I2C_SCAN 626 #undef CONFIG_CONSOLE_CMDHELP 627 628 /* Remove features crypto test doesn't use to save space */ 629 #undef CONFIG_AP_RO_VERIFICATION 630 #undef CONFIG_SPI_HASH 631 #endif /* CRYPTO_TEST_SETUP */ 632 #endif /* __CROS_EC_BOARD_H */ 633