1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_COMMON_BLOCK_SMM 4 bool 5 help 6 Intel Processor common SMM support 7 8config SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP 9 bool 10 help 11 Intel Processor trap flag if it is supported 12 13config SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS 14 bool 15 help 16 Enable locking of security-sensitive SoC and mainboard GPIOs. 17 An SoC may provide a list of gpios to lock, and the mainboard 18 may also provide a list of gpios to lock. 19 20config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE 21 bool 22 default n 23 help 24 Disable eSPI SMI source to prevent the embedded controller 25 from asserting SMI while in firmware. 26 27config SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE 28 bool "Enable TCO SMI" 29 default n 30 help 31 Enable TCO SMI source to e.g. handle case instrusion. 32 33config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS 34 int 35 default 100 if CHROMEOS 36 default 0 37 help 38 Time in milliseconds that SLP_SMI for S5 waits for before 39 enabling sleep. This is required to avoid any race between 40 SLP_SMI and PWRBTN SMI. 41 42config HECI_DISABLE_USING_SMM 43 bool 44 depends on SOC_INTEL_COMMON_BLOCK_SMM 45 default n 46 help 47 HECI disable using SMM. Select this option to make HECI disable 48 using SMM mode, independent of dedicated UPD to perform HECI disable. 49 50config PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B 51 bool 52 depends on SOC_INTEL_COMMON_BLOCK_SMM 53 default n 54 help 55 Intel Core processors select the periodic SMI rate via GEN_PMCON_A. 56 On Intel Atom processors the register is different and they use 57 GEN_PMCON_B/GEN_PMCON2 with different address. 58