xref: /aosp_15_r20/external/coreboot/src/soc/intel/common/block/gpio/Kconfig (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1## SPDX-License-Identifier: GPL-2.0-only
2
3config SOC_INTEL_COMMON_BLOCK_GPIO
4	bool
5	select HAVE_DEBUG_GPIO
6	select HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT
7	help
8	  Intel Processor common GPIO support
9
10if SOC_INTEL_COMMON_BLOCK_GPIO
11
12# Use to program Interrupt Polarity Control (IPCx) register
13# Each bit represents IRQx Active High Polarity Disable configuration:
14# when set to 1, the interrupt polarity associated with IRQx is inverted
15# to appear as Active Low to IOAPIC and vice versa
16config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
17	bool
18	default n
19
20# Used to configure Pad Tolerance as 1.8V or 3.3V
21config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
22	bool
23	default n
24
25# Used to configure IOSSTATE and IOSTERM
26config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
27	bool
28	default n
29
30# Indicate if multiple ACPI devices are used for each gpio community.
31config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
32	bool
33	default n
34
35# Indicate if SoC supports dual-routing of GPIOs (to different paths like SCI,
36# NMI, SMI, IOAPIC). This is required to support IRQ and wake on the same pad.
37config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
38	bool
39	default n
40
41config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
42	bool
43	default n
44	help
45	  Till ADL PCH,`Pad Configuration Lock` can only be set or cleared
46	  using non-posted sideband write.
47
48config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR
49	bool
50	default n
51	depends on !SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
52	help
53	  SoC user to select this config if `Pad Configuration Lock` can only be set or
54	  cleared using private configuration register (PCR) write.
55	  Starting with MTL SoC, the recommendation is to use PCR for locking down the
56	  GPIO configuration.
57
58# Indicate if SoC supports 4 bits Pad Mode with PAD_CFG_DW0 registers
59config SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS
60	bool
61	default n
62	help
63	 SoC user to select this config if Pad Mode (PMODE) width of PAD_CFG_DW0 regiser
64	 is 4 bits to support Native Function 1 to 15.
65
66endif
67